Extended distance fiber optic interface

I claim:

1. An apparatus comprising:

a. a host computer, at least a portion of said host computer operating in accordance with a first predetermined parallel electrical communication protocol;

b. a peripheral device, at least a portion of said peripheral device operating in accordance with a second predetermined parallel electrical communication protocol;

c. a device controller coupled to said portion of said peripheral device that operates in accordance with said second predetermined parallel electrical communication protocol via a cable and wherein said device controller is located at a variable distance from said host computer of up to 10 kilometers;

d. a fiber optic input/output link coupled to said portion of said host computer that operates in accordance with said first predetermined parallel electrical communication protocol and further coupled to said device controller, said fiber optic input/output link having a length that substantially matches said variable distance from said host computer to said device controller and operates in accordance with a predetermined serial optical communication protocol;

e. first interfacing means coupled to said host computer and further coupled to said fiber optic input/output link for interfacing between said first predetermined parallel electrical communication protocol and said serial optical communication protocol;

f. second interfacing means coupled to said device controller and further coupled to said fiber optic input/output link for interfacing between said second predetermined parallel electrical communication protocol and said serial optical communication protocol; and

g. at least one of said first and second interfacing means further including means for accommodating said variable distance such that said operation of said host computer is independent of said variable distance, said means for accommodating including a buffering means.

2. An apparatus according to claim 1 wherein said first predetermined parallel electrical communication protocol is compatible with an existing electrical interface.

3. An apparatus according to claim 2 wherein said existing electrical interface comprises the Block Multiplexer Channel protocol.

4. An apparatus according to claim 2 wherein said existing electrical interface comprises the ESCON protocol.

5. An apparatus according to claim 1 or 2 or 3 or 4 wherein said device controller further comprises:

a. an additional interface which may be coupled to an additional peripheral device via an additional cable.

6. An apparatus according to claim 5 wherein said additional interface is compatible with Futurebus+.

7. An apparatus according to claim 6 wherein said device controller further comprises an embedded Reduced Instruction Set Computer.

8. An apparatus according to claim 7 wherein said device controller further comprises a disk storage subsystem.

9. An apparatus according to claim 8 wherein said device controller further comprises:

a. means for transferring data directly between said disk storage subsystem and said Futurebus+ interface.

10. An apparatus according to claim 1 wherein said second predetermined parallel electrical communication protocol is compatible with an existing electrical interface.

11. An apparatus according to claim 10 wherein said existing electrical interface comprises the Block Multiplexer Channel protocol.

12. An apparatus according to claim 10 wherein said existing electrical interface comprises the ESCON protocol.

13. An apparatus for transferring data between a host computer having a Block Multiplexer Channel interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a communication interface which is compatible with the Block Multiplexer Channel interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer Block Multiplexer Channel interface to the device controller communication interface; and

c. a memory device located within said device controller for buffering the transferred data to the plurality of peripheral devices.

14. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a Block Multiplexer Channel interface which is compatible with the electrical interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer electrical interface to the device controller Block Multiplexer Channel interface; and

c. a memory device located within said device controller for buffering the transferred data to the plurality of peripheral devices.

15. An apparatus for transferring data between a host computer having an ESCON interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a communication interface which is compatible with the ESCON interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer ESCON interface to the device controller communication interface; and

c. a memory device located within said device controller for buffering the transferred data to the plurality of peripheral devices.

16. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having an ESCON interface which is compatible with the electrical interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer electrical interface to the device controller ESCON interface; and

c. a memory device located within said device controller for buffering the transferred data to the plurality of peripheral devices.

17. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a communication interface which is compatible with the electrical interface, at least one of a plurality of peripheral device interfaces coupled to at least one of the plurality of peripheral devices via at least one of the plurality of peripheral device interfaces, at least another of the plurality of peripheral device interfaces coupled to at least another of the plurality of peripheral devices via at least one of a plurality of FUTUREBUS+ interfaces;

b. a fiber optic medium coupling the host computer electrical interface to the device controller communication interface; and

c. a memory device located within said device controller for buffering the transferred data to the host computer.

18. An apparatus for transferring data between a host computer having a Block Multiplexer Channel interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a communication interface which is compatible with the Block Multiplexer Channel interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer Block Multiplexer Channel interface to the device controller communication interface; and

c. a memory device located within said device controller for buffering the transferred data to the host computer.

19. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a Block Multiplexer Channel interface which is compatible with the electrical interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer electrical interface to the device controller Block Multiplexer Channel interface; and

c. a memory device located within said device controller for buffering the transferred data to the host computer.

20. An apparatus for transferring data between a host computer having an ESCON interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having a communication interface which is compatible with the ESCON interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer ESCON interface to the device controller communication interface; and

c. a memory device located within said device controller for buffering the transferred data to the host computer.

21. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a device controller having an ESCON interface which is compatible with the electrical interface and further having a plurality of peripheral device interfaces coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

b. a fiber optic medium coupling the host computer electrical interface to the device controller ESCON interface; and

c. a memory device located within said device controller for buffering the transferred data to the host computer.

22. An apparatus according to claims 13, 14, 15, 16, 17, 18, 19, 20 or 21 where said memory device is contained within a Reduced Instruction Set Computer.

23. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a host converter having a fiber optic interface, the host converter is coupled to the electrical interface of the host computer and converts the data from an electrical representation to an optical representation;

b. a device controller having a plurality of peripheral device interfaces, the device controller is coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

c. a controller converter having a fiber optic interface, the controller converter is coupled to the device controller and converts the data from an optical representation to an electrical representation;

d. a controller memory device coupled to the controller converter and further coupled to the plurality of peripheral device interfaces for buffering the transferred data to the peripheral devices;

e. a fiber optic medium coupling the fiber optic interface of the host converter to the fiber optic interface of the controller converter; and

f. a protocol controller coupled to the controller converter and further coupled to the controller memory device for controlling the protocol used during the data transfer.

24. An apparatus according to claim 23 wherein the protocol controller provides a FIFPS60 protocol.

25. An apparatus according to claim 23 wherein the protocol controller provides a modified FIFPS60 protocol.

26. An apparatus for transferring data between a host computer having an electrical interface and a plurality of peripheral devices located at a distance of up to 10 kilometers therefrom comprising:

a. a host converter having a fiber optic interface, the host converter is coupled to the electrical interface of the host computer and converts the data from an optical representation to an electrical representation;

b. a device controller having a plurality of peripheral device interfaces, the device controller is coupled to the plurality of peripheral devices via the plurality of peripheral device interfaces;

c. a controller converter having a fiber optic interface, the controller converter is coupled to the device controller and converts the data from an electrical representation to an optical representation;

d. a controller memory device coupled to the controller converter and further coupled to the plurality of peripheral device interfaces for buffering the transferred data from the peripheral devices;

e. a fiber optic medium coupling the fiber optic interface of the host converter to the fiber optic interface of the controller converter; and

f. a protocol controller coupled to the controller converter and further coupled to the controller memory device for controlling the protocol used during the data transfer.

27. An apparatus according to claim 26 wherein the protocol controller provides a FIFPS60 protocol.

28. An apparatus according to claim 26 wherein the protocol controller provides a modified FIFPS60 protocol.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to data transfer techniques for data processing systems and more particularly relates to data transfer over extended distances.

2. Description of the Prior Art

It has been known for some time to transfer digital data between peripheral equipments and host computers. The earliest and most popular medium for such transfers is electrical energy, which flows within a circuit including portions of the host computer, peripheral devices, and interconnecting electrical cables. These data transfers may be serial in nature, which transmit one data bit at a time, or parallel, in which a number of data bits are transmitted simultaneously.

For a given switching speed of an individual electrical circuit, the parallel approach is inherently faster because it transfers multiple data bits simultaneously. This has meant that serial transmissions have tended to be limited to low data rate information paths or to long distances wherein the cost for parallel transmission is prohibitively expensive. Therefore, most modern day data transfers between host computers and associated peripheral devices utilize parallel electrical transmission. A typical protocol for such transmissions is the popular Block Multiplexer Channel (i.e. BMC) utilized by Unisys Corporation. This highly efficient approach transfers data as parallel bytes (along with parity bits) over a first parallel cable and control signals over a second parallel cable. Because these two cables transfer data and control signals only in one direction, a second pair of cables is usually needed for transfers in the opposite direction. The technique provides an effective transfer rate in each direction of nearly 4.5 MB/sec.

A second medium which is gaining popularity for data transmission is fiber optics. In this approach, the digital data is converted to pulses of light which are transferred over a special light conducting fiber optic cable. Because this transmission medium does not experience the same distributed capacitance which delays electrical transmissions, higher data rates can generally be achieved for a given transmission energy. In fact the data transmission rates tend to be sufficiently high, that serial fiber optic transmissions can be utilized to replace parallel electrical transmissions for many host computer to peripheral device transfers.

Regardless of the transmission medium, particular difficulty is experienced with transmission over extended distances. This occurs because of the finite additional time per unit of distance required to transfer the signal. For most practical standardized interfaces, such as Unisys BMC referenced above, a maximum practical distance is specified (e.g. 500 feet). Such a standard maximum length permits defining efficient software and hardware applicable to the majority of interfaces, which transfer data over short distance (i.e. less than 500 feet). A different or supplementary protocol is defined for extended distances (i.e. in excess of 500 feet). This second protocol accommodates the delays associated with the longer transfer time.

A second characteristic of long distance data transfer is signal loss as a function of distance. Whereas this factor also occurs with optical transmission, it is clearly most pronounced with the electrical medium. One component of this electrical loss is purely resistive in nature. Additional driver voltage may be used to compensate. However, a second reactive component (usually capacitive) tends to complicate the problem. The result is that extended distance electrical data interfaces usually employ different and much higher power circuitry in an attempt to lessen the time delays and adverse signal to noise ratios. These non-standard protocols coupled with the non-standard hardware and software present system integration, power dissipation, and reliability problems.

At the corresponding data rates using the optical medium and current fiber optic techniques, extended distance transmission produces time delays over and above shorter distance transmission. However, the corresponding signal losses are not nearly as severe as with the electrical medium. Therefore, systems employing optical transmission techniques up to several miles need compensate only for the additional time delays but need not be concerning with signal losses. However, prior art systems provide this compensation only within the framework of protocols designed expressly for optical transmission. This produces incompatibility with existing hardware, software, and interface standards.

SUMMARY OF THE INVENTION

The present invention overcomes the disadvantages of the prior art systems by providing a fiber optic data transmission interface technique, which may transfer data over extended distances, yet maintain functional compatibility with existing interface standards for both electrical and optical data transmission. These advantages are provided through the use of a standardized controller along with modularized interfaces for the various existing and new interface protocols.

The standardized controller incorporates a microprogrammed, high performance, Reduced Instruction Set Computer (RISC). The architecture of the present system will readily accommodate RISC clock rates up to 50 MHz. Through the use of buffering, the standardized controller with its embedded RISC can readily compensate for the delays associated with extended distance data transmission. In this way, channel extender usage is made transparent to user hardware and software.

The modularized interfaces contain all of the protocol specific logic required to transfer data in the corresponding format. Though the preferred embodiment of the present invention utilizes Unisys BMC and Futurebus+ (IEEE standard for optical medium), clearly other existing and new protocols are equally applicable.

For the BMC standard interface, for example, a fiber optic protocol is established which transparently appears as electrical transmission to the user (see also the above referenced, commonly assigned U.S. patent application). The single chip modularized interface operates in a minimum mode (MIN) permitting transfers up to 500 feet, whereas switching to the maximum mode (MAX) accommodates transmission and reception up to 10 kilometers. The standardized controller containing the embedded RISC automatically compensates for the differences in delay times between these two modes to render them transparent to the user of the data.

Integration of the standardized controller with Futurebus+ and storage controller subsystems ensures that data transfers amongst peripheral device subsystems may be accomplished without attention from the host computer. Input spooling and processing of spooled output data are typical applications.

One object of the present invention is to provide a Futurebus+based single circuit board storage controller including SCSI RAIDS Array Controller and BMC extender controller using fiber optics. The modified BMC protocol provides smooth upward migration and downward compatibility.

A second objective of the present invention is to provide a unique architecture for a high performance storage controller. A further objective is to introduce an improved and scalable storage controller. A yet further objective of the present invention is to provide a novel input/output controller system which can be interfaced easily to an existing network environment using fiber optics as the transmission medium, with existing and yet to be defined interface protocols.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects of the present invention and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof and wherein:

FIG. 1 is a conceptualized diagram of the present invention;

FIG. 2 is a basic block diagram of the device controller;

FIG. 3 is a block diagram of the elements of the Futurebus+ interface;

FIG. 4 is a block diagram of the elements of the Host Computer BMC interface employing the optical medium;

FIG. 5 is a block diagram of the elements of the Device Controller BMC interface employing the optical medium;

FIG. 6 is a block diagram of the disk subsystem controller;

FIG. 7 is a flow chart of the transmission protocol logic for a Host Computer initiated transfer;

FIG. 8 is a timing diagram for the transfer of FIG. 7;

FIG. 9 is a flow chart of the transmission protocol logic for a Device Controller initiated transfer;

FIG. 10 is a timing diagram for the transfer of FIG. 9;

FIG. 11 is a schematic diagram of the connections to the RISC chip;

FIG. 12 is a schematic diagram of the connections to the level conversion transceiver;

FIG. 13 is a schematic diagram of the connections to the arithmetic co-processor;

FIG. 14 is a schematic diagram of the control logic;

FIG. 15 is a schematic diagram of additional control logic;

FIG. 16 is a schematic of the instruction flash memory;

FIG. 17 is a schematic diagram of the data/instruction (SRAM) buffer memory;

FIG. 18 is a schematic diagram of the data/instruction buffer memory drivers;

FIG. 19 is a schematic diagram of the working stack;

FIG. 20 is a schematic diagram of the buffer memory;

FIG. 21 is a schematic diagram of the Futurebus+ address/data interface;

FIG. 22 is a schematic diagram of the Futurebus+ interface circuitry;

FIG. 23 is a schematic diagram of the Futurebus+ parallel protocol controller;

FIG. 24 is a schematic diagram of the Futurebus+ data path controller;

FIG. 25 is a schematic diagram of the Futurebus+ arbitrator;

FIG. 26 is a schematic diagram of the disk subsystem/RISC interface;

FIG. 27 is a schematic diagram of the disk subsystem/RISC data path;

FIG. 28 is a schematic diagram of one of the individual disk controllers;

FIG. 29 is a schematic diagram of the disk subsystem buffer memory;

FIG. 30 is a schematic diagram of the SCSI buffer memory address circuit;

FIG. 31 is a schematic diagram of the maintenance port;

FIG. 32 is a schematic diagram of the BMC FIFO's;

FIG. 33 is a basic diagram of the fiber optic driver/receiver circuit;

FIG. 34 is a detailed schematic diagram of the fiber optic driver;

FIG. 35 is a detailed schematic diagram of the fiber optic receiver; and

FIG. 36 is a schematic of the CRC logic.

DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is an overall block diagram of a system employing the present invention. In accordance with this preferred embodiment, fiber optic modified BMC and Futurebus+ interface standards are used. However, those of skill in the art will be readily able to adapt the techniques found herein to yet other existing and new interface standards.

Device controller 10 of the present invention communicates with host computer 12 over fiber optic cables 16 and 18 using a protocol which is compatible with the existing BMC interface standard (see also the above referenced U.S. patent application). As shown in the diagram, fiber optic cables 16 and 18 may be either of minimum length (i.e. 500 feet or less) or may be extended to as much as 10 kilometers. Though device controller 10 and corresponding interface 12 must be switched to maximum mode (MAX) to accommodate the extended distance interface, this relatively long distance is otherwise transparent to the remaining hardware and software of the system as explained below.

The remaining interfaces of device controller 10 include the IEEE standard Futurebus+ 22, which may communicate with any number of different compatible peripherals, and disk array subsystem interface 20, which is explained in more detail below. In addition to the advantages of the present invention apparent in the interface between device controller 10 and host computer 12, considerable advantages accrue to the use of these other interfaces as is explained in more detail below.

FIG. 2 is a detailed block diagram of device controller 10. Embedded RISC 58 is a microprogrammed device which regulates all of the functions of device controller 10. It also provides certain interface to interface transfers without interaction with host computer 12.

Embedded processor 58 employs RISC processor 72 which is preferably a commercially available AM29000 device. Arithmetic processor 72 is electrically coupled as shown herein and is programmed in accordance with the manufacturers suggestions and as further provided herein to perform the desired functions.

Instruction flash memory 76 provides the microcode stream to instruction SRAM 78 via transceivers 88 and busses 80 and 24 at the time of power up. This permits device controller 10 to be down loaded with its unique characteristics because instruction flash memory 76 is a writable EPROM. During operation, instructions are provided to arithmetic processor 72 from instruction SRAM 78 via bus 24. Addressing for instruction flash memory 76 and instruction SRAM is provided via bus 60 which is coupled to bus 90 by high speed address latches 66. Bus 90 also provides addressing information to arithmetic co-processor 70 and working stack 68.

Control logic 86 provides access, arbitration, and reset controls to RISC processor 72 via lines 84, to the Futurebus+ interface circuitry via lines 82 and 100, to the disk subsystem via lines 83, and to the BMC interface circuitry via lines 85. The nature of these control lines is discussed in greater detail below.

Buffer memory 62 is coupled between busses 60 and 24. It is used to temporarily store data in transit between two of the interfaces of device controller 10. Working stack 68, on the other hand, provides the temporary storage for embedded controller 58. Maintenance port 74 provides internal access to embedded controller 58 for maintenance purposes.

Bus 24 is the main internal 36 bit (i.e. 32 data bits and four parity bits) parallel data bus for device controller 10, which makes internal transfers of the external interface data. It is designed to operate at a bandwidth of 100 MB/sec. The remaining internal busses of embedded controller 58 (i.e. bus 90, bus 80, and bus 60) do not include parity for address/data and therefore transfer only 32 parallel address/data bits without parity.

Disk array controller 26 is connected as a RAID 5 configuration. The RAID 5 disk controller 26 interfaces directly with bus 24. The multiplexer 42 provides address/data lines to the SIOP of the disk array controller 26. This is mainly used for device level diagnostic purposes. The multiplexer 42 has data bus 24 and portion 64 as input lines. Transceivers 113 provides the Futurebus+ 22 interface for the bus request (BR) and bus grant (GR) control signals on lines 100A.

The Futurebus+ address and data interface is bidirectional. The data bus 24 and address bus 60 is through data path controller 122. The data path receives or sends multiplexed data and address bus 120 to the Futurebus+ 22 via transceivers 118. Status information uses lines 92 and drivers/receivers 116. Arbitration of Futurebus+ 22 utilizes local arbitration controller 104, lines 106, and drivers/receivers 108.

Local Futurebus+ control is provided by parallel protocol controller 110 via lines 94 for status, via lines 96 and drivers/receivers 114 for commands, and via lines 102 and drivers/receivers 108 for synchronization. The interface between the parallel protocol controller 110 and data path controller 122 is provided via line 98. As explained in more detail below, Futurebus+ 22 is maintained in accordance with the applicable IEEE 896.1 standard.

As explained above (see also FIG. 1), communication between device controller 10 and host computer 12 is via fiber optic cables 16 and 18 using a slightly modi