On-chip voltage controlled oscillator

Claims

What is claimed is:

1. A circuit comprising:

a voltage regulator for rejecting low frequency noise from a regulated power supply, the voltage regulator including a voltage regulator output for providing a noise-attenuated regulated voltage; and

an oscillator, the voltage regulator and the oscillator implemented on a common substrate, the oscillator coupled to the voltage regulator output,

the voltage regulator further including attenuation means, which attenuation means includes a passive filter coupled to the regulated power supply for attenuating high frequency noise from the regulated power supply, and for supplying power from the power supply to the voltage regulator,

wherein the passive filter includes a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator, wherein the noise frequencies are higher than about 5 MHz, the passive filter further including a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz,

wherein the attenuation means further includes means for maintaining an attenuation of at least about -30 dB for noise frequencies in a range from about DC to at least about 800 MHz,

wherein the voltage regulator further includes a band gap circuit and regulator means for providing adequate current to maintain the regulated voltage while preventing noise from passing through the regulator means to the voltage regulator output, the regulator means including a Darlington pair coupled to the voltage regulator output, and a control terminal of the Darlington pair coupled to the band gap circuit for receiving variable current, the band gap circuit coupled to the voltage regulator output and controlling the variable current in response to changes in the regulated voltage,

wherein the oscillator comprises a multivibrator which includes a control voltage input, and capacitors connected in parallel, wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance, and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal, the first transistor coupled to the regulated power supply and to one end of a resistor, another end of the resistor coupled to both a collector and a base of a second transistor, the second transistor coupled to a plurality of transistors to form a multiple output current mirror, the multiple output current mirror coupled to the capacitors connected in parallel.

2. The circuit according to claim 1, wherein the attenuation means further includes an active filter means, the combination of the passive filter and the active filter means for attenuating noise frequencies in a range from about DC to at least about 800 MHz.

3. The circuit of claim 1, wherein:

the second transistor and the plurality of transistors are all coupled together through their bases;

the plurality of transistors includes a third transistor having a collector coupled to one end of the capacitors connected in parallel, and a fourth transistor having a collector coupled to another end of the capacitors connected in parallel; and

the second, third, and fourth transistors are all coupled to ground.

4. The circuit of claim 3, wherein the multivibrator further includes:

a pair of switching transistors coupled to opposite ends of the capacitors connected in parallel; and wherein

the oscillator further comprises:

two outputs each for providing a square wave output which is inverted in relation to the other square wave output, the two outputs each including:

an output transistor having a collector coupled to the voltage regulator output, a base of the output transistor coupled to one of the pair of switching transistors, and an emitter of the output transistor coupled to ground through an output resistor, the emitter of the output transistor providing the square wave output which is inverted in relation to the other square wave output.

5. The circuit of claim 4, wherein the oscillator further comprises:

a DC bias circuit including a second resistor having one end coupled to the voltage regulator output and a second end coupled to a second multiple output current mirror, which second multiple output current mirror is coupled to the capacitors connected in parallel, for supplying a minimum current to the second current mirror for maintaining a minimum oscillation frequency of the multivibrator during an absence of a voltage signal at the control voltage input.

6. The circuit of claim 5, wherein the second multiple output current mirror comprises:

a fifth transistor having a collector coupled to said one end of the capacitors connected in parallel;

a sixth transistor having a collector coupled to said another end of the capacitors connected in parallel;

a seventh transistor having its collector and base coupled to the second resistor; and wherein

the fifth, sixth, and seventh transistors are all coupled together through their bases and are all coupled to ground through their emitters.

7. The circuit of claim 1, wherein the circuit is implemented in an analog PLL, which PLL includes a phase detector coupled to an output of the oscillator and to a signal source.

8. The circuit according to claim 1, wherein the voltage regulator output is coupled to ground through a temperature responsive diode and two resistors, the temperature responsive diode and two resistors all connected in series, for providing a consistent temperature compensated regulated voltage.

9. A circuit comprising:

a voltage regulator coupled to a power supply and including a voltage regulator output for providing a regulated voltage, wherein the voltage regulator includes a passive filter coupled to the power supply for attenuating high frequency noise, the passive filter including a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator and a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz; and

an oscillator, the voltage regulator and the oscillator being implemented on a common substrate, the oscillator coupled to the voltage regulator output, wherein the oscillator comprises a multivibrator which includes a control voltage input and capacitors connected in parallel, wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance, and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal, the first transistor coupled to the power supply and to one end of a resistor, another end of the resistor coupled to both a collector and a base of a second transistor, the second transistor coupled to a plurality of transistors to form a multiple output current mirror, the multiple output current mirror coupled to the capacitors connected in parallel.

10. The circuit of claim 9, wherein:

the second transistor and the plurality of transistors are all coupled together through their bases;

the plurality of transistors includes a third transistor having a collector coupled to one end of the capacitors connected in parallel, and a fourth transistor having a collector coupled to another end of the capacitors connected in parallel; and

the second transistor and the plurality of transistors are all coupled to ground.

11. The circuit of claim 10, wherein the multivibrator further includes:

a pair of switching transistors coupled to opposite ends of the capacitors connected in parallel; and wherein

the oscillator further comprises:

two outputs each for providing a square wave output which is inverted in relation to the other square wave output, the two outputs each including:

an output transistor having a collector coupled to the voltage regulator output, a base of the output transistor coupled to one of the pair of switching transistors, and an emitter of the output transistor coupled to ground through a second resistor, the emitter of the output transistor providing the square wave output which is inverted in relation to the other square wave output.

12. The circuit of claim 11, wherein the oscillator further comprises:

a DC bias circuit including a second resistor having one end coupled to the voltage regulator output and a second end coupled to a multiple output current mirror, which multiple output current mirror is coupled to the capacitors connected in parallel, for supplying a minimum current to the current mirror for maintaining a minimum oscillation frequency of the multivibrator during an absence of a voltage signal at the control voltage input.

13. The circuit of claim 12, wherein the multiple output current mirror comprises:

a fifth transistor having a collector coupled to said one end of the capacitors connected in parallel;

a sixth transistor having a collector coupled to said another end of the capacitors connected in parallel;

a seventh transistor having its collector and base coupled to the second resistor; and wherein

the fifth, sixth, and seventh transistors are all coupled together through their bases and are all coupled to ground through their emitters.

14. The circuit of claim 13, wherein the third and fourth transistors, and the fifth and sixth transistors each consist of a pair of matched transistors, each pair of matched transistors coupled to opposite ends of the capacitors connected in parallel for providing symmetric square wave pulses at each of said two outputs.

15. A circuit comprising:

a voltage regulator coupled to a power supply and including a voltage regulator output for providing a regulated voltage, wherein the voltage regulator includes a passive filter coupled to the power supply for attenuating high frequency noise, the passive filter including a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator and a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz; and

an oscillator, the voltage regulator and the oscillator being implemented on a common substrate, the oscillator coupled to the voltage regulator output, wherein the oscillator comprises a multivibrator which includes a control voltage input and capacitors connected in parallel, wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance, and wherein the oscillator further comprises a DC bias circuit including a resistor having one end coupled to the voltage regulator output and a second end coupled to a multiple output current mirror, which multiple output current mirror is coupled to the capacitors connected in parallel, for supplying a minimum current to the current mirror for maintaining a minimum oscillation frequency of the multivibrator during an absence of a voltage signal at the control voltage input.

16. The circuit of claim 15, wherein the multiple output current mirror comprises:

a first transistor coupled to one end of the capacitors connected in parallel;

a second transistor coupled to another end of the capacitors connected in parallel;

a third transistor having its collector and base coupled to the resistor; and wherein

the first, second, and third transistors are all coupled together through their bases and are all coupled to ground through their emitters.

17. The circuit of claim 15, wherein the DC bias circuit further includes means for lessening the noise sensitivity of the oscillator by improving its transfer characteristic by about 500 MHz of output frequency per volt of the control voltage signal.

18. The circuit of claim 10, wherein the oscillator comprises a maximum number of diode voltage drops from the voltage regulator output to ground, the maximum number of diode voltage drops equal to four.

19. The circuit of claim 9, wherein the circuit is implemented in an analog PLL, which PLL includes a phase detector coupled to an output of the oscillator and to a signal source.

20. A phase locked loop comprising:

a regulated power supply;

a phase detector including means for receiving a signal;

a loop filter coupled to the phase detector for receiving a phase detector output;

a VCO coupled to the regulated power supply and to the loop filter for receiving a loop filter output, the VCO providing a voltage controlled output to the phase detector in response to the loop filter output; and

a voltage regulator coupled to the regulated power supply and to the VCO for rejecting low frequency noise from the regulated power supply and for providing a noise-attenuated regulated voltage to the VCO;

the voltage regulator and the VCO implemented on a common substrate;

wherein, the voltage regulator comprises:

active filter means for attenuating low frequency noise;

a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the active filter means;

a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz;

a band gap circuit;

regulator means for providing adequate current to maintain the regulated voltage while preventing noise from passing through the regulator means to the VCO, the regulator means including:

a Darlington pair coupled to the regulated power supply, an output of the Darlington pair coupled to the VCO, and a control terminal of the Darlington pair coupled to the band gap circuit for receiving variable current, the band gap circuit coupled to the VCO and controlling the variable current in response to changes in the regulated voltage;

further wherein the VCO comprises a multivibrator which includes a control voltage input and capacitors connected in parallel, wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance, and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal, the first transistor coupled to the power supply and to one end of a resistor, another end of the resistor coupled to both a collector and a base of a second transistor, the second transistor coupled to a plurality of transistors to form a multiple output current mirror, the multiple output current mirror coupled to the capacitors connected in parallel.

BACKGROUND OF THE INVENTION

The present invention relates to a voltage controlled oscillator (VCO) circuit suitable for use in a phase locked loop to create an analog phase locked loop with high noise rejection.

On chip VCO's are usually implemented using a multivibrator circuit where the oscillation is controlled by charging and discharging an on-chip capacitor. A common application for such a circuit is in an optical high speed data link, which usually house a serializer VCO and a deserializer VCO on the same module. These VCO's are especially sensitive to power supply noise, other VCO's and data patterns which have the same frequency component as the VCO operating frequency but are asynchronous with each other. This type of noise is referred to as near frequency noise. Enough noise of this kind can override the control voltage input to the VCO and cause the phase locked loop, of which the VCO is a part, to lose phase lock. Noise which contains odd harmonic frequencies of the fundamental will also affect the VCO although the sensitivity is not as dominant as the fundamental frequency.

A previous approach to reduce noise sensitivity was to use passive filtering techniques to filter the high frequency noise using R,L,C networks on the module or external to the module. This approach does not have full frequency band rejection and uses a large number of components.

Another approach is to use a digital phase locked loop, which inherently has better noise immunity. For applications such as high speed (gigahertz) clock recovery the digital phase locked loop cannot be implemented at the speeds desired with present CMOS technology.

It is an object of the present invention to provide a noise immune VCO that can be implemented on-chip and which can supply sufficient transient current and unimpaired AC performance.

It is a further object of the present invention to provide a VCO for use in an analog phase locked loop which is tolerant of near frequency noise.

It is another object of the present invention to provide a VCO for use in an analog phase locked loop which is more tolerant of harmonic noise injected into the power supply of the VCO from other external circuits, acting as noise sources.

SUMMARY OF THE INVENTION

In one aspect of the present invention a voltage controlled oscillator circuit is provided including an oscillator providing an output frequency responsive to a control signal having a minimum frequency clamp to assure operation of the multivibrator at all times. A supply voltage regulator provides a supply voltage to the oscillator. The supply voltage regulator includes a temperature compensated reference voltage and a a regulator loop. The regulator loop includes means for providing adequate current to maintain the regulated voltage. The means for providing adequate current has a first terminal connected to the input of the supply voltage regulator, a second terminal connected to the output of the supply voltage regulator, and a third terminal serving as a control terminal. The regulator loop is responsive to the temperature compensated reference and the supply voltage regulator output voltage. The regulator loop controls the control terminal of the means for providing adequate current at the regulated voltage, so that the series voltage regulator can maintain a constant output voltage. Passive filter means is connected to the input of the supply voltage regulator. The passive filter means removes noise from the supply voltage regulator input having frequencies higher than the regulator loop can respond to, the output of said passive filter means providing power to the regulator loop.

In another aspect of the present invention a voltage controlled oscillator is provided including a multivibrator having first and second switching transistors which are turned on and off, with the transistor being in opposite states relative to one another, responsive to a control current. Capacitor means are connected to the first and second switching transistors to be charged and discharged by the first and second switching transistors, when the switching transistors turn on and off. A variable control current signal varies the charging and discharging current in the capacitor means responsive to an input voltage signal which is coupled to the multivibrator. A fixed current for charging and discharging the capacitor means, maintains a minimum multivibrator frequency thereby assuring operation of the multivibrator even in the absence of the variable control current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an analog phase locked loop with a voltage regulator supplying the VCO in accordance with one aspect of the present invention.

FIG. 2 is a high level part schematic part block diagram of a discrete embodiment of the voltage regulator of FIG. 1.

FIG. 3 shows a schematic representation of an integrated circuit embodiment of the voltage regulator of FIG. 1.

FIG. 4 is a graph showing the input noise attenuation due to passive and active filtering of the voltage supplied to the voltage controlled oscillator versus a logarithmic frequency scale.

FIG. 5 shows a schematic representation of the VCO of FIG. 1 in more detail.

FIG. 6 is a graph showing the small signal phase locked loop gain around the operating point in MHz/volt versus the control voltage of the VCO with and without the use of a DC bias current in the VCO.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawing wherein like numerals indicate like elements throughout and particularly FIG. 1 thereof, an analog phase locked loop (PLL) is shown comprising a phase detector 1, which compares the frequency of an input signal to an output signal provided by a voltage controlled oscillator (VCO) 3 and generates a phase error signal. The phase error signal is provided to a loop filter 5 which provides a control signal to the VCO 3. The output frequency of the VCO is controlled by the control signal from the loop filter 5. Therefore, the PLL loop synchronizes the output signal provided by the VCO with the input signal, labelled data, in frequency as well as in phase. When the two signals are synchronized or locked, the phase error between the VCO output and the data signal is very small or zero. An on-chip voltage regulator 7 with an on module capacitor 9 is supplied by a power supply and provides a regulated voltage to the VCO 3. The PLL can be implemented as a conventional continuous time phase locked loop or a current charge pump (not shown) can be situated between the phase detector 1 and the loop filter 5. The charge pump provides an open circuit state to isolate the loop filter from the charge pump enabling a zero static phase error at steady state.

Referring now to FIG. 2, an embodiment of a voltage regulator is shown. A passive filter shown as two L section filters 11 is shown connected to an active filter/series regulator 13. The L section filters comprise resistors 15, 21, with one end of the resistors serving as the input of the filter and the other end connected through capacitors 17 and 23 to ground. The junction of capacitor 23 and resistor 21 is the output of the filter. The active filter series regulator 13 includes an npn transistor 25 which has its collector connected to the 5 volt supply and its emitter connected through a resistor to the inverting input of an operational amplifier 31 and through a resistor 33 to ground. The passive filter 11 supplies power to the operational amplifier 31. The active filter/series regulator further includes a temperature compensated reference circuit shown as a band gap circuit 35 which provides the reference voltage to the noninverting input of the operational amplifier 31. The voltage divider comprised of resistors 27 and 33 allows a voltage greater than the band gap reference voltage to be regulated. The output of the operational amplifier is connected to the base of the transistor 25. The output of the active filter/series regulator provides a supply voltage to the VCO 3.

In operation, the power supply voltage is filtered by a passive filter comprising resistors 15 and 21 and capacitors 17 and 23. Resistor 15 and capacitor 17 provide high frequency attenuation filtering at frequencies above the response ability of the voltage regulator, since most regulators fail to reject input noise as frequencies increase due to loop roll off limitations. Resistor 21 and capacitor 23 provide an additional high frequency attenuation break for the circuit. The output of the passive filter is used to provide power to the operational amplifier 31. The unfiltered power supply signal is provided to the series pass element 25. The series pass element does not have any voltage gain and also presents a high impedance to its input, so that noise is not passed to the output. The operational amplifier 31, the base and emitter of npn transistor 25 and resistors 27 and 33 form a regulation loop. The operational amplifier 31 compares a signal proportional to the voltage regulator output to the output of the band gap circuit. The operational amplifier output controls the pass element so that sufficient current is supplied to the VCO.

Referring now to FIG. 3 an embodiment of the voltage regulator which drives the VCO 3 is shown which is suitable for implementation as an integrated circuit. Passive filtering is provided to the power supply voltage which is connected to one end of resistor 15. The other end of resistor 15 connected through capacitor 17 to ground and through series connected resistor 21 and capacitor 23 to ground. A resistor 41 is connected at one end to the junction of resistor 21 and capacitor 23, to the anode of a diode 43, and through diode 43 to ground. An npn transistor 45 has its base connected to the anode of diode 43. The collector of transistor 45 is connected to the emitter of pnp transistor 47 and to the base of pnp transistor 51 and to the base of pnp transistor 53. The base of transistor 47 is connected to the collectors of pnp transistor 51 and npn transistor 79. The collector of transistor 47 is connected to ground. Resistors 57 and 61 are both connected at one end to the junction of resistors 21 and capacitor 23. Resistors 57 and 61 are connected at the other end to the emitters of transistor 51 and transistor 53, respectively. The emitter of transistor 45 is connected to the emitter of four parallel connected npn transistors 63, 64, 65, and 66. The bases of transistors 63, 64, 65, and 66 are connected to the base of npn transistor 69. Four parallel connected resistors 73A, 73B, 73C, and 73D are connected between the emitters of transistors 63, 64, 65, and 66, and the emitter of transistor 69. The emitter of transistor 69 is connected through series connected resistors 75A and 75B to ground. Resistors 73A, 73B, 73C, 73D, 75A, and 75B all have the same resistance value and physical aspect ratio (length to width). The collector of transistor 53 is connected