According to a first aspect of the invention, a memory device has a main memory array and a sub memory array. In a single burst, data are read from a series of columns in the main memory array, transferred from one column in the main memory array to one column in the sub memory array, read from a series of columns in the sub memory array, and written into the above-mentioned one column in the main memory array. According to a second aspect of the invention, a memory device has a memory array and separate external data input terminals and output terminals. In a single burst, data are read from a series of columns in the memory array, and written to one of the columns, preferably the last column in the series. Input of the written data is preferably simultaneous with the output of the data read from the column to which the input data are written.

There are provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines, and the plurality of word lines are provided in a direction of the bit line. A sense amplifier array including a plurality of latch circuits is provided in areas between the memory mats arranged in the bit line direction, respectively, and a pair of input/output nodes of which are connected to a pair of bit lines separately placed in the memory mats on both sides of the area, respectively. In this case, for a general memory mat other than both end portions in the bit line direction, word lines in any one of the memory mats are activated, while, for end memory mats provided on both end portions in the bit line direction, word lines of both memory mats are activated together.

A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

A sense amplifier driving line is connected to the source of an N-channel MOS transistor. Accordingly, even if a control signal attains H level, a sub-amplifier will not operate. This is because the sense amplifier driving line and an LIO line pair both attain a precharge potential, and a gate-source voltage of an N-channel MOS transistor attains 0V. Thus, it is not necessary to add a circuit configuration for supplying a signal notifying of activation of a row block, and a semiconductor memory device with a smaller area is obtained.

A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well structure includes at least one P-well in a P-type substrate, a number of N-wells, and a retrograde P-well formed within one of the N-wells. The process for fabricating the triple-well structure includes first implanting boron ions in the P-type substrate. A photomask is subsequently formed for the implantation of phosphorous ions in the region where a P-type MOS transistor is to be fabricated. A high temperature drive-in procedure is then employed to form a P-well and a number of N-wells. A selected area of one of the N-wells where an N-type MOS transistor is defined is then subjected to boron ion implantation, which is followed by an annealing procedure to form the retrograde P-well.