Arrangement of power supply and data input/output pads in semiconductor memory device

Claims

What is claimed is:

1. A semiconductor memory device formed on a chip, comprising:

a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip;

a plurality of data input/output buffer means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, each said data input/output buffer means including a buffer for transmitting and receiving data to and from the corresponding memory block and a pad connected to the buffer; and

a plurality of peripheral buffer means arranged in the vicinity of a center portion in said center region along said first direction for receiving an external signal for accessing said plurality of memory blocks,

said plurality of data input/output buffer means being arranged in a region excluding the vicinity of said center portion.

2. A semiconductor memory device formed on a chip, comprising:

a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip;

a plurality of data input/output buffer means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, and arranged in groups on one side and on another side with respect to a center portion in said center region along said first direction, each said data input/output buffer means including a buffer for transmitting and receiving a data signal to and from the corresponding memory block and a pad connected to the buffer; and

a plurality of power pads arranged adjacent to each respective data input/output buffer means group on each of said one side and said other side for supplying a power source voltage only to an associated data input/output buffer means group.

3. The semiconductor memory device as recited in claim 2, wherein each of said plurality of power pads connects only a power interconnection line for supplying the power source voltage to an associated data input/output buffer means group.

4. The semiconductor memory device as recited in claim 2, wherein

said plurality of data input/output buffer means are aligned on each of said one side and said other side of said center region, and

said plurality of power pads are arranged in said center region so as to sandwich a corresponding data input/output buffer means group therebetween on each of said one side and said other side.

5. The semiconductor memory device as recited in claim 2, further comprising:

a peripheral circuit arranged in the center portion between said one side and said other side of said center region, for receiving an external signal controlling an access to said plurality of memory blocks and for controlling the access to said plurality of memory blocks in response to the received external signal; and

a peripheral power pad arranged exclusively for said peripheral circuit in said center portion for receiving externally applied power source voltage and supplying the received power source voltage to said peripheral circuit.

6. The semiconductor memory device as recited in claim 2, wherein each said power pad includes a power supply pad receiving an external power supply voltage for internal transmission, and a ground pad receiving an external ground potential for internal supply.

7. The semiconductor memory device as recited in claim 2, wherein each said power pad is arranged between data input/output buffer means in each said group of data input/output buffer means.

8. The semiconductor memory device as recited in claim 2, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines in the first direction, and said power pads in each group of data input/output buffer means includes power supply pads supplying a power supply voltage of said power source voltage arranged in alignment with data input/output buffer means on one line of said at least two lines, and ground pads supplying a ground voltage of said power source voltage arranged in alignment with data input/output buffer means on another line of said at least two lines.

9. The semiconductor memory device as recited in claim 2, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines, and said power source voltage comprises one power supply voltage and another power supply voltage and said power pads includes a power supply pad receiving the one power supply voltage for internal transmission and a ground pad receiving the other power supply voltage for internal transmission arranged in each of said at least two lines.

10. The semiconductor memory device as recited in claim 2, wherein said plurality of power pads include power supply pads supplying one power supply voltage and ground pads supplying another power supply voltage, and said plurality of power pads are aligned with said plurality of data input/output buffer means, and at least one data input/output buffer means is inserted between a power supply pad and a ground pad.

11. The semiconductor memory device as recited in claim 5, wherein each of said plurality of power pads receives a power supply voltage of a first voltage level, and said peripheral power pad receives a power supply voltage of a second voltage level different from said first voltage level.

12. The semiconductor memory device as recited in claim 2, wherein said plurality of power pads each connect an interconnection line supplying a power source voltage separate from others.

13. The semiconductor memory device according to claim 12, further comprising:

a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.

14. The semiconductor memory device as recited in claim 3, wherein said plurality of data input/output buffer means are further grouped into subgroups of a predetermined number of data input/output buffer means in each of said groups, and each of said power pads connects an interconnection line supplying the power source voltage only to an associated subgroup of data input/output buffer means.

15. The semiconductor memory device according to claim 14, further comprising;

a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.

16. A semiconductor memory device formed on a chip, comprising:

a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip;

a first pad arranged in a center portion in said center region along said first direction, for supplying a power source voltage to a control circuit for controlling an accessing operation to said plurality of memory blocks;

a plurality of second pads arranged in regions opposing to each other with respect to the center portion of said center region, each of said plurality of second pads supplying a power source voltage; and

a plurality of data input/output buffers provided corresponding to said plurality of memory blocks, in a region excluding the center portion of said center region, for carrying out input/output of data to a corresponding memory block, said plurality of data input/output buffers each operating with the power source voltage supplied from one of said plurality of second pads provided in a region proximate thereto of said center region.

17. The semiconductor memory device as recited in claim 16, wherein said plurality of second pads each connecting only a power source interconnection line supplying the power supply voltage to a data input/output buffer associated therewith.

18. A semiconductor memory device formed on a chip, comprising:

a plurality of memory blocks arranged in a first direction on both sides of a center region along said first direction on said chip, and divided into first and second groups along said first direction;

first and second pads respectively formed in peripheral portions opposing to each other in said center region along said first direction, each of said first and second pads receiving a power source voltage;

a third pad arranged in a center portion in said center region along said first direction and receiving the power source voltage;

a plurality of data input/output pad portions arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks, each said data input/output pad portions transmitting and receiving data to and from the corresponding memory block, wherein said plurality of data input/output pad portions are divided into first and second groups according to first and second groups of said plurality of memory blocks, a data input/output pad portion provided corresponding to memory blocks in said first group operating in reception of power source voltage from said first pad, and a data input/output pad portion provided corresponding to memory blocks in said second group operating in reception of the power source voltage from said second pad; and

peripheral circuitry operating in reception of the power source voltage from said third pad, determining an accessing operation to said plurality of memory blocks in response to an externally applied signal, and controlling the accessing operation according to the determination.

19. The semiconductor memory device as recited in claim 18, wherein

said first pad includes a pair of power pads arranged so as to sandwich data input/output pad portions in said first group therebetween along said first direction, and

said second pad includes a pair of power pads arranged so as to sandwich data input/output pad portions in said second group therebetween along said first direction.

20. The semiconductor memory device as recited in claim 19, wherein said pair of power pads in each of said first and second pads includes a power supply pad supplying one power supply voltage of said power source voltage and a ground pad supplying another power supply voltage of said power source voltage.

21. The semiconductor memory device as recited in claim 19, wherein each said power pad includes a power supply pad supplying one power supply voltage of said power source voltage and a ground pad supplying another power supply voltage of said power source voltage.

22. The semiconductor memory device as recited in claim 18, wherein

said first pad includes a power pad sandwiched between data input/output pad portions in said first group, and

said second pad includes a power pad sandwiched between data input/output pad portions in said second group.

23. A semiconductor memory device, comprising:

first and second memory blocks each having a plurality of memory cells;

first and second input/output means arranged corresponding to said first and second memory blocks along one side of said first and second memory blocks and spaced from each other along said one side for transmitting and receiving data between a corresponding memory block and an outside of the semiconductor memory device; and

peripheral circuitry arranged in a region between said first and second input/output means for controlling an accessing operation to said first and second memory blocks.

24. The semiconductor memory device as recited in claim 23, wherein said first and second input/output means are arranged in the vicinity of a center portion on said one side of corresponding memory blocks.

25. The semiconductor memory device as recited in claim 23, further comprising:

a first pad formed in a region opposing to a region forming said peripheral circuitry with respect to said first input/output means for receiving an externally applied power source voltage and supplying the received power source voltage to said first input/output means; and

a second pad formed in a region opposing to the region forming said peripheral circuitry with respect to said second input/output means for receiving another externally applied power source voltage and supplying the received power source voltage to said second input/output means.

26. The semiconductor memory device as recited in claim 23, wherein said peripheral circuitry includes a control circuit determining accessing operation, and input means for receiving an externally applied signal and transmitting the received signal to said control circuit.

27. The semiconductor memory device as recited in claim 23, further comprising a power pad formed in a region between said first and second input/output means for receiving an externally applied power source voltage and transmitting the received power source voltage to said peripheral circuitry as an operation power source voltage.

28. The semiconductor memory device as recited in claim 23, further comprising:

third and fourth memory blocks arranged on said one side of said first and second memory blocks so as to oppose to said first and second memory blocks, respectively, said third and fourth memory blocks each having a plurality of memory cells;

third input/output means arranged corresponding to said third memory block and adjacent to said first input/output means for carrying out input/output of data to and from said third memory block with power source voltage supplied from said first pad; and

fourth input/output means arranged corresponding to said fourth memory block and adjacent to said second input/output means for carrying out input/output of data to and from said fourth memory block with power source voltage supplied from said second pad,

said peripheral circuitry controlling an accessing operation to said first to fourth memory blocks.

29. The semiconductor memory device as recited in claim 25, wherein

only a power source interconnection line for supplying the power source voltage to said first input/output means is connected to said first pad, and

only a power source interconnection line for supplying the power source voltage to said second input/output means is connected to said second pad.

30. The semiconductor memory device as recited in claim 25, wherein

said first pad includes a pair of power pads arranged so as to sandwich said first input/output means therebetween in a direction along said one side, and

said second pad includes a pair of power pads arranged so as to sandwich said second input/output means therebetween in a direction along said one side.

31. The semiconductor memory device as recited in claim 28, wherein

only a power source interconnection line supplying a power source voltage to both said first and third input/output means is connected to said first pad, and

only a power source interconnection line supplying a power source voltage to both said second and fourth input/output means is connected to said second pad.

32. The semiconductor memory device as recited in claim 28, wherein

said first pad includes a pair of power pads arranged so as to sandwich said first and third input/output means therebetween in a direction along said one side, and

said second pad includes a pair of power pads arranged so as to sandwich said second and fourth input/output means therebetween in a direction along said one side.

33. The semiconductor memory device as recited in claim 31, wherein

said first pad includes a pair of power pads arranged so as to sandwich said first and third input/output means therebetween in a direction along said one side, and

said second pad includes a pair of power pads arranged so as to sandwich said second and fourth input/output means therebetween in a direction along said one side.

34. A semiconductor memory device, comprising:

a first memory block including a plurality of memory cells;

a first group of DQ pads receiving and supplying external data for said first memory block, and arranged in alignment with each other;

a first group of power pads receiving an external power source voltage for internal transmission, and arranged in alignment with said first group of DQ pads,

a second memory block including a plurality of memory cells;

a second group of DQ pads receiving and supplying external data for said second memory block, and arranged in alignment with each other; and

a second group of power pads arranged in alignment with said second group of DQ pads, and receiving and supplying an external power source voltage for internal transmission.

35. The semiconductor memory device as recited in claim 34, wherein said external source voltage comprises a power supply voltage and a ground voltage, and wherein

said first group of power pads includes a power supply pad supplying the power supply voltage and a ground pad which are arranged sandwiching at least one DQ pad of said first group of DQ pads, and

said second group of power pads includes a power supply pad supplying the power supply voltage, and a ground pad supplying the ground potential which are arranged sandwiching at least one DQ pad in said second group of DQ pads.

36. The semiconductor memory device as recited in claim 34, wherein said external source voltage comprises a power supply voltage and a ground voltage, and wherein

said first group of power pads consists of power supply pads supplying the power supply voltage, and

said second group of power pads consists of ground pads supplying the ground voltage, and

said first group of power pads and said second group of power pads are arranged on two lines in a region between said first and second memory blocks.

37. The semiconductor memory device as recited in claim 35, wherein said first group of power pads and said first group of DQ pads are arranged on an outer side of said first memory block opposing to an inner region between said first and second memory blocks, and said second group of DQ pads and said second group of power pads are arranged on an outer side of said second memory block opposing to said inner region.

38. The semiconductor memory device as recited in claim 35, wherein said first and second groups of DQ pads and said first and second groups of power pads are arranged in a region between said first and second memory blocks.

39. The semiconductor memory device as recited in claim 34, wherein said external source voltage includes a power supply voltage and a ground voltage, and wherein

said first group of power pads includes power supply pads each supplying the power supply voltage and ground pads each supplying the ground voltage, which are arranged alternately on a line, and

said second group of power pads includes power supply pads each supplying the power supply voltage and ground pads each supplying the ground voltage, which are alternately arranged on another line.

40. A semiconductor memory device formed on a chip, comprising:

a plurality of memory blocks each including a plurality of memory cells;

a plurality of DQ buffers provided corresponding to said plurality of memory blocks for transmitting and receiving data to and from corresponding memory blocks;

a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof and provided extending over said chip and at least one of said plurality of memory blocks;

a plurality of power pads provided corresponding to each respective memory block and coupled to said power bus for supplying the voltage received from the power bus to said plurality of DQ buffers provided corresponding to corresponding memory blocks.

41. The semiconductor memory device as recited in claim 40, wherein said plurality of power pads each connect an interconnection line supplying a power source voltage separate from others.

42. The semiconductor memory device as recited in claim 40, wherein said plurality of DQ buffers are grouped into groups, one group for each memory block, and each group include a second plurality of DQ buffers, and said second plurality of DQ buffers are grouped into subgroups of a predetermined number of DQ buffers in each of said groups, and each of said power pads connects an interconnection line supplying the power source voltage only to an associated subgroup of DQ buffers.

43. A semiconductor memory device, comprising:

a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns;

a plurality of data buses provided corresponding to each of said plurality of memory blocks, each of said plurality of data buses arranged extending along only a corresponding memory block; and

a plurality of data input/output pad portions for communicating data with the memory blocks through the data buses, a predetermined number of the data input/output pad portions being provided for each of the memory blocks, and each of the data input/output pad portions communicating data with only a corresponding memory block.

44. The semiconductor memory device according to claim 43, wherein said plurality of memory blocks are arranged on both sides of a center region extending in a first direction, and said plurality of data input/output pad portions are arranged alignedly on said center region.

45. The semiconductor memory device according to claim 43, wherein said plurality of memory blocks are arranged on both sides of a center line, and each of said plurality of data input/output pad portions are arranged on an outer side opposing to the center line of a corresponding memory block.

46. The semiconductor memory device according to claim 43, wherein each of said plurality of memory blocks has a predetermined number of memory cells selected at a time, and wherein said semiconductor memory device further comprises a compressor means provided for each of said plurality of memory blocks and coupled to receive data of the predetermined number of memory cells of a corresponding memory block for compressing the data of the predetermined number of memory cells when enabled in response to a test mode instruction signal.

47. The semiconductor memory device according to claim 46, wherein said plurality of memory blocks are provided on both sides of a center region extending in a first direction, and wherein said semiconductor memory device further comprises a further compressor means provided commonly for each set of memory blocks facing to each other with respect to said center region and further compressing data compressed by and received from the compressor means provided for a corresponding set of memory blocks when enabled in response to said test mode instruction signal.

48. The semiconductor memory device according to claim 46, wherein said compressor means supplies the compressed data to a data input/output pad portion provided for a corresponding memory block.

49. The semiconductor memory device according to claim 46, wherein said compressor means comprises a coincidence detector for detecting whether data received from the predetermined number of memory cells are identical in logic with each other.

50. The semiconductor memory device according to claim 47, wherein said further compressor means supplies the compressed data to an input/output pad portion provided for a corresponding set of memory blocks.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor memory devices, and in particular, to an arrangement of power supply pads and data input/output pads in a semiconductor memory device. More particularly, the present invention relates to a layout of power supply pads, and data input/output buffers and peripheral circuits, and a multibit test circuit in a general-purpose DRAM (Dynamic Random Access Memory).

2. Description of the Background Art

FIG. 33 schematically shows a chip layout of a conventional semiconductor memory device. In FIG. 33, the semiconductor memory device is formed on a semiconductor chip 1100, and includes four memory blocks MB1, MB2, MB3, and MB4. Each of memory blocks MB1-MB4 includes a plurality of memory cells. During the normal operation (during an external accessing), a one-bit memory cell is selected in each of memory blocks MB1-MB4, and data is written thereto or read therefrom (in the case of .times.4 bit configuration).

In the center region (a region between memory blocks MB1 and MB3 and memory blocks MB2 and MB4) of semiconductor chip 1100, arranged are pads for receiving external power supply voltage and ground voltage and for input/output of signals. Such a structure in which pads are arranged in the center region of a chip is known as a lead on chip (LOC) arrangement, in which the tips of lead frame are arranged on the chip, and the lead frame is connected at the respective tips to the pads arranged in the center region of the chip by wire bonding. Alignment of the pads in the chip center region allows an area occupied by the pads to be reduced as compared to a structure in which pads are arranged at a peripheral portion along both sides of semiconductor chip 1100, thereby improving the efficiency of use of the semiconductor chip.

In this pad arrangement, power supply pads VC1 and VC2 are usually arranged at opposite ends in the center region of semiconductor chip 1100 in order to maintain compatibility of pins with a semiconductor memory device of the previous generation for example. Data input/output pads DQ1-DQ4 are collectively arranged adjacent to one power supply pad VC1. The other power supply pad VC2 supplies power supply voltage to circuits other than the data input/output circuits. In the figure, power supply pads VC1 and VC2 are shown supplying power supply voltage Vcc. Similarly, ground pads for supplying ground voltage Vss are arranged adjacent to power supply pads VC1 and VC2, respectively. However, for simplicity of illustration, the ground pads are not shown.

Data input/output pads DQ1-DQ4 carry out transmission and reception of data to and from memory blocks MB1-MB4 through internal data buses 1102a-l102d, respectively. Although not clearly shown in FIG. 33, data input/output buffers are provided adjacent to respective data input/output pads DQ1-DQ4. These data input/output buffers are made operative in response to supply of operation power supply voltage from power supply pad VC1 and ground voltage. By providing an operation power source for the data input/output buffers separately from that for the other circuits, power supply voltage and ground voltage used upon input/output of data are stabilized, and data input/output operation (data output operation in particular) is stabilized (data is input/output stably without the influence of power supply noise), and is increased in speed (charge/discharge operation is carried out at a high speed due to alleviation of the load of a power supply circuit).

The data input/output buffers are arranged adjacent to data input/output pads DQ1-DQ4. These data input/output buffers operate with power supply voltage Vcc supplied from the power supply pad VCI in common. Since a plurality of (four in FIG. 33) data input/output buffers are coupled to one power supply pad, the load of the power supply pad (power supply line) increases. The current supplying capability of power supply pad VC1 is determined according to the external specification. Therefore, when the number of data input/output buffers (data output buffers in particular) connected to the power supply pad VC1 increases, each data input/output buffer cannot be supplied with current of a sufficient magnitude from power supply pad VC1 stably. As a result, power supply voltage and ground voltage vary, the data input/output buffers cannot charge/discharge respective output nodes at a high speed, and these buffers cannot operate at a high speed. During the data output operation in particular, when variation of power supply voltage causes the operation speed of the output buffers to decrease, a timing at which valid output data appear at external pin terminals through the pads is delayed, and data cannot be read out at a high speed.

Power supply pad VC2 provided at a periphery of the center region of semiconductor chip 1100 is used for supplying power supply voltage to peripheral circuits. Although not clearly shown in FIG. 33, the peripheral circuits are distributedly arranged on semiconductor chip 1100. Therefore, the length of a power supply line from power supply pad VC2 to each peripheral circuit becomes longer, causing reduction of power supply voltage by interconnection line resistance, instability of power supply voltage or the like. As a result, the peripheral circuits cannot operate stably.

In order to shorten the power supply lines from power supply pad VC1 to the data input/output buffers, and to decrease the load of the power supply lines as much as possible, the data input/output buffers and data input/output pads DQ1-DQ4 are collectively arranged in the vicinity of power supply pad VC1. Therefore, internal data line 1102a between memory block MB1 and data input/output pad DQ1 and internal data line 1102b between memory block MB2 and data input/output pad DQ2 are larger in length than internal data line 1102c between memory block MB3 and data input/output pad DQ3 and internal data line 1102d between memory block MB4 and data input/output pad DQ4. In this case, the interconnection line resistances and the parasitic capacitances of internal data lines 1102a and 1102b become larger than those of internal data lines 1102c and 1102d, and the signal propagation delay in internal data lines 1102a and 1102b becomes larger than that in internal data lines 1102c and 1102d, hampering high speed accessing. In particular, at the time of data reading, a timing at which data read out from memory blocks MB1 and MB2 appear and are determined at pads DQ1 and DQ2 is delayed from a timing at which memory cell data read out from memory blocks MB3 and MB4 appear and are determined at pads DQ3 and DQ4. It is necessary to decide an output data determination timing by the delayed timing, resulting in longer access time at the time of data reading.

Similarly, at the time of data writing, internal write data is generated from write data which appear on pads DQ1-DQ4 in response to a write pulse (generated in response to a write enable signal), and transmitted to respective memory blocks MB1-MB4 through internal data lines 1102a-l102d. In this case, a timing at which write data is written in memory blocks MB1 and MB2 is delayed from a timing at which write data is written in memory blocks MB3 and MB4, resulting in a longer data writing time.

As shown in FIG. 34, in the case of a conventional arrangement of data input/output pads, peripheral pads PD1-PDn receiving address signals and clock signals (external control signals such as a row address strobe signal RAS and a write enable signal WE), and a master control circuit 1110 receiving internal signals from peripheral pads PD1-PDn and generating signals controlling accessing operations to memory blocks MB1-MB4 are provided in a region other than a region for forming data input/output pads DQ1-DQ4 in the center region of semiconductor chip 1100. Buffers provided corresponding to pads PD1-PDn operate in reception of power supply voltage from power supply pad VC2. Usually, peripheral pads PD1-PDn are arranged alignedly. An internal signal from peripheral pad PD1 is applied to master control circuit 1110 through a signal line 1112, and an internal signal from peripheral pad PDn is applied to master control circuit 1110 through a signal line 1113.

Master control circuit 1110 provides necessary control signals for memory blocks MB1-MB4, respectively, and generates signals defining data input/output timings of the data input/output buffers provided corresponding to data input/output pads DQ1-DQ4. Generally, the DRAM strobes an address signal applied to an address input pad in response to the falling of row address strobe signal RAS, and generates an internal row address signal. Usually, for the address signal, a set-up time and a hold time are determined with respect to the falling edge of the signal RAS. When signal lines 1112 and 1113 are different in length from each other as shown in FIG. 34, these signal lines 1112 and 1113 have different signal propagation delays from each other, and therefore, it is necessary to set the set-up time and the hold time for the worst case. This prevents an implementation of earlier internal operation start timing and high speed operation. Further, the difference in distances from master control circuit 1110 to memory blocks MB1-MB4 prevents operation timings of memory blocks MB1-MB4 from being common, and accessing time becomes longer for the worst case.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a semiconductor memory device operating stably at a high speed.

Another object of the present invention is to provide a semiconductor memory device including a pad layout for implementing high speed and stable operation.

A semiconductor memory device according to one aspect of the present invention includes a plurality of memory blocks arranged in alignment with a first direction on both sides of the center region along the first direction, a plurality of data input/output buffers arranged corresponding to the plurality of memory blocks and adjacent to the corresponding memory block in the center region, each data input/output buffer transmitting and receiving data to and from the corresponding memory block, and a plurality of buffers arranged in the vicinity of the center portion in the center region along the first direction for receiving an external signal for accessing the plurality of memory blocks. The plurality of data input/output buffers are arranged in a region other than the vicinity of the center portion.

Preferably, further provided are a plurality of power supply pads arranged adjacent to a data input/output buffer group in each of one side region and the other side region of the center region for supplying power supply voltage only to a corresponding data input/output buffer group.

Preferably, a respective power supply pad connects only a power supply interconnection line for supplying power supply voltage to a corresponding data input/output buffer group.

Preferably, the plurality of data input/output buffers are aligned in each of one side region and the other side region of the center region, and the plurality of power supply pads are arranged in the center region so as to sandwich a corresponding data input/output buffer therebetween in the first direction in each of one side region and the other side region.

Preferably, further provided are peripheral circuitry arranged in the center portion between one side region and the other side region of the center region for receiving an external signal controlling accessing to the plurality of memory blocks and for controlling accessing to the plurality of memory blocks in response to the received external signal, and a peripheral power supply pad provided exclusively for the peripheral circuitry in the center portion of the center region for receiving externally applied power supply voltage and supplying the received power supply voltage to the peripheral circuitry.

Preferably, a compressor for compressing data of multibits of memory cells is provided for each memory block.

In one aspect of the present invention, the data input/output buffers are arranged in the vicinity of each corresponding memory block, and the peripheral circuitry is arranged in the vicinity of the center portion, so that the length of internal data buses to all the data input/output buffers can be made identical, and that data input/output can be carried out at a high speed. Further, arranging an external signal input buffer in the center portion allows the master control circuit serving as the peripheral circuitry to be arranged in the chip center portion so that an external signal can be transmitted to the peripheral circuitry with a shortest signal line, resulting in high speed access.

Preferably, the plurality of data input/output buffers are arranged corresponding to the respective of memory blocks. The plurality of data input/output buffers are arranged in groups on one side region and the other side region opposite to each other with respect to the center portion of the center region. Preferably, the pads are arranged corresponding to each data input/output buffer group. Each pad supplies power supply voltage only to a corresponding data input/output buffer group. Therefore, it is not necessary to apply power supply voltage from one pad to all the data input/output buffers, resulting in stable supply of power supply voltage to the data input/output buffers. As a result, variation of power supply voltage during operation of the data input/output buffers can be suppressed. It is not necessary to set an access time taking the power supply voltage into consideration in accessing of data input/output, enabling high speed access. Further, since the data input/output buffers are arranged corresponding to respective memory blocks, the distances between respective memory blocks and corresponding data input/output buffers can be made approximately identical with each other, and that a different data input/output buffer provides a different timing at which a valid data signal is determined can be prevented, and a margin for determination timing of a valid data signal can be made small. Accordingly, high speed access is enabled.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically showing a chip layout and an arrangement of external pin terminals of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a diagram schematically showing a structure of a power supply pad and data input/output pad portions.

FIG. 3 is a diagram schematically showing a structure of a memory block of the semiconductor memory device shown in FIG. 1.

FIG. 4 is a diagram schematically showing a layout of a peripheral circuit portion in the semiconductor memory device according to the present invention.

FIGS. 5A and 5B are signal waveform diagrams used for showing set-up times and hold times defined for the semiconductor memory device, and for explaining the meritorious effect of the semiconductor memory device shown in FIG. 4.

FIG. 6 is a diagram showing one example of a manner of distribution of power supply voltage from the power supply pads in the semiconductor memory device according to the present invention.

FIG. 7 is a diagram showing another manner of distribution of power supply voltage from the power supply pads in the semiconductor memory device according to the present invention.

FIG. 8 is a diagram showing an arrangement of external pin terminals of the semiconductor memory device according to the present invention.

FIG. 9 is a diagram showing another arrangement of external pin terminals of the semiconductor memory device according to the present invention.

FIG. 10 is a diagram schematically showing an internal layout of a semiconductor memory device having the arrangement of external pin terminals shown in FIG. 9.

FIG. 11 is a diagram showing a further external pin arrangement of the semiconductor memory device according to the present invention.

FIG. 12 is a diagram showing an inner pad layout of the semiconductor memory device in the package of FIG. 11.

FIG. 13 is a diagram showing another inner pad layout of the semiconductor memory device in the package of FIG. 11.

FIG. 14 iS a diagram showing a further another external pin arrangement of the semiconductor memory device according to the present invention.

FIG. 15 is a diagram showing an inner pad layout of the semiconductor memory device in the package of FIG. 14.

FIG. 16 is a diagram showing another inner pad layout of the semiconductor memory device in the package of FIG. 14 according to the present invention.

FIG. 17 is a diagram showing a further inner pad layout of the semiconductor memory device in the package of FIG. 14.

FIG. 18 is a diagram showing a further another inner pad layout of the semiconductor memory device in the package of FIG. 14.

FIG. 19 is a diagram showing a still external pin arrangement of a semiconductor memory device according to the present invention.

FIG. 20 is a diagram showing an inner pad layout of the semiconductor memory device in the package of FIG. 19.

FIG. 21 is a diagram showing a still another external pin terminals of a semiconductor memory device according to the present invention.

FIG. 22 is a diagram showing an inner pad layout of the semiconductor memory device in the package of FIG. 21.

FIG. 23 is a diagram showing a still further another external pin arrangement of a semiconductor memory device according to the present invention.

FIG. 24 is a diagram showing an inner pad layout of the semiconductor memor