High speed network switch - Patent Review 5604735

What is claimed is:

1. A high speed network switch comprising:

a plurality of transceivers for interfacing directly with a like plurality of nodes, each of said transceivers having a receive and transmit through port for passing data to and from said nodes, said data comprising an encoded connect sequence, a first wait sequence, and user data;

isolation means for initializing each transceiver for looping back said data;

switching means for directly connecting any pair of said transceivers; and

a controller for establishing and prioritizing matrix connections and disconnections, said controller decoding said connect sequence and scheduling said switching means connections, such that a requesting node sequentially transmits said encoded connect sequence followed by said user data to said network switch assuming node-to-node communication has been established with a destination node, said isolation means looping said user data back to said requesting node when said destination node is unavailable.

2. The high speed network switch of claim 1 wherein said encoded connect sequence includes routing information.

3. The network switch of claim 1 wherein said encoded connect sequence is a series of eleven binary words including destination node data, priority data, route/data status, queued mode data and parity data.

4. The network switch of claim 1 wherein said data passed by said transceivers includes a disconnect sequence that is a single binary data word.

5. The network switch of claim 3, wherein said destination node data, priority data, route/data status, queued mode data and parity data form an 11 bit binary sequence word.

6. The network switch of claim 5, wherein said 11 bit binary sequence word is encoded to create said encoded sequence word by taking said 11 bit binary sequence word and generating an 11 word sequence wherein a transition from a binary 1 to binary zero, and a transition from a binary zero to a binary 1 result in the transmission of a first data word, while a steady state between consecutive bits results in the transmission of a second data word thereby generating a sequence of 11 data words based on the transitions between successive data bits.

7. The network switch as in claim 6, wherein said first data word is 40 bits in length and is comprised of 24 binary 1's, followed by 8 binary 0's, followed by a 01010101 binary string.

8. The network switch as in claim 4, wherein said disconnect sequence is 40 bits in length and is comprised of 24 binary 0's, followed by 8 binary 1's, followed by a 10101010 binary string.

9. The network switch of claim 1, wherein said transceivers further include a serial asynchronous receiver for decoding said encoded connect sequence.

10. The network switch of claim 9, wherein said controller further includes

a like plurality of node route control state machines coupled to each of said transceivers for receiving decode routing requests from said serial asynchronous receiver in each of said transceivers;

a bus architecture for interconnecting each of said node route control state machines to a data bus;

a bus arbiter for arbitrating access to said data bus upon receipt of a connection request from any of said node route control state machines, said bus arbiter granting access to said data bus to a first requesting node route control state machine whereupon said requesting node route control state machine generates a first configuration command including requesting and destination data;

means for snooping on said data bus in each of said node route control state machines for detecting said first configuration command and determining if said first configuration command destination data is directed to its respective node;

means for generating a second configuration command upon the availability of said destination;

means for generating a switch matrix configuration responsive to said first and second configuration commands upon verification of said second configuration command.

11. The network switch of claim 10 wherein each of said node route control state machines further includes;

a selector for designating each of said node route control state machines to be associated with a preselected group of said node route control state machines forming a hunt group therein; and

a hunt group state machine, said hunt group state machine responsive to said first configuration command for generating a hunt group request signal including a hunt group identification tag upon the unavailability of a destination node designated by said destination data, said hunt group state machine including means for snooping on said data bus for detecting said hunt group identification tag generated by said unavailable destination node, a request circuit for generating a request signal from an available member of an indicated hunt group to said bus arbiter for servicing a requesting node indicated by said requesting data, and means for generating said second configuration command upon a grant of said data bus to one of said available members of said hunt group by said bus arbiter, said second configuration command including said requesting data and an identification tag for said granted available member of said hunt group.

12. A method for establishing node-to-node communication in a network, said network having a plurality of nodes directly connected to a network switch having a like plurality of transceivers, a switch matrix, a controller having a like plurality of node state machines, and a blind interrogation data format including an encoded connect sequence, a first wait sequence, user data and a disconnect sequence, the method comprising the steps of:

(a) initializing said switch matrix to loop-back transmissions for each transceiver;

(b) initiating a first communication link between a requesting node and a destination node, said requesting node transmitting an encoded connect sequence, a first wait sequence and user data to a first transceiver of said network switch;

(c) decoding said encoded connect sequence received by said first transceiver to derive destination and route data;

(d) coupling said derived destination and route data to an associated node state machine in said controller, said associated node state machine placing said destination and route data on a data bus;

(e) snooping on said data bus by each of said plurality of node state machines to determine if said destination node corresponds to their associated node,

(f) placing an authentication word on said data bus by said state machine associated with said destination node upon the availability of said destination node;

(g) configuring said switch matrix to connect said requesting node to said destination node when said authentication word has been placed on said data bus; and

(h) looping said user data back to said requesting node when said destination node is unavailable.

13. A method for establishing node-to-node communication in a network, said network having a plurality of nodes directly connected to a network switch having a like plurality of transceivers, a switch matrix, a controller having a like plurality of node state machines, and a blind interrogation data format including an encoded connect sequence, a first wait sequence, user data and a disconnect sequence, the method comprising the steps of:

(a) initializing said switch matrix to loop-back transmissions for each transceiver;

(b) selecting ones of said nodes for association in a hunt group;

(c) initiating a first communication link between a requesting node and a destination node, said requesting node transmitting an encoded connect sequence, a first wait sequence and user data to a first transceiver of said network switch;

(d) decoding said encoded connect sequence received by said first transceiver to derive destination and route requestor data;

(e) coupling said derived destination and route requestor data to an associated node state machine in said controller, said associated node state machine placing said destination and route requestor data on a data bus;

(e) snooping on said data bus by each of said plurality of node state machines to determine if said destination node corresponds to their associated node,

(f) placing an authentication word on said data bus by said state machine associated with said destination node upon the availability of said destination node;

(g) placing a hunt group request signal including a hunt group identification tag on said data bus if said destination node is unavailable and said destination node is in said hunt group;

(h) issuing a service request signal responsive to said hunt group request signal by all available members of said hunt group;

(I) arbitrating between said available hunt group members and selecting one of said available hunt group members to service said first communication link;

(j) placing an authentication word on said data bus by said selected one of said hunt group members indicating route requestor data and destination data, said destination data including an identification tag for said selected one of said hunt group members;

(k) configuring said switch matrix to make said first communication link based on said destination and route requestor data when said authentication word has been placed on said data bus; and

(l) looping said user data back to said requesting node when said destination node and all hunt group members are unavailable.

14. A high speed network switch comprising:

a plurality of transceivers for interfacing directly with a like plurality of nodes, each of said transceivers having a receive and transmit through port for passing data to and from said nodes and said network, said data comprising an encoded connect sequence, a first wait sequence, user data and a disconnect sequence, each of said transceivers having a serial asynchronous receiver for decoding said encoded connect sequence and outputting a routing information word;

a switch matrix for directly routing data between said transceivers, said switch matrix comprising a switch matrix controller, a plurality of ports, and means for switching data between said ports, each of said transceivers coupled to one of said plurality of ports of said switch matrix, said switch matrix for cross coupling receive and transmit through ports for any pair of transceivers of said network switch;

a controller for establishing and prioritizing matrix connections and disconnections, said controller comprising

(a) a like plurality of node route state machines each coupled to one of said transceivers and receiving said routing information word;

(b) a data bus connecting each of said node route state machines;

(c) a bus arbiter for prioritizing access requests from each of said node route state machines for access to said data bus, said bus arbiter granting control of said data bus to a single authorized node route state machine at a time;

(d) means for placing a routing command including a destination node ID on said data bus by said authorized node route state machine;

(e) snooping means in each of said node route state machines for determining if said routing command on said data bus is directed to their associated node, and if their associated node is available for connection;

(f) authentication means in each of said node route state machines to place an authentication word on said data bus if said routing command is directed to said associated node and said associated node is available;

(g) a state machine engine for processing said routing commands and authentication words to update a routing table and issue switch configuration commands; and

(I) a sequence generator responsive to said routing commands for formatting instructions to be passed to said switch matrix controller for configuring said switch matrix; and

signals having a blind interrogation data format transmitted by said nodes to said transceivers for establishing node-to-node communication whereby a requesting node sequentially transmits said encoded connect sequence and user data assuming said node-to-node communication has been established, said switch matrix looping said user data back to said requesting node when said destination node is unavailable.

15. The network switch of claim 14 wherein said switch matrix couples each of said transceivers receive through port to said same transceiver transmit through port while said nodes are inactive.

16. A high speed network switch comprising:

a plurality of transceivers for interfacing directly with a like plurality of nodes, each of said transceivers having a receive and transmit through port for passing data to and from said nodes and said network, said data comprising an encoded connect sequence, a first wait sequence, user data and a disconnect sequence;

first switching means for looping back said data for each of said transceivers to said nodes;

a second switching means for connecting any pair of said transceivers;

a controller for establishing and prioritizing matrix connections and disconnections, said controller decoding said encoded connect sequence and scheduling said second switching means connections; and

signals having a blind interrogation data format transmitted by said nodes to said transceivers for establishing node-to-node communication, such that a requesting node sequentially transmits said encoded connect sequence and user data to said network switch assuming said node-to-node communication has been established with a destination node, said first switching means looping said user data back to said requesting node when said destination node is unavailable.

17. A high speed network switch comprising:

a plurality of transceivers for interfacing directly with a like plurality of nodes, each of said transceivers having a receive and transmit through port for passing data to and from said nodes and said network, said data comprising an encoded connect sequence, a first wait sequence, user data and a disconnect sequence;

a switch matrix for directly routing data between said transceivers, said switch matrix comprising a switch matrix controller, a plurality of ports, and means for switching data between said ports, each of said transceivers coupled to one of said plurality of ports of said switch matrix, said switch matrix for cross coupling receive and transmit through ports for any pair of transceivers of said network switch;

a controller for establishing and prioritizing matrix connections and disconnections, said controller initializing each of said switch matrix ports for loop-back; and

signals having a blind interrogation data format transmitted by said nodes to said transceivers for establishing node-to-node communication, whereby a requesting node sequentially transmits said encoded connect sequence and user data assuming said node-to-node communication has been established, said switch matrix looping said user data back to said requesting node when said destination node is unavailable.

Description Submit all comments and votes

The present invention relates generally to communication networks. More particularly, to a switching apparatus for configuring a network for node-to-node communications.

BACKGROUND OF THE INVENTION

The present invention provides an improvement in communication networking by providing a high-speed routing mechanism for transmitting data between nodes on a communications network.

Conventional local area networks provide switches or bridges for linking users on a network. Switching systems in a communications network environment process requests from users to link a requesting user node with a destination node by decoding packets containing routing information generated by the requesting node.

Message switching is a form of data switching which relies on a store-and-forward technology. Each switch within a given network stores a network message in its entirety (packets) and transfers them out of storage upon the availability of the destination node. Often interrupt strategies are employed to achieve near real-time operation over portions of the network that are nearly transparent to the end users. Storage costs and complex interrupt handlers make these systems undesirable for low cost networks which seek to operate at or near real time with minimal system latency.

Circuit switching is a form of data switching which dedicates system resources to a particular call or transaction. Physical resources in time, space or frequency spectrum are dedicated to the exclusive use of a single call for the duration of that call. Circuit switching apparatus contain no storage devices, and merely route information based on the availability of a given destination node. Accordingly, "blocking" may result, wherein a call or transaction may not be established, due to the dedicated nature of the circuit switching connections whenever a system resource is in use.

Circuit switching systems operate in real time providing node to node communications once a connection is made between a source and destination. The performance of a circuit switching system can be measured in terms of connect time and latency. Connect time refers to the amount of time it takes to make a requested connection between a source and destination node in a network. Latency is a related consideration which refers to the time period between the application of a stimulus (a request for connection in a network) and the first indication of a response from the network. Most network communications are inherently short duration in nature, on the order of magnitude of 5 milliseconds or less. Accordingly, networks employing circuit switching systems are required to rapidly connect and disconnect physical resources as fast as possible to avoid "blocking" of transactions, and achieve transparent real time communications on the network. Any improvements in speeding up the connect and disconnect cycles as well as improving the overall system latency is desirable in networks employing circuit switching.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a high bandwidth, and high speed switching system with minimal latency for network communications.

It is a further object of the present invention to provide a high speed switching system which directly switches available resources while also allowing for a user to queue a routing request to Initiate connection upon resource availability.

The apparatus of the present invention comprises a switching apparatus including a plurality of transceivers for interfacing directly with a like plurality of user nodes. Each of the transceivers has a receive and transmit through port for passing data to and from user nodes and a network. Transmitted information includes a connect symbol, a first wait sequence, user data and a disconnect symbol. The switching apparatus further includes circuitry for isolating each transceiver so as to loop back data when not in use and a switching matrix for directly connecting any pair of transceivers. Each of the transceivers includes circuitry for detecting connect and disconnect symbols and an interface for connection to a serial asynchronous receiver to derive node requests, routing data, priority and other information from the connect symbols detected at the transceiver. Derived switch configuration requests are processed by a node route control state machine, with each node route control state machine integrated in a bus architecture for configuring the matrix switch. A bus arbitration state machine controls the bus architecture servicing bus requests and providing bus grants for the transfer of routing information to switch control logic and command sequencer. In operation, a requesting node transmits a connect sequence consisting of 11 symbols (1 symbol=1 forty bit word), waits a predefined period while sending idles and then transmits user data to the network switch assuming node-to-node communication has been established with a destination node. In the event a connection fails to be made, the isolation circuitry loops user data back to the requesting node indicating the destination node is unavailable. The requesting node may set a priority for a connection request, queue a request for a destination node that is currently busy, or alternatively request data from the switch micro-controller core. In the preferred embodiment, the microcontroller core continuously monitors the status and operational levels for all attached nodes, thus forming a network diagnostic subsystem.

In a second embodiment, a multi-switch configuration may be implemented whereupon a requesting node will generate a plurality of connection request sequences, each sequence consisting of 11 symbols, so as to initiate node-to-node communication with a destination node connected to a different switch.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

FIG. 1 is a block diagram of a switching apparatus according to the preferred embodiment of the present invention.

FIG. 2 is a block diagram of a transceiver according to the preferred embodiment of the present invention.

FIG. 3 is a block diagram of a switch matrix according to the preferred embodiment of the present invention.

FIG. 4 is a block diagram of the control electronics for configuring the switch matrix.

FIG. 5 shows the state machine diagram for a bus arbiter according to the preferred embodiment of the present invention.

FIG. 6a shows the state machine diagram for a node route connect state machine according to the preferred embodiment of the present invention.

FIG. 6b shows the state machine diagram for a hunt group state machine according to the preferred embodiment of the present invention.

FIG. 7 shows the state machine diagram for a switch controller state machine according to the preferred embodiment of the present invention.

FIG. 8a shows a data structure generated by a source node for establishing connection to a destination node.

FIG. 8b shows a data structure generated by a source node for queuing a connection request for establishing a link to a destination node which was previously busy.

FIG. 9a shows a multi-switch configuration implemented by interconnecting a pair of switching devices according to the preferred embodiment of the present invention.

FIG. 9b shows a data structure generated by a source node for establishing connection to a destination node in a multi switch configuration.

FIG. 9c shows a data structure generated by a source node for queuing a connection request for establishing a link to a destination node which was previously busy.

FIG. 10 shows a multi-switch configuration after a first connection request has been serviced by an interfacing switch.

FIG. 11 shows a multi-switch configuration after a second connection request has been serviced thereby allowing for full duplex communication between nodes connected to different switches.

FIG. 12 shows a three switch configuration utilizing three switches according to the preferred embodiment of the present invention.

FIG. 13 is a block diagram of a switching apparatus according to a second preferred embodiment of the present invention that utilizes an optical crosspoint switch.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring first to FIG. 1, a switching apparatus 100 incorporating the teaching of the present invention is shown. A plurality of nodes 102 are connected to the switch 100 at a like plurality of transceivers 104. The transceivers 104 receive and transmit serial data between the switching apparatus 100 and the nodes 102. Each transceiver 104 is coupled to a switch matrix 106 via a high speed serial I/O link 108. The high speed serial I/O link includes separate transmit 110 and receive links 112 thereby allowing for full duplex operation in each node to node connection.

For the purposes of this document, both host computers and switches shall sometimes be called "nodes." The transceivers 104 of a switch can be connected to any network node, regardless of whether that node is a switch or an end user's host computer.

The switch matrix 106 includes a switch controller 114 for configuring the transmit 110 and receive links 112 of each transceiver to either loop back data or establish full duplex communication with any other node 102 connected to the switch matrix 106. Control electronics 116 coupled to the switch matrix 106 configures the switch matrix 106.

Referring now to FIG. 2, a transceiver 104 according to the preferred embodiment of the present invention is shown. The transceiver 104 has a first serial data input 200 and first serial data output 202 for transmitting data between a user node 102 and the transceiver 104. The transceiver 104 also includes a second serial data input 204 and second serial data output 206 for transmitting serial data between the transceiver 104 and the matrix switch 106.

A diagnostics port 207 is provided to monitor transceiver 104 performance by the control electronics 116, as well as for transmission of diagnostics data by the switch to the node associated with the transceiver 104. The diagnostics port 207 has five signal lines including a chip select line for enabling use of the diagnostics port 207 for a given transceiver; a ready line for signalling that the diagnostic port is ready to receive serial data; a first serial data line for transmitting transceiver diagnostics data to the switch 100; a second serial data line for transmitting diagnostics commands or data from the switch 100 to the transceiver; and a bit shift clock signal line for assisting in the serial transmissions between the diagnostic port and the switch.

In the preferred embodiment, the transceiver 104 is a plug-and-play style device which may be plugged into the switching apparatus as required to meet various node transmission requirements. The transceivers may be customized to conform to user node requirements such as optical transceivers for converting fiber optics transmissions, RF transceivers or a conventional twisted pair configuration. The switching apparatus may be configured with a plurality of interfaces designed to meet the individual needs of the individual nodes. In the preferred embodiment fiber optic receivers (Fiber Optic Transceiver, part number FTR-8510-1SW manufactured by Finisar) are used providing an optical interface between the nodes and the switching apparatus.

The transceiver 104 also includes a detection circuit 208 and corresponding connect 210 and disconnect output port 212 for detecting initiation and termination sequences passed from a source node to the switching apparatus 100. The detection circuit 208 monitors the serial transmission stream from its corresponding node 102, waiting for the detection of a connection or disconnection sequence. In the preferred embodiment of the present invention, the connection sequence is a series of eleven "words" each of 40 binary bits transmitted by the source node. The words are either one of two forms, a connect word (IntC word) or a neutral word (IntN word). The connection sequence generated by a source node indicates to the switch matrix route and data requests as well as other control information. In the preferred embodiment, the 11 word connect sequence is an encoded sequence representative of 2 start bits, followed by 8 data bits and one parity bit. The eight data bits are broken down as follows: five bits for route/data information (up to 32 destination nodes represented by combinations of the 5 bits), one bit for route or data mode (e.g. the first five bits are to be interpreted as route or data), one bit for low/high priority, and finally one bit for queued mode or another optional feature.

The encoding of the connection sequence takes place at the source node 102, where particular combinations of the connect word (IntC) and the neutral word (IntN) are arranged using an alternate mark inversion (AMI) like encoding technique. In the preferred embodiment, every connection sequence begins with a pair of connect words (IntC, IntC, . . . ), representative of a "10" sequence of start bits. An encoded sequence representative of the remaining 8 data bits and one parity bit is then generated by comparing the last bit sent (binary representation) with the next bit in line. If no state change is to occur (e.g. the combination of the last and next bit is 00 or 11) then a neutral word is generated for transmission down to the transceiver 104. If a state change is to occur (e.g. the combination of the last and next bit is 01 or 10) then a connect word is generated for transmission down to the switch matrix transceiver 104. This encoding continues until the last bit (the parity bit) is encoded thereby generating the last word of the 11 word connection sequence for transmission to the transceiver 104.

In the preferred embodiment of the present invention the connection word is a series of 24 binary 1's, followed by 8 binary 0's, followed by a 10101010 binary pattern, and the neutral word is a series of 40 binary bits alternating between 1 and 0, starting with a 1. The neutral word may be formed of other combinations of binary 1's and 0's which are distinguishable from the connect and disconnect sequences. The preferred embodiment employs a capacitive detector which detects the series of continuous 1's (or 0's) and starts a connection Cycle. As such the neutral word must be defined so as assure a complete discharge of the capacitive detector. The decoder 208 includes a connect sequence output port connected to a port dedicated state machine in the control electronics 116 via the connect output pin 210.

In the preferred embodiment the disconnection sequence is a single 40 bit disconnect word (IntD) comprising a series of 24 binary 0's, followed by 8 binary 1's, followed by a 01010101 binary pattern. A source node 102 which desires to reconfigure from its current switch configuration and return to a loopback condition will generate the disconnect word (IntD) for transmission to the transceiver 104. The decoder 208 in the transceiver 104, decodes the disconnect sequence, and issues a disconnect service request to the port dedicated state machine in the control electronics 116 associated with this port on disconnect output pin 212.

Those ordinarily skilled in the art will recognize that the particular sequence of binary 1's and 0's selected may be of other lengths or combinations in either the connect or disconnect sequence. The particular combinations of 1's or 0's were selected to both minimize the occurrence of conflicts associated with real data and the connect or disconnect sequences themselves and also to assure a complete discharge of the capacitive detector used in the preferred embodiment of the present invention. The detection circuit 208 may be implemented using RC circuits and comparators or by other circuitry known in the art.

Referring now to FIG. 3, the switch matrix 106 of the preferred embodiment of the present invention is shown. The switch matrix 106 includes a plurality of ports 300, each having an input 302 and output 304. Each transceiver 104 is coupled to the switch matrix 106 at one of the ports 300. More specifically, the second serial data output 206 from each transceiver 104 is coupled to an input 302 of a corresponding port 300. Similarly, the second serial data input 204 from each transceiver 104 is coupled to an output 304 of the same port 300. In this way, by configuring the switch matrix 106 to couple a particular port's input 302 to the same port's output 304, a loop-back configuration may be established for any individual node. In loop-back, any serial transmissions generated by a source node as an output will be looped-back by the switch matrix to the same source node as an input.

In the preferred embodiment, the switching apparatus 100 is configured to include 16 ports in the switch matrix 106. This configuration will support switching between 16 different nodes in an isolated switch network, or combinations of 16 different nodes and other switches in a multiple switch environment. Those ordinarily skilled in the art will recognize that any number of ports (n ports) may be provided in the switch matrix to service n devices.

The switch matrix 106 includes cross-coupling means 306 for coupling any pair of inputs 302 and outputs 304, thereby establishing full duplex communication between any source and any destination node in the network. The switch matrix 106 further includes a switch controller 114 for receiving matrix configuration commands via a command port 310. The switch controller 114 processes connect and disconnect requests generated by the control electronics 116. In the preferred embodiment of the present invention, switch matrix 106 is a sixteen port cross point switch part number TQ8017 manufactured by Triquint Semiconductor, Inc.

Referring now to FIG. 4, the control electronics 116 of the present invention is shown. A plurality of Node Route Control State Machines 400.sub.0-15 (NRCSM) are connected one to each transceiver 104 via the connect output pin 210.sub.0-15 and disconnect output pin 212.sub.0-15. Each NRCSM 400 includes a serial asynchronous receiver (SAR) 401 for processing the 11 word connect sequence cycle and a hunt group state machine 425. The function and connection of the hunt group state machine will be discussed in further detail below.

The connect output pin 210.sub.0-15 from each detector 208 of each associated transceiver 104 transmits the detected connect sequence cycle to the serial asynchronous receiver (SAR) 401 within each NRCSM 400 for processing. The SAR 401 uses a free running clock and an edge trigger (start bit) state machine to extract 8 bits of data from the 11 word connection sequence. The 11 word connection sequence is translated by the SAR 401 into two start bits, 8 data bits, and one parity bit. In the preferred embodiment, the SAR 401 has two forms of error detection, first the two start bits must be received before any route/data information is processed, and secondly, the SAR 401 will check the parity by use of the translated parity bit to assure data integrity.

The disconnect output pin 212.sub.0-15 transmits disconnect service requests (IntD) detected by the detector 208 of a given transceiver 104, indicating the source node desires to re-establish a loopback configuration.

Each NRCSM 400.sub.0-15 is connected to five shared busses in a bus architecture to a bus arbiter 402. The five busses connected to each NRCSM are: Bus.sub.-- Request 404 for use by a NRCSM for scheduling a connection request; Bus.sub.-- Clock 406 for timing data bus transfers; Bus.sub.-- State 408 for indicating which of the six states the arbiter currently is operating in; Bus.sub.-- Grant 410, an acknowledgment signal from the arbiter 402 that for the next two clock cycles the authorized NRCSM may utilize the data bus; and Bus.sub.-- Data 412, the data bus for transmitting route information between the nodes and the switch controller state machine.

The Bus.sub.-- Request bus 404 is shown in bus form, however, in the preferred embodiment, is actually 16 individual single bit signals originating one at each of the sixteen NRCSMs 400.sub.0-15. Each of these individual busses is terminated at the arbiter 402. Those ordinarily skilled in the art will recognize that the individual connection scheme allows for simultaneous requests to be issued to the arbiter 402. In an alternative embodiment, a multi-bit signal is received from each NRCSM which includes priority information.

The Bus.sub.-- Clock bus 406 is a single bit wide and contains the bus clock signal generated by the bus arbiter 402 for control and timing of the transmission of data on the bus architecture.

The Bus.sub.-- State bus 408 is five bits wide and contains the status information for the current state of the bus arbiter 402. The bus arbiter 402 has six states which are transmitted via this bus to each of the NRCSM 400.sub.0-15, to switch controller state machine 414 and the hub controller interface logic 420. The six states are: Bus Request state 00000, Bus Grant state 00001, Command (Node Request) state 00010, Node Response state 00100, Hunt Group Request state 01000, and the Hunt Group Grant state 10000. The status of the bus arbiter 402 will be discussed in greater detail below.

The Bus.sub.-- Grant bus 410 is 5 bits wide and carries the ID of the NRCSM which has been selected to be serviced based on a bus request signal sent to the arbiter 402 during the first cycle of the bus arbitration (corresponding to the Bus Request state 00000 in the arbiter 402) or during a hunt group arbitration (corresponding to the Hunt Group Request state 01000 in the arbiter 402). The Bus.sub.-- Grant bus 410 is active during the second cycle of the bus arbiter state machine cycle (Bus Grant state 00001 ) and during the hunt group grant cycle (corresponding to the Hunt Group Grant state 10000).

The Bus.sub.-- Data bus 412 is 16 bits wide and carries route and data information to be passed between the NRCSMs. The Bus.sub.-- Data bus 412 is active during the Command (Node Request) state 00010 and Node Response state 00100 cycles of the bus arbiter 402. During the Command (Node Request) state 00010, the Bus.sub.-- Data bus 412 carries the route information from the source NRCSM which has been granted the use of the data bus. During the Node Response state 00100, the Bus.sub.-- Data bus 412 carries reply information from a destination node requested by the selected NRCSM in the form of a 16 bit data word either granting or denying the route requested. A typical Bus.sub.-- Data signal contains a 5-bit source node ID, a 5-bit destination node ID, a 1-bit route/data designation (i.e., indicating whether the destination node ID field should be interpreted as route or data information), a 1-bit queued mode flag, a 1-bit priority flag, and 3 command/response bits.

A switch controller state machine 414 is coupled to the Bus.sub.-- Clock bus 406, the Bus.sub.-- State bus 408 and the Bus.sub.-- Data bus 412. The switch control logic circuit 414 snoops on the Bus.sub.-- State bus 408 waiting for the grant of the data bus to a source NRCSM and retrieves data from the Bus.sub.-- Data bus 412 during the Command and Response cycles. The switch controller state machine 414 formats the command information to be transmitted to the switch matrix 106 by means of a sequencer 416. The switch control logic also maintains a switch configuration shadow register 418 that stores data representing the current configuration of the switch matrix 106.

Finally, the micro-controll