The current invention provides a timer circuit for timing a plurality of time periods. The timer circuit has a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values. A first timing signal generator generates a first timing signal to indicate the expiry of a first time period by detecting the first occurrence of the second logic value (0), in a subset of the set of logic states at the set of state outputs. A second timing signal generator generates a second timing signal to indicate the expiry of a second time period by detecting a predetermined combination of logic values at the set of state outputs.
A background calibrated A/D converter includes a random time interval generator that initiates background calibration at randomly selected time instants to increase the spurious-free dynamic range of the A/D converter.
