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Memory circuitry having bus interface for receiving information in packets and access time registers    
United States Patent5606717   
Link to this pagehttp://www.wikipatents.com/5606717.html
Inventor(s)Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
AbstractAn interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a plurality of semiconductor circuits. The interfacing circuitry is coupled to the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. The interfacing circuitry resides inside the semiconductor circuit and includes a decoder for decoding the packets received to identify the data, addresses, and control information. A control logic circuitry is coupled to the decoder circuitry for controlling device operation of the first semiconductor circuit in accordance with the data, addresses, and control information received. A register circuitry is coupled to the decoder and the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting reply information through the multiline bus in response to the data, addresses, and control information received. The register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information.
   














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Drawing from US Patent 5606717
Memory circuitry having bus interface for receiving information in

     packets and access time registers - US Patent 5606717 Drawing
Memory circuitry having bus interface for receiving information in packets and access time registers
Inventor     Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Owner/Assignee     Rambus, Inc. (Mountain View, CA)
Patent assignment
All assignments
Publication Date     February 25, 1997
Application Number     07/847,651
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     March 5, 1992
US Classification     710/36 710/3 710/8 710/10 710/104 710/109 710/112 710/119 711/100
Int'l Classification     G06F 013/00
Examiner     Shin; Christopher B.
Assistant Examiner    
Attorney/Law Firm     Blakeley, Sokoloff, Taylor & Zafman
Address
Parent Case     This is a divisional of application Ser. No. 07/510,898, filed Apr. 18, 1990.
Priority Data    
USPTO Field of Search     395/275 395/200 395/550 395/284 395/288 395/310 395/287 395/290 395/292 395/299 395/285 398/821 398/822 398/823 398/824 398/825 398/826 398/827 398/828 398/829 398/830 398/831 398/832 398/833 398/834 398/835 398/836 398/837 398/838 398/839 398/840 398/841 398/842 398/843 398/844 398/845 398/846 398/847 398/848 398/849 398/850 398/851 398/852 398/853 398/854 398/855 398/856 398/857 398/858 398/859 398/860 398/861 398/862 398/863 398/864 398/865 398/866 398/867
Patent Tags     memory circuitry bus interface receiving information in packets access time registers
   
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