 |
Claims  |
|
|
What is claimed is:
1. A delay locked loop circuit, comprising:
an arbiter circuit for comparing an input signal of a first frequency to an
output signal of a second frequency, and in response, providing a retard
signal in response to receiving an enable signal;
a control circuit for receiving the retard signal, and in response,
providing a control voltage, the control voltage having a magnitude
relative to a difference between a transition of the input signal and a
transition of the output signal;
a voltage controlled delay circuit, coupled to the control circuit, for
receiving the control voltage, and in response, adjusting the phase of the
output signal with respect to the input signal; and
a collapse detector circuit, the collapse detector circuit having an input
terminal coupled to the voltage controlled delay circuit for detecting
when the output signal has not transitioned within a predetermined time,
wherein the predetermined time is greater than at least one clock cycle of
the input signal, and in response to detecting that the output signal has
not transitioned within the predetermined time, the collapse detector
circuit providing a collapse detector signal to the control circuit for
causing the output signal to transition.
2. The delay locked loop circuit of claim 1, wherein the arbiter circuit
comprises:
a first logic gate having a first input terminal for receiving the input
signal, a second input terminal for receiving the enable signal, and an
output terminal;
a second logic gate having a first input terminal for receiving the output
signal, a second input terminal for receiving the enable signal, and an
output terminal;
a third logic gate having a first input terminal coupled to the output
terminal of the first logic gate, a second input terminal, and an output
terminal;
a fourth logic gate having a first input terminal coupled to the output
terminal of the second logic gate, a second input terminal coupled to the
output terminal of the third logic gate, and an output terminal coupled to
the second input terminal of the third logic gate;
a first register having an input terminal coupled to the output terminal of
the third logic gate, a control terminal for receiving the enable signal,
and an output terminal;
a second register having an input terminal coupled to the output terminal
of the fourth logic gate, and a control terminal for receiving the enable
signal; and
a third register having an input terminal coupled to the output terminal of
the first register, a control terminal for receiving the enable signal,
and an output terminal for providing the retard signal.
3. The delay locked loop circuit of claim 2, wherein the tint, second,
third, and fourth logic gates are each characterized as performing a NAND
logic function.
4. The delay locked loop circuit of claim 1, wherein the input signal and
the output signal are characterized as being ECL (emitter-coupled logic)
signals.
5. The delay locked loop circuit of claim 1, wherein the control circuit
comprises:
an inverter having an input terminal for receiving the retard signal, and
an output terminal for providing the control voltage;
a first current source having a first terminal coupled to a first power
supply voltage terminal, and a second terminal coupled to the inverter;
a second current source having a first terminal coupled to a second power
supply voltage terminal, and a second terminal coupled to the inverter;
and
a capacitor having a first terminal coupled to the output terminal of the
inverter, and a second terminal coupled to the first power supply voltage
terminal.
6. The delay locked loop circuit of claim 1, wherein the voltage controlled
delay circuit comprises:
a first differential amplifier having first and second transistors, a first
resistive element being coupled between a first power supply voltage
terminal and a first current electrode of the first transistor, a second
resistive element being coupled between the first power supply voltage
terminal and a first current electrode of the second transistor, the first
differential amplifier for receiving true and complement components of the
enable signal, and an output terminal;
a variable current source, coupled to the second current electrodes of the
first and second transistors, for receiving the control voltage, and in
response, providing a current source for the first differential amplifier
proportional to the magnitude of the control voltage;
a second differential amplifier having third and fourth transistors, a
third resistive element being coupled between the first power supply
voltage terminal and a first current electrode of the third transistor, a
fourth resistive element being coupled between the first power supply
voltage terminal and a first current electrode of the fourth transistor, a
control electrode of the third transistor coupled to the first current
electrode of the first transistor, and a control electrode of the fourth
transistor coupled to the first current electrode of the second
transistor; and
a latch circuit, coupled to the second differential amplifier, for setting
a switching point of the second differential amplifier.
7. The delay locked loop circuit of claim 6, wherein the first, second,
third, and fourth transistors are bipolar transistors.
8. The delay locked loop circuit of claim 6, wherein the latch circuit
comprises:
a fifth transistor having a first current electrode coupled to the first
power supply voltage terminal, a control electrode coupled to the first
current electrode of the fourth transistor, and a second current electrode
coupled to a second power supply voltage terminal; and
a sixth transistor having a first current electrode coupled to the first
power supply voltage terminal, a control electrode coupled to the first
current electrode of the third transistor, and a second current electrode
coupled to the second power supply voltage terminal.
9. An integrated circuit memory having a delay locked loop circuit, the
delay locked loop circuit comprising:
an arbiter circuit for comparing an input signal of a first frequency to an
output signal of a second frequency, and in response, providing a retard
signal in response to receiving an enable signal;
a control circuit for receiving the retard signal, and in response,
providing a control voltage, the control voltage having a magnitude
relative to a difference between a transition of the input signal and a
transition of the output signal;
a voltage controlled delay circuit, coupled to the control circuit, for
receiving the control voltage, and in response, adjusting a phase of the
output signal with respect to the input signal; and
a collapse detector circuit, the collapse detector circuit having an input
terminal coupled to the voltage controlled delay circuit for detecting
when the output signal has not transitioned within a predetermined time,
wherein the predetermined time is greater than at least one clock cycle of
the input signal, and in response to detecting that the output signal has
not transitioned within the predetermined time, the collapse detector
circuit providing a collapse detector signal to the control circuit, for
causing the output signal to transition.
10. The integrated circuit memory of claim 9, wherein the arbiter circuit
comprises:
a first logic gate having a first input terminal for receiving the input
signal, a second input terminal for receiving the enable signal, and an
output terminal;
a second logic gate having a first input terminal for receiving the output
signal, a second input terminal for receiving the enable signal, and an
output terminal;
a third logic gate having a first input terminal coupled to the output
terminal of the first logic gate, a second input terminal, and an output
terminal;
a fourth logic gate having a first input terminal coupled to the output
terminal of the second logic gate, a second input terminal coupled to the
output terminal of the third logic gate, and an output terminal coupled to
the second input terminal of the third logic gate;
a first register having an input terminal coupled to the output terminal of
the third logic gate, a control terminal for receiving the enable signal,
and an output terminal;
a second register having an input terminal coupled to the output terminal
of the fourth logic gate, and a control terminal for receiving the enable
signal; and
a third register having an input terminal coupled to the output terminal of
the first register, a control terminal for receiving the enable signal,
and an output terminal for providing the retard signal.
11. The integrated circuit memory of claim 10, wherein the first, second,
third, and fourth logic gates are each characterized as performing a NAND
logic function.
12. The integrated circuit memory of claim 9, wherein the input signal and
the output signal are characterized as being ECL (emitter-coupled logic)
signals.
13. The integrated circuit memory of claim 9, wherein the control circuit
comprises:
an inverter having an input terminal for receiving the retard signal, and
an output terminal for providing the control voltage;
a first current source having a first terminal coupled to a first power
supply voltage terminal, and a second terminal coupled to the inverter;
a second current source having a first terminal coupled to a second power
supply voltage terminal, and a second terminal coupled to the inverter;
and
a capacitor having a first terminal coupled to the output terminal of the
inverter, and a second terminal coupled to the first power supply voltage
terminal.
14. The integrated circuit memory of claim 9, wherein the voltage
controlled delay circuit comprises:
a first differential amplifier having first and second transistors, a first
resistive element being coupled between the first power supply voltage
terminal and a first current electrode of the first transistor, a second
resistive element being coupled between the first power supply voltage
terminal and a first current electrode of the second transistor, the first
differential amplifier for receiving true and complement components of the
enable signal, and an output terminal;
a variable current source, coupled to the second current electrodes of the
first and second transistors, for receiving the control voltage, and in
response, providing a current source for the first differential amplifier
proportional to the magnitude of the control voltage;
a second differential amplifier having third and fourth transistors, a
third resistive element being coupled between the first power supply
voltage terminal and a first current electrode of the third transistor, a
fourth resistive element being coupled between the first power supply
voltage terminal and a first current electrode of the fourth transistor, a
control electrode of the third transistor coupled to the first current
electrode of the first transistor, and a control electrode of the fourth
transistor coupled to the first current electrode of the second
transistor; and
a latch circuit, coupled to the second differential amplifier, for setting
a switching point of the second differential amplifier.
15. The integrated circuit memory of claim 14, wherein the first, second,
third, and fourth transistors are bipolar transistors.
16. The integrated circuit memory of claim 14, wherein the latch circuit
comprises:
a fifth transistor having a first current electrode coupled to the first
power supply voltage terminal, a control electrode coupled to the first
current electrode of the fourth transistor, and a second current electrode
coupled to a second power supply voltage terminal; and
a sixth transistor having a first current electrode coupled to the first
power supply voltage terminal, a control electrode coupled to the first
current electrode of the third transistor, and a second current electrode
coupled to the second power supply voltage terminal.
17. An integrated circuit memory having a delay locked loop circuit, the
delay locked loop circuit comprising:
an arbiter circuit for comparing a first periodic input signal of a first
frequency to a periodic output signal of a second frequency in response
receiving a second periodic input signal of the first frequency, the
arbiter circuit for determining which of the first periodic input signal
and the periodic output signal transition first, and in response to the
first periodic input signal transitioning before the periodic output
signal, providing a control signal of a first logic state, and in response
to the first periodic input signal transitioning after the periodic output
signal, providing the control signal of a second logic state, and wherein
the first frequency is different from the second frequency;
a control circuit having an input terminal for receiving the control
signal, and for providing a first control voltage when the control signal
is of the first logic state and for providing a second control voltage
when the control signal is of the second logic state;
a voltage controlled delay circuit, coupled to the control circuit, for
receiving the first and second control voltages, and in response,
adjusting a propagation delay provided by the voltage controlled delay
circuit for adjusting a phase of the output signal with respect to the
input signal; and
a collapse detector circuit, the collapse detector circuit having an input
terminal coupled to the voltage controlled delay circuit for detecting
when the output signal has not transitioned within a predetermined time,
wherein the predetermined time is greater than at least one clock cycle of
the first periodic input signal, and in response to detecting that the
periodic output signal has not transitioned within the predetermined time,
the collapse detector circuit providing a collapse detector signal to the
control circuit, thereby decreasing the propagation delay of the voltage
controlled delay circuit to cause the periodic output signal to
transition.
18. The integrated circuit memory of claim 17, wherein the arbiter circuit
comprises:
a first logic gate having a first input terminal for receiving the first
periodic input signal, a second input terminal for receiving the second
periodic input signal, and an output terminal;
a second logic gate having a first input terminal for receiving the
periodic output signal, a second input terminal for receiving the second
periodic input signal, and an output terminal;
a third logic gate having a first input terminal coupled to the output
terminal of the first logic gate, a second input terminal, and an output
terminal;
a fourth logic gate having a first input terminal coupled to the output
terminal of the second logic gate, a second input terminal coupled to the
output terminal of the third logic gate, and an output terminal coupled to
the second input terminal of the third logic gate;
a first register having an input terminal coupled to the output terminal of
the third logic gate, a control terminal for receiving the second periodic
input signal, and an output terminal;
a second register having an input terminal coupled to the output terminal
of the fourth logic gate, and a control terminal for receiving the second
periodic input signal; and
a third register having an input terminal coupled to the output terminal of
the first register, a control terminal for receiving the second periodic
input signal, and an output terminal for providing the control signal.
19. The integrated circuit memory of claim 18, wherein the first periodic
input signal and the periodic output signal are characterized as being ECL
(emitter-coupled logic) signals.
20. The integrated circuit memory of claim 17, wherein the voltage
controlled delay circuit comprises:
a first differential amplifier having first and second transistors, a first
resistive element being coupled between the first power supply voltage
terminal and a first current electrode of the first transistor, a second
resistive element being coupled between the first power supply voltage
terminal and a first current electrode of the second transistor, the first
differential amplifier for receiving true and complement components of the
second periodic input signal, and an output terminal;
a variable current source, coupled to the second current electrodes of the
first and second transistors, for receiving the control voltage, and in
response, providing a current source for the first differential amplifier
proportional to the magnitude of the control voltage;
a second differential amplifier having third and fourth transistors, a
third resistive element being coupled between the first power supply
voltage terminal and a first current electrode of the third transistor, a
fourth resistive element being coupled between the first power supply
voltage terminal and a first current electrode of the fourth transistor, a
control electrode of the third transistor coupled to the first current
electrode of the first transistor, and a control electrode of the fourth
transistor coupled to the first current electrode of the second
transistor; and
a latch circuit, coupled to the second differential amplifier, for setting
a switching point of the second differential amplifier. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
CROSS REFERENCE TO RELATED APPLICATIONS
1. A related application entitled "Synchronous Memory Having Parallel
Output Data Paths", by Flannagan et al., and having U.S. Pat. No.
5,402,389, was filed concurrently herewith, and assigned to the assignee
hereof.
2. A related application entitled "Write Control For A Memory Using A Delay
Locked Loop", by Flannagan et al., and having U.S. Pat. No. 5,440,514, was
filed concurrently herewith, and assigned to the assignee hereof.
3. A related application entitled "Pipelined Memory Having Synchronous And
Asynchronous Operating Modes", by Childs et al., and having U.S. Pat. No.
5,384,737, was filed concurrently herewith, and assigned to the assignee
hereof.
4. A related application entitled "Memory Having Bit Line Load With
Automatic Bit Line Precharge And Equalization", by Flannagan et al., and
having U.S. Pat. No. 5,416,744, was filed concurrently herewith, and
assigned to the assignee hereof.
FIELD OF THE INVENTION
This invention relates generally to delay locked loop circuits, and more
particularly, to a delay locked loop for detecting the phase difference of
two signals having different frequencies.
BACKGROUND OF THE INVENTION
A phase locked loop is used to synchronize a phase of an output signal with
the phase of an input signal. A typical phase locked loop includes a phase
comparator, and voltage controlled oscillator. The phase comparator
compares the phase of an output signal of the voltage controlled
oscillator with the phase of the input signal. An output signal
representing the phase difference is provided by the phase comparator. A
delay locked loop differs from a phase locked loop in that in a voltage
controlled delay (VCD) is used instead of a voltage controlled oscillator.
Like the phase locked loop, the delay locked loop determines the phase
difference between two signals and provides an output signal to adjust the
delay of the VCD to "lock" the phase of the two signals. A problem with
the conventional delay locked loop is that it can only phase lock two
signals of the same frequency.
Two conventional circuits for providing a VCD in a delay locked loop are
the shunt-capacitor type VCD and the starved-inverter VCD. In
shunt-capacitor VCD, a capacitor with fixed capacitance is connected to
the output of a CMOS inverter through a shunt transistor. By providing a
gate-to-source voltage (VGS) to the shunt transistor, the transconductance
of the shunt transistor can be increased which increases a capacitive
loading at an output terminal of the CMOS inverter. By adjusting the
voltage at the gate of shunt transistor, a predetermined delay can be
introduced in the rise and fall times of the inverter output.
In the starved-inverter VCD, an N-channel transistor of a conventional two
transistor inverter is connected in series with another N-channel
transistor (known as a current-starving transistor). The gate of the
current-starving transistor is controlled by a voltage which limits the
amount of current that can be discharged through the inverter. The higher
the VGS of the current-starving transistor, the faster the output terminal
of the inverter can be reduced to ground potential.
In the shunt-capacitor VCD, the capacitive loading of the output is varied,
while the inverter current stays fixed. In the starved-inverter VCD, the
load capacitance remains fixed, while the inverter current is varied.
These two designs work fine for most of VCD applications. However, both
the shunt-capacitor VCD and the starved-inverter VCD require that the
input signals of the VCD be CMOS (complementary metal-oxide semiconductor)
level signals. If the input signals are relatively small signals, such as
ECL (emitter-coupled logic) level signals, then they need to be converted
to CMOS levels before being applied to the VCD. Also, the output signals
of the VCD have to be reconverted to small signal, or ECL level signals.
The level conversions, provide additional undesirable delay in the delay
locked loop.
Another problem with the shunt-capacitor VCD is that it does not have a
good maximum delay to minimum delay ratio. Thus, in order to increase the
maximum delay, additional delay stages are needed. Adding delay stages to
increase the maximum delay, also increases the minimum delay. The
additional delay stages also increases layout area required for the VCD.
The starved-inverter VCD has a good maximum to minimum delay ratio.
However, most of delay occurs when V.sub.GS is near the threshold voltage
(V.sub.T) of the current-starving transistor. This means that the
starved-inverter VCD is very sensitive to the noise.
SUMMARY OF THE INVENTION
Accordingly, there is provided, in one form, a delay locked loop circuit
having an arbiter circuit, a control circuit, and a voltage controlled
delay circuit. The arbiter circuit compares an input signal of a first
frequency to an output signal of a second frequency, and provides a retard
signal in response to receiving an enable signal. The control circuit
receives the retard signal, and in response, provides a control voltage,
the control voltage having a magnitude relative to a difference between a
transition of the input signal and a transition of the output signal. The
voltage controlled delay circuit is coupled to the control circuit, and
receives the control voltage. In response, the voltage controlled delay
circuit adjusts the phase of the output signal with respect to the input
signal. These and other features and advantages will be more clearly
understood from the following detailed description taken in conjunction
with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates in block diagram form, a memory in accordance with the
present invention.
FIG. 2 illustrates in partial block diagram form and partial logic diagram
form, a portion of the memory of FIG. 1.
FIG. 3 illustrates in block diagram form, the read control delay locked
loop of FIG. 1.
FIG. 4 illustrates in block diagram form, the dummy path of FIG. 1.
FIG. 5 illustrates in schematic diagram form, an output path register of
FIG. 2.
FIG. 6 illustrates in schematic diagram form, the output enable register of
FIG. 2.
FIG. 7 illustrates in schematic diagram form, the final amplifier of FIG.
2.
FIG. 8 illustrates in partial logic diagram form and partial block diagram
form, the arbiter circuit of FIG. 3.
FIG. 9 illustrates in schematic diagram form, the voltage controlled delay
circuit of FIG. 3.
FIG. 10 illustrates in schematic diagram form, the VCD control circuit of
FIG. 3.
FIG. 11 illustrates in partial logic diagram form and partial schematic
diagram form, the collapse detector circuit of FIG. 3.
FIG. 12 illustrates in block diagram form the write control delay locked
loop of FIG. 1.
FIG. 13 illustrates in partial schematic diagram form and partial logic
diagram form, the voltage controlled delay circuits of FIG. 12.
FIG. 14 illustrates in partial schematic diagram form and partial logic
diagram form, the arbiter circuit of FIG. 12.
FIG. 15 illustrates in partial schematic diagram form and partial logic
diagram form, the VCD control circuit of FIG. 12.
FIG. 16 illustrates in partial schematic diagram form and partial logic
diagram form, the collapse detector circuit of FIG. 12.
FIG. 17 illustrates in partial schematic diagram form and partial logic
diagram form, the bit line load circuit of FIG. 1.
FIG. 18 illustrates a timing diagram of various signals of the memory of
FIG. 1 in three stage pipeline mode.
FIG. 19 illustrates a timing diagram of various signals of the memory of
FIG. 1 in two stage pipeline mode.
FIG. 20 illustrates a timing diagram of various signals of the memory of
FIG. 1 in asynchronous mode during read and write cycles.
DESCRIPTION OF A PREFERRED EMBODIMENT
| | |
