An analog signal monitoring (ASM) circuit (40, 42) non-intrusively monitors an analog circuit (20) within an electronic system. The ASM circuit (40,42) comprises input circuitry (80) that receives a plurality of analog signal inputs while the analog circuit (20) operates in a functional mode. Translation circuitry (142) associates with the input circuitry (80) for converting the analog signal inputs into digital signal representations of the analog signal inputs. Output circuitry (58) associates with the translation circuitry to output the digital representations. Control circuitry (114) controls the translation and output circuitry while the analog circuit (20) is in a functional mode. The ASM circuit (40, 42) also include an event qualification circuit (68) that includes input circuitry (236) to receive the digital signal representations, compare circuitry (104) to compare the received digital representations to an expected value and output a matched signal when a compared condition is identified.
A testable circuit comprises a signal path having a time-dependent response behavior (for example, a high-pass filter behavior). The signal path is tested for faults. To this end, the circuit is switched to a test mode in which the signal path is isolated from other signal paths. Subsequently, a test signal containing a signal transition is applied to the input of the signal path and it is tested whether the signal on the output of the signal path at any instant exceeds a threshold level during a predetermined time interval after the transition. The result is loaded into a register and read from the circuit.
An integrated circuit device has an analog block connected to a sigma-delta modulator. Analog signals from internal nodes in the analog block are fed to the sigma-delta modulator. The sigma-delta modulator produces digital representations of the analog signals. The digital representations are forwarded to a processor for analysis of the internal node signal. The above structure may be integrated within the framework of existing digital test structures to form a built-in self-test scheme.
An image reading apparatus disclosed in this invention has first and second line sensors. The output from the first line sensor is compressed by a first compression circuit, and the output from the second line sensor is compressed by a second compression circuit. Furthermore, control is made to output image data for one page compressed by the first compression circuit, and thereafter, to output image data for one page compressed by the second compression circuit. The first compression circuit can operate at a higher speed than the second compression circuit.
A method to test an integrated circuit design on a computer simulation loads a desired simulation test vector in parallel into a scan chain (30). The simulation loads the desired vector at a slight offset or upstream shift allowing several serial shifts of the loaded vector through the scan chain (32). After the serial shifts, the initial IC state is set for executing an IC function (34). The IC function includes applying an input on the external pins and receiving an output from the external pins, given the initial IC state loaded by the simulation After executing the IC function, the simulation unloads the resulting IC state in parallel (36) and compares the resulting IC state to a target vector (38).
The invention relates to a method of testing interconnections in integrated circuit (IC) assemblies. Hereto, a test signal is applied to an IC pin (110) providing an input terminal to the interconnection. In known methods, such as the boundary-scan method, a response signal is measured on an output terminal of the interconnection, provided by a further IC pin. According to the invention, however, a response signal is evaluated which is generated on the same terminal (110) as to which the test signal is applied. This has the advantage that the method of the invention can be applied when only one end of the interconnect to be tested can be supplied with appropriate test hardware. The method is particularly suited for testing a capacitance (195) between an IC pin (110) and a supply line, e.g. a ground line.
