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Hardware logic emulation system with memory capability    
United States Patent5612891   
Link to this pagehttp://www.wikipatents.com/5612891.html
Inventor(s)Butts; Michael R. (Portland, OR); Batcheller; Jon A. (Newberg, OR)
AbstractA plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
   














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Hardware logic emulation system with memory capability - US Patent 5612891 Drawing
Hardware logic emulation system with memory capability
Inventor     Butts; Michael R. (Portland, OR); Batcheller; Jon A. (Newberg, OR)
Owner/Assignee     Quickturn Design Systems, Inc. (Mountain View, CA)
Patent assignment
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Publication Date     March 18, 1997
Application Number     08/470,751
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     June 6, 1995
US Classification     716/16
Int'l Classification     H03K 017/693
Examiner     Trans; Vincent N.
Assistant Examiner    
Attorney/Law Firm     Lyon & Lyon
Address
Parent Case     RELATED APPLICATION DATA This is a continuation of application Ser. No. 08/245,310 filed on May 17, 1994, now U.S. Pat. No. 5,452,231, which is a continuation of application Ser. No. 07/923,361 filed on Jul. 31, 1992, now abandoned, which was a division of application Ser. No. 07/698,734 filed on May 10, 1991, now abandoned, which was a continuation-in-part of application Ser. No. 07/417,196 filed on Oct. 4, 1989, now U.S. Pat. No. 5,036,473, which was a continuation-in-part of application Ser. No. 07/254,463 filed on Oct. 5, 1988, now abandoned.
Priority Data    
USPTO Field of Search     364/488 364/489 364/490 364/491 364/578 395/500 326/39 326/41 340/825.83
Patent Tags     hardware logic emulation memory capability
   
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