Method and apparatus for enabling an assembly of non-standard memory components to emulate a standard memory module

Claims

What is claimed is:

1. Logic means for enabling a memory module comprised of an assembly of non-standard memory devices to emulate an industry standard memory module, the non-standard memory module including

a plurality of addressable memory devices, each of which is responsive to a combination of signals including at least one Column Address Strobe (CAS) signal, one Row Address Strobe (RAS) signal, and address input signals A.sub.0 -A.sub.n+1, one less than the number of address signals received by said memory module, and is operative to receive and output data signals via data input/output pins, and

a circuit board for supporting said memory devices and having

connector means for receiving control signals and for receiving and outputting the data signals, the control signals including at least a plurality of CAS signals, a plurality of RAS signals, a WRITE ENABLE signal, and a plurality of computer-generated address input signals A.sub.0 -A.sub.n, the data signals including a plurality of D.sub.0 -D.sub.m data signals where m is a function of the number of said memory devices,

means for coupling the control signals from said connector means to said memory devices, and

a databus for coupling the data signals between the data input/output pins of said memory devices and said connector means,

said logic means forming a part of said means for coupling the control signals to said memory devices, and comprising:

a logic circuit responsive to said plurality of CAS signals and said plurality of RAS signals and operative to generate a RAS L signal, a RAS H signal, a first extra address signal A.sub.n+1 L, and a second extra address signal A.sub.n+1 H,

said RAS L signal providing a row address strobe for a first group L of said memory devices,

said RAS H signal providing a row address strobe for a second group H of said memory devices,

said address signal A.sub.n+1 L providing an extra address input for use with said address input signals A.sub.0 -A.sub.n to address said first group of memory devices, and

said address signal A.sub.n+1 H providing an extra address input for use with said address input signals A.sub.0 -A.sub.n to address said second group of memory devices.

2. Logic means as recited in claim 1 wherein said assembly of non-standard memory devices are grouped into four memory blocks respectively responsive to four externally generated CAS signals /CAS0, /CAS1, /CAS2, and /CAS3, and wherein said logic circuit is configured to implement the following truth table:

__________________________________________________________________________ Truth Table Inputs Outputs Inputs Outputs Operation /RAS0 /RAS1 /RASL A10L /RAS2 /RAS3 /RASH A10H __________________________________________________________________________ REFRESH L 0 0 0 0 0 0 0 0 REFRESH H 0 0 0 1 0 0 0 1 READ/WRITE L 0 1 0 1 0 1 0 1 READ/WRITE H 1 0 0 0 1 0 0 0 SET UP 1 1 1 1 1 1 1 1 __________________________________________________________________________

wherein /RAS0, /RAS1, /RAS2, and /RAS3 represent four externally generated RAS signals;

two of said four memory blocks being included within said group L and two of said four memory blocks being included within said group H, wherein said group L is responsive to output signals /RASL and A10L and said group H is responsive to output signals /RAS H and A10H.

3. Logic means as recited in claim 2 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.9 memory block with a parity bit.

4. Logic means as recited in claim 3 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.8 memory block without a parity bit.

5. Logic means as recited in claim 4 wherein said logic circuit is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said /RAS L signal and said /RAS H signal which causes a refresh signal to be initiated.

6. Logic means as recited in claim 5 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said /RAS L signal and said /RAS H signal which causes sufficient set-up time for said memory devices to start a new cycle.

7. Logic means as recited in claim 1 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.9 memory block with a parity bit.

8. Logic means as recited in claim 1 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.8 memory block without a parity bit.

9. Logic means as recited in claim 1 wherein said logic circuit is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said /RAS L signal and said /RAS H signal which causes a refresh signal to be initiated.

10. Logic means as recited in claim 1 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said /RAS L signal and said /RAS H signal which causes sufficient set-up time for said memory devices to start a new cycle.

11. A memory module including an assembly of non-standard memory devices and adapted to emulate an industry standard memory module, comprising:

a plurality of addressable memory devices, each of which is responsive to a combination of signals including at least one Column Address Strobe (CAS) signal, one Row Address Strobe (RAS) signal, and address input signals A.sub.0 -A.sub.n+1, n being one less than the number of address signals received by said memory module, and is operative to receive and output data signals via data input/output pins;

a circuit board for supporting said memory devices and having

connector means for receiving control signals and for receiving and outputting the data signals, the control signals including at least a plurality of CAS signals, a plurality of RAS signals, and a plurality of computer-generated address input signals A.sub.0 -A.sub.n, the data signals including a plurality of D.sub.0 -D.sub.m data signals where m is a function of the number of said memory devices,

means for coupling the control signals from said connector means to said memory devices, and

a databus for coupling the data signals between the data input/output pins of said memory devices and said connector means,

logic means forming a part of said means for coupling the control signals to said memory devices, and comprising:

a logic circuit responsive to said plurality of CAS signals and said plurality of RAS signals and operative to generate a RAS L signal, a RAS H signal, a first extra address signal A.sub.n+1 L, and a second extra address signal A.sub.n+1 H,

said RAS L signal providing a row address strobe for a first group L of said memory devices,

said RAS H signal providing a row address strobe for a second group H of said memory devices,

said address signal A.sub.n+1 L providing an extra address input for use with said address input signals A.sub.0 -A.sub.n to address said first group L of memory devices, and

said address signal A.sub.n+1 H providing an extra address input for use with said address input signals A.sub.0 -A.sub.n to address said second group H of memory devices.

12. A memory module as recited in claim 11 wherein said plurality of addressable memory devices are grouped into four memory blocks respectively responsive to four externally generated CAS signals /CAS0, /CAS1, /CAS2, and /CAS3, and wherein said logic circuit is configured to implement the following truth table:

__________________________________________________________________________ Truth Table Inputs Output Inputs Output Operation /RAS0 /RAS1 /RASL A10L /RAS2 /RAS3 /RASH A10H __________________________________________________________________________ REFRESH L 0 0 0 0 0 0 0 0 REFRESH H 0 0 0 1 0 0 0 1 READ/WRITE L 0 1 0 1 0 1 0 1 READ/WRITE H 1 0 0 0 1 0 0 0 SET UP 1 1 1 1 1 1 1 1 __________________________________________________________________________

wherein /RAS0, /RAS1, /RAS2, and /RAS3 represent four externally generated RAS signals;

two of said four memory blocks being included within said first group L and two of said four memory blocks being included within said second group H.

13. A memory module as recited in claim 12 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.9 memory block with a parity bit.

14. A memory module as recited in claim 13 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.8 memory block without a parity bit.

15. A memory module as recited in claim 14 wherein said logic circuit is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said /RAS L signal and said /RAS H signal which causes a refresh signal to be initiated.

16. A memory module as recited in claim 15 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said /RAS L signal and said /RAS H signal which causes sufficient set-up time for said memory devices to start a new cycle.

17. A memory module as recited in claim 11 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.9 memory block with a parity bit.

18. A memory module as recited in claim 11 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.8 memory block without a parity bit.

19. A memory module as recited in claim 11 wherein said logic circuit is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said /RAS L signal and said /RAS H signal which causes a refresh signal to be initiated.

20. A memory module as recited in claim 11 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said /RAS L signal and said /RAS H signal which causes sufficient set-up time for said memory devices to start a new cycle.

21. A method of emulating an industry standard memory module using non-standard memory devices in a memory module, comprising:

selecting a particular combination of memory devices and organizing such devices in groups such that data of a particular word length can be input thereto and output therefrom via a databus, such that less than all of the available memory locations can be addressed by externally generated address signals, and such that each memory device can be strobed by an externally generated CAS signal;

providing logic means responsive to externally generated CAS signals and RAS signals, and operative to develop new RAS signals for strobing said memory devices, and operative to develop additional address signals for permitting the addressing of memory locations not addressable by said externally generated address signals; and

using said logic means to facilitate the input and output of data to and from said memory module via said data bus.

22. A method as recited in claim 21 wherein said assembly of non-standard memory devices includes four memory blocks, two of said four memory blocks being included within a first group L and two of said four memory blocks being included within a second group H, each of the memory blocks respectively responsive to four externally generated CAS signals /CAS0, /CAS1, /CAS2, and /CAS3, said logic means being configured to implement the following truth table:

__________________________________________________________________________ Truth Table Inputs Outputs Inputs Outputs Operation /RAS0 /RAS1 /RASL A10L /RAS2 /RAS3 /RASH A10H __________________________________________________________________________ REFRESH L 0 0 0 0 0 0 0 0 REFRESH H 0 0 0 1 0 0 0 1 READ/WRITE L 0 1 0 1 0 1 0 1 READ/WRITE H 1 0 0 0 1 0 0 0 SET UP 1 1 1 1 1 1 1 1 __________________________________________________________________________

wherein /RAS0, /RAS1, /RAS2, and /RAS3 represent four externally generated RAS signals, /RAS L and /RAS H are said new RAS signals generated by said logic means for respectively strobing said first group L and said second group H of said memory blocks, and A10L and A10H are said additional address signals generated by said logic means for addressing said first group L and said second group H respectively.

23. A method as recited in claim 22 wherein each of said memory blocks is comprised of one or more of said memory devices configured to form a 2M.times.9 memory block with a parity bit.

24. A method as recited in claim 23 wherein each of said memory blocks is comprised of one or more of said memory devices configured to form a 2M.times.8 memory block without a parity bit.

25. A method as recited in claim 24 wherein said logic means is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said /RAS L signal and said /RAS H signal which causes a refresh signal to be initiated.

26. A method as recited in claim 25 wherein said logic means is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said /RAS L signal and said /RAS H signal which causes sufficient set-up time for said memory devices to start a new cycle.

27. A method as recited in claim 21 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.9 memory block with a parity bit.

28. A method as recited in claim 21 wherein each of said memory blocks is comprised of at least one of said memory devices configured to form a 2M.times.8 memory block without a parity bit.

29. A method as recited in claim 21 wherein said logic means is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said /RAS L signal and said /RAS H signal which causes a refresh signal to be initiated.

30. A method as recited in claim 21 wherein said logic means is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said /RAS L signal and said /RAS H signal which causes sufficient set-up time for said memory devices to start a new cycle.

31. In a memory module including:

a plurality of addressable memory devices, each of which is responsive to a combination of signals including at least one Column Address Strobe (CAS) signal, a Row Address Strobe (RAS) signal, and address signals A.sub.0 -A.sub.n+1, n being one less than the number of address signals received by said memory module, and is operative to receive and output data signals via data input/output pins;

a circuit board for supporting said memory devices and having

connector means for receiving control signals and for receiving and outputting the data signals, the control signals including at least a plurality of CAS signals, a plurality of RAS signals, and a plurality of computer-generated address signals A.sub.0 -A.sub.n, the data signals including a plurality of D.sub.0 -D.sub.m data signals where m is a function of the number of said memory devices,

means for coupling said CAS signals and said RAS signals from said connector means to a logic means and for coupling said CAS signals and said address signals to said memory devices, and

a databus for coupling the data signals between the data input/output pins of said memory devices and said connector means,

an improved means for coupling the control signals to said memory devices, comprising:

a logic circuit responsive to said CAS signals and said RAS signals and operative to generate at least one new RAS signal, and at least one extra address signal A.sub.n+1,

said new RAS signal providing a row address strobe for said memory devices, and

said extra address signal A.sub.n+1 providing an extra address signal for use with said address signals A.sub.0 -A.sub.n to address said memory devices.

32. In a memory module as recited in claim 31 wherein said logic circuit is responsive to a predetermined relationship between said RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said at least one new RAS signal which causes a refresh signal to be initiated.

33. In a memory module as recited in claim 32 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said at least one new RAS signal which causes sufficient set-up time for said memory devices to start a new cycle.

34. In a memory module as recited in claim 31 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said at least one new RAS signal which causes sufficient set-up time for said memory devices to start a new cycle.

35. A memory module comprising:

a plurality of addressable memory devices, each of which is responsive to a combination of signals including a Column Address Strobe (CAS) signal, a Row Address Strobe (RAS) signal, and address signals A.sub.0 -A.sub.n+1, n being one less than the number of address signals received by said memory module, and is operative to receive and output data signals via data input/output pins;

a circuit board for supporting said memory devices and having

connector means for receiving control signals and for receiving and outputting the data signals, the control signals including at least a plurality of CAS signals, a plurality of RAS signals, and a plurality of computer-generated address signals A.sub.0 -A.sub.n, the data signals including a plurality of D.sub.0 -D.sub.m data signals where m is a function of the number of said memory devices,

means for coupling said CAS signals and said RAS signals from said connector means to a logic means and for coupling said CAS signals and said address signals to said memory devices, and

a databus for coupling the data signals between the data input/output pins of said memory devices and said connector means,

said logic means forming a part of said means for coupling the control signals to said memory devices, and comprising

a logic circuit responsive to said plurality of CAS signals and said RAS signals and operative to generate at least one new RAS signal, and at least one extra address signal A.sub.n+1,

said new RAS signal providing a row address strobe for said memory devices, and

said extra address signal A.sub.n+1 providing an extra address signal for use with said address signals A.sub.0 -A.sub.n to address said memory devices.

36. A memory module as recited in claim 35 wherein said logic circuit is responsive to a predetermined relationship between said plurality of RAS signals and operative to generate a RAS precharge pulse t.sub.RP on said at least one new RAS signal which causes a refresh signal to be initiated.

37. A memory module as recited in claim 36 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said at least one new RAS signal which causes sufficient set-up time for said memory devices to start a new cycle.

38. A memory module as recited in claim 35 wherein said logic circuit is responsive to particular combinations of said plurality of RAS signals indicating read, write and refresh cycles, and further comprising:

means for detecting signals indicating the end of a read, write or refresh cycle; and

means for introducing a t.sub.RP pulse on said at least one new RAS signal which causes sufficient set-up time for said memory devices to start a new cycle.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of computer memory hardware. More particularly, the present invention relates to an improved memory circuit board apparatus designed to perform with computer systems notwithstanding the lack of an industry standard memory devices organization and providing for the use of certain types of memory devices having non-standard depths.

2. Brief Description of the Prior Art

A computer system typically requires a certain minimum amount of memory in order to operate at an acceptable level of processing speed. If more memory is added to the computer system, there will be a higher level of computational speed.

One type of memory module is the Single In Line Memory Module ("SIMM") wherein a number of memory devices (chips) are mounted on a small circuit board having an edge connector with a number of pins. These memory devices can be either dynamic random access memory devices ("DRAM") or static random access memory devices ("SRAM"). The number of addressable locations within the memory device is referred to as the depth of the device. Size or depth of memory devices is typically referred to in units of "K" and "M", with 1K being 1024 units and 1M being 1024K units.

SIMMs can be readily plugged into or removed from a system board designed to accept such SIMMs. The SIMMs receive all necessary power, ground, and logic signals from the system board.

In order to provide compatibility between computer system and memory modules from the various manufacturers, the JEDEC council of the Electronic Industries Association provides a number of industry standards. By designing and producing system boards and memory modules according to these standards, compatibility between the different system boards and memory modules is ensured. More specifically, JEDEC Standard No. 21-C covers memory modules and cards, including the 72-pin DRAM Module Family. Under this standard, the following memory configurations for 72-pin DRAM memory modules are specified:

TABLE 1 ______________________________________ Configuration Depth of Memory Device Banks ______________________________________ 256K .times. 36 256K 1 512K .times. 36 256K 2 1M .times. 36 1M 1 2M .times. 36 1M 2 4M .times. 36 4M 1 8M .times. 36 4M 2 ______________________________________

Note that the depths of the memory devices in Table 1 are 256K, 1M, or 4M. Since this standard supports either one or two banks of memory, certain new memory DRAMs with single Row Address Strobe ("/RAS") control signals cannot be used in the above configurations. For example, DRAMs such as the 512K.times.8 DRAM with single RAS control signal, the 2M.times.8 DRAM with single RAS control signal, and the 8M.times.8 DRAM with single RAS control signal are available (or will soon be available) but cannot be used in the above JEDEC specified configurations. However, they can be used in the following configurations:

TABLE 2 ______________________________________ Configuration Depth of Memory Device Banks ______________________________________ 512K .times. 32/36 512K 1 2M .times. 32/36 2M 1 8M .times. 32/36 8M 1 ______________________________________

Note that the depth of the memory devices in Table 2 includes 512K, 2M, and 8M. However, the above memory module configurations are not compatible with computer systems conforming to JEDEC standards because these configurations are not provided under the JEDEC standard.

More specifically, because computer systems conforming to the JEDEC standard do not accommodate 512K, 2M, or 8M memory devices on memory modules, they do not provide the needed address signals for these configurations. For example, under the JEDEC standard, a 2M.times.36 configuration has to use two banks of 1M deep memory devices (see Table 1), rather than one bank of 2M deep memory devices (see Table 2). A memory module using one bank of 2M deep memory devices will not function properly because the computer system only provides ten address signals to address 1M deep memory devices rather than the needed eleven address signals to address 2M deep memory devices. Specifically, the address signals A9 for the 512K deep DRAM, A10 for the 2M deep DRAM, and A11 for the 8M deep DRAMs are not provided. Thus, these memory devices cannot be used unless some specific logic is provided.

As the supply and demand of memory devices fluctuate and the memory devices of Table 2 become widely available and provide better price/density ratio, there is a strong incentive to use these non-standard configurations and memory devices. For example, 1M.times.4 DRAMs are becoming less available while 2M.times.8 DRAMs are becoming more readily available and their prices are dropping.

In addition to the cost consideration, using the nonstandard memory devices also reduces power consumption. By using only 1 bank of memory devices instead of two banks of memory devices as required under the JEDEC standard, less power is needed. Also, capacitive loading is drastically reduced, due to the use of fewer devices, thus providing better capability to increase the number of SIMMs installable in the computer system.

There are several problems presented in using memory devices not provided for under the JEDEC standard. Before discussing these problem, memory module configuration according to the JEDEC standard is explained in detail.

Referring now to FIG. 1 of the drawing, an electrical schematic depiction of a two bank, two megabit ("Mb") deep.times.36 memory module configuration according to the JEDEC standard specification is illustrated. This memory module is comprised of a circuit board, as suggested by the dashed lines 9, adapted to carry two banks 10 and 12 of memory blocks, and includes means for conducting a set of input signals 30-46, a set of output signals, and an output bus 47. Each bank in this configuration includes four 1Mb .times.9 memory blocks 14, 16, 18, and 20 in bank 10, and memory blocks 22, 24, 26, and 28 in bank 12. Each 1 Mb.times.9 memory block can be comprised of two 1 Mb.times.4 memory devices plus a 1 Mb.times.1 memory device, nine 1 Mb.times.1 memory devices, or other combinations of memory devices. Each memory device is a single IC chip contained within a standard device package. Under the JEDEC standard for 72 pin SIMMs, only 1M deep memory devices can be used instead of 2M deep memory devices.

There are a number of input signals to be applied to each of the memory devices. These signals include four Column Address Strobe ("CAS") signals, "/CAS0" input at 36, "/CAS1" input at 34, "/CAS2" input at 32, and "/CAS3" input at 30, four Row Address Strobe ("RAS") signals, "/RAS0" input at 38, "/RAS1" input at 40, "/RAS2" input at 42, and "/RAS3" input at 44, a Write Enable ("/WE") signal input at 45, and ten address signals (A0-A9) input at 46. There are also power input signals, ground signals, and an Output Enable ("/OE") signal which in the interest of simplicity are not shown. The /OE signal is typically grounded in this configuration.

Note that the /RAS, /CAS, /OE, and/WE signals are active low signals, meaning "ON" or active when there is a low voltage level on the line and "OFF" when there is a high voltage level on the line. Active low signals such as the CAS signals are commonly expressed as "/CAS", or with a horizontal bar over it. Further note that it is understood that the various signals are propagated on the circuit board to various components or pins via electrical traces or lines.

The CAS and RAS signals in conjunction allow addressing of each of the memory blocks. By activating the corresponding RAS and CAS signals each memory block can be individually selected. Once the memory block is selected, the specific location within the memory block is accessed via the address signals, A0-A9. With these ten address signals, 1M deep memory locations can be accessed. Depending on a high or low /WE signal, a read or write operation can be made to the addressed memory location.

In a read operation, the corresponding data from the addressed location is sent out to the data bus 47. For example, memory block 20 or 28 sends out 9 bits of data via a sub-bus 48 to the data bus 47; and memory block 18 or 26 sends out 9 bits of data via another sub-bus 50 to the data bus 47. Memory block 16 or 24 and memory block 14 or 22 send out another 18 bits of data via sub-buses 52 and 54 for a total of 36 bits to the data bus 47.

Note that there are 9 bits of data obtained from each memory block in this illustration. The 9 bits of data is typically 8 bits of information data and 1 parity bit for error checking. With a set of four blocks of memory devices, there are a total of thirty-six bits. While under the JEDEC standard 36 bits of data are specified, in other configurations where there are no parity bits, each memory block outputs 8 bits of data for a total of thirty-two bits of data. In this case, a data bus width of thirty-two bits is sufficient. The present invention will work with both cases.

In order to use one bank of 2M deep memory devices, instead of two banks of 1M deep memory devices, there are several problems that need to be resolved. First of all, because the computer system recognizes the memory module as a two bank, 1M deep memory device module instead of a one bank, 2M deep memory device module, it will provide the same set of signals as illustrated in FIG. 1. However, with ten address signals, only 1M depth can be addressed. The second 1M depth cannot be accessed without additional circuit logic to provide an additional address signal. Furthermore, with only four memory blocks in an one bank system, instead of eight memory blocks in the two bank system, only two RAS signals are needed rather than the four RAS signals provided by the computer system. Additional logic is also needed to translate the four RAS signals into two RAS signals for the memory blocks.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a memory module apparatus using memory devices not provided for under industry standards that can accept signals from a computer system and translate these signals such that the memory modules can be properly read, written, and refreshed.

A further object of the present invention is to provide a method for allowing memory modules previously requiring two banks of memory devices to use only one bank of memory devices, thereby reducing power consumption and capacitive loading.

Another object of the present invention is to provide a method and apparatus utilizing higher depth memory devices which are decreasing in price.

The present invention can be implemented in a variety of non-standard memory configurations. For discussion and illustration purposes, the implementation of a 2M.times.32/36, one bank non-standard 72 pin memory module of Table 2 supra is discussed. According to the JEDEC standard 2M.times.36 configuration, the memory module is comprised of two banks of 1M deep memory blocks. For this JEDEC standard configuration, the computer system will provide four RAS signals, four Column Address Strobe signals, a Write Enable signal, and ten address signals, A0-A9. The RAS and CAS signals allow memory blocks of the memory banks to be accessed. However, with only ten address signals, only 1M deep memory locations can be addressed. In order to address 2M deep memory devices, an eleventh address signal (A10) is needed. The present invention uses additional logic to derive an eleventh address signal from the RAS signals. In addition, during refresh cycles, the computer system will only provide signals to refresh 1M of the memory locations; but for the logic of the preferred embodiment, the second 1M of memory locations would not be refreshed and the data would be lost. The present invention thus provides the needed logic so that the full 2M memory locations will be refreshed. In effect, the preferred embodiment of the present invention emulates a two bank, 1M depth per bank memory module system with a one bank, 2M deep memory module system.

The present invention thus allows memory modules with non-standard memory configurations to be properly addressed and accessed by a computer system. The present invention can provide for SIPs and other types of memory circuit boards as well.

These and other objects and advantages of the present invention will no doubt become apparent to those skilled in the art after having read the following detailed description of the preferred embodiment which is illustrated in the several figures of the drawing.

IN THE DRAWING

FIG. 1 is a block diagram illustrating a JEDEC standard 2M.times.36 memory module using 1M deep DRAMs.

FIG. 2 is a block diagram illustrating a 2M.times.36 memory module using 2M deep memory devices in accordance with the present invention.

FIG. 3 is an electrical schematic diagram showing the principal components of the logic block illustrated in FIG. 2.

FIG. 4a is a timing diagram illustrating the states of RAS signal and CAS signal used to initiate a CAS-Before-RAS type refresh cycle.

FIG. 4b is a timing diagram illustrating the states of RAS signal, CAS signal, and address signals used to initiate a RAS-Only type refresh cycle.

FIG. 5 is a signal state and timing diagram showing various signals appearing in the electrical schematic diagram of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 2, an electrical schematic depiction of a memory module containing an embodiment of the present invention is illustrated. In this embodiment, there is but one bank 15 of memory blocks, and each memory block, 60 62 64 66, is 2M deep instead of 1M deep.

The set of input signals to the memory module is the same set of input signals as in FIG. 1. As illustrated, the RAS signals are routed to a logic block 80 which is also resident on the module circuit board 11. In addition to going to the respective memory blocks, the CAS signals are routed to logic block 80 as well. In response, the logic block outputs a /RAS L (lower bank) signal 70 to memory blocks 64 and 66, a /RAS H (higher bank) signal 76 to memory blocks 60 and 62, a first address signal, A10L (lower bank) 72, to memory blocks 64 and 66, and a second address signal, A10H (higher bank) 74, to memory blocks 60 and 62. Each CAS signal addresses one memory block instead of two. The /WE signal and address signals A0 to A9 go to each memory block as before.

When properly addressed, the respective memory blocks transfer data to and from the data bus 47 via sub-buses 48, 50, 52, 54, in the same manner as described above.

Referring to FIG. 3, an embodiment of a logic circuit 80 in accordance with the present invention is illustrated. Note that /RAS0 and /RAS1 can be considered as one set of signals and /RAS2 and /RAS3 can be considered as a second set of signals. T