Delay-locked loop - Patent Review 5614855

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Delay-locked loop

United States Patent

5614855

Link to this page

http://www.wikipatents.com/5614855.html

Inventor(s)

Lee; Thomas H. (Cupertino, CA); Donnelly; Kevin S. (San Francisco, CA); Ho; Tsyr-Chyang (San Jose, CA); Johnson; Mark G. (Los Altos, CA)

Abstract

A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90.degree. ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.

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