Data detection methods and apparatus for a direct access storage device

We claim:

1. A method for maximum-likelihood data detection in a direct access storage device including a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said method comprising the steps of:

receiving a plurality of digital samples from the ADC;

applying the received digital samples to a first digital filter for providing class-IV partial response (PR4) samples;

applying the filtered PR4 digital samples to a second digital 1+D filter for providing extended Class IV partial response (EPR4) samples;

applying the filtered PR4 digital samples to a first data detector;

applying the filtered EPR4 digital samples to a second data detector;

identifying a predetermined parameter responsive to the received digital samples; and

selecting at least one of the first and second data detectors responsive to the identified predetermined parameter.

2. A method as recited in claim 1 wherein the step of applying the filtered PR4 digital samples to the first data detector includes the step of applying the filtered PR4 digital samples to a PR4 Viterbi detector.

3. A method as recited in claim 1 wherein the step of applying the filtered EPR4 digital samples to the second data detector includes the step of applying the filtered EPR4 digital samples to an EPR4 Viterbi detector.

4. A method for maximum-likelihood data detection in a direct access storage device including a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said method comprising the steps of:

receiving a plurality of digital samples from the ADC;

applying the received digital samples to a partial response (PR) shaping filter for providing PR digital samples;

applying the received digital samples to a selected second filter;

applying the filtered PR digital samples to a first data detector;

applying the second filtered digital samples to a second data detector;

identifying a predetermined parameter responsive to the received digital samples; and

selecting at least one of the first and second data detectors responsive to the identified predetermined parameter.

5. A method as recited in claim 4 wherein the step of applying the filtered PR digital samples to the first data detector includes the step of applying the filtered PR digital samples to a PR Viterbi detector.

6. A method for maximum-likelihood data detection in a direct access storage device including a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said method comprising the steps of:

receiving a plurality of digital samples from the ADC;

applying the received digital samples to a noise whitening filter for providing noise whitening digital samples;

applying the received digital samples to a selected second filter;

applying the filtered noise whitening digital samples to a first data detector;

applying the second filtered digital samples to a second data detector;

identifying a predetermined parameter responsive to the received digital samples; and

selecting at least one of the first and second data detectors responsive to the identified predetermined parameter.

7. A method as recited in claim 6 wherein the step of applying the filtered noise whitening digital samples to the first data detector includes the step of applying the filtered noise whitening digital samples to a full-state Viterbi detector.

8. A method as recited in claim 6 wherein the step of applying the filtered noise whitening digital samples to the first data detector includes the step of applying the filtered noise whitening digital samples to a reduced state Viterbi detector.

9. A method for maximum-likelihood data detection in a direct access storage device including a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said method comprising the steps of:

receiving a plurality of digital samples from the ADC;

applying the received digital samples to a pre-processing filter for providing pre-processing digital samples;

applying the received digital samples to a selected second filter;

applying the filtered pre-processing digital samples to a first data detector;

applying the second filtered digital samples to a second data detector;

identifying a predetermined parameter responsive to the received digital samples; and

selecting at least one of the first and second data detectors responsive to the identified predetermined parameter.

10. A method as recited in claim 9 wherein the step of applying the filtered pre-processing digital samples to said first data detector includes the step of applying the filtered preprocessing digital samples to an adaptive Viterbi detector.

11. A method for maximum-likelihood data detection in a direct access storage device including a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said method comprising the steps of:

receiving a plurality of digital samples from the ADC;

applying the received digital samples to a selected first filter;

applying the received digital samples to a selected second filter;

applying the first filtered digital samples to a first data detector;

applying the second filtered digital samples to a second data detector; wherein said first data detector and said second data detector include an extended partial-response maximum-likelihood (EPRML) data detector and a partial response maximum-likelihood (PRML) data detector;

identifying a predetermined parameter; the identified predetermined parameter including at least a zone of a disk and a head and radius combination; and

selecting at least one of said extended partial response maximum-likelihood (EPRML) data detector and said partial response maximum-likelihood (PRML) data detector responsive to each identified head and radius combination.

12. A method as recited in claim 11 wherein the step of identifying the predetermined parameter includes the step of identifying a signal resolution.

13. Apparatus for data detection in a direct access storage device including a digital data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said apparatus comprising:

a first filter coupled to the ADC for receiving and filtering a plurality of digital samples from the ADC;

a second filter coupled to the ADC for receiving and filtering a plurality of digital samples from the ADC;

an extended class-IV partial response (EPR4) Viterbi detector coupled to the first filter for receiving the first filtered samples;

a data detector coupled to the second filter for receiving the second filtered samples;

means for identifying a predetermined parameter responsive to the received digital samples; and

means for selecting at least one of the EPR4 Viterbi detector and the data detector responsive to the identified predetermined parameter.

14. Apparatus for data detection in a direct access storage device including a digital data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples, said apparatus comprising:

a first filter coupled to the ADC for receiving and filtering a plurality of digital samples from the ADC;

a second filter coupled to the first filter for receiving and filtering a plurality of digital samples from the first filter;

a partial response class-IV (PR4) Viterbi detector coupled to the first filter for receiving the first filtered samples;

a data detector coupled to the second filter for receiving the second filtered samples;

means for identifying a predetermined parameter responsive to the received digital samples from the ADC; and

means for selecting at least one of the PR4 Viterbi detector and the data detector responsive to the identified predetermined parameter.

15. Apparatus as recited in claim 14 wherein the data detector includes an extended class-IV partial response (EPR4) Viterbi detector.

16. Apparatus as recited in claim 14 wherein the data detector includes a partial response Viterbi detector.

17. Apparatus as recited in claim 14 wherein the data detector includes an adaptive Viterbi detector.

18. Apparatus as recited in claim 14 wherein the data detector includes a full-state Viterbi detector.

19. Apparatus as recited in claim 14 wherein the data detector includes a reduced-state Viterbi detector.

20. Apparatus as recited in claim 14 wherein the data detector includes an extended class-IV partial response (EPR4) Viterbi detector implementation of a modified metric function J* is represented by ##EQU3## where .delta..sub.k ({a'.sub.k })=A(-2x'k({a'k}) (y.sub.k.sup.EPR4 +C)+(x'.sub.k ({a'.sub.k }))2); and where A is a scaling factor and

where the y.sub.k.sup.EPR 4 are extended class IV partial response (EPR4) samples corrupted with additive noise, C is a real constant and x'.sub.k ({a'.sub.k }) are the hypothesized, noise-free channel output samples given by

x'.sub.k ({a'.sub.k })=a'.sub.k +a'.sub.k-1 -a'.sub.k-2 -a'.sub.k-3, a'.sub.i .epsilon.{-1,+1 }.

21. Apparatus as recited in claim 20 wherein branch metrics Z.sub.k and Q.sub.k are represented in terms of received class IV partial response (PR4) samples as

Z.sub.k =y.sub.k+1.sup.PR4 +2y.sub.k.sup.PR4 +Y.sub.k-1.sup.PR4

and

Q.sub.k =-Z.sub.k +(4-.alpha.),

where 0.ltoreq..alpha.<1, C=-1 and y.sub.k.sup.EPR4 y.sub.k.sup.PR4 +y.sub.k-1.sup.PR4.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to data detection methods and apparatus, and more particularly to methods and apparatus for partial-response maximum-likelihood (PRML), extended partial-response maximum-likelihood (EPRML), and Viterbi data detection in a direct access storage device (DASD).

2. Description of the Prior Art

Partial-response signaling with maximum-likelihood sequence detection techniques are known for digital data communication and recording applications. Achievement of high-data density and high-data rates has resulted in the use of a PPML channel for writing and reading digital data on the disks.

Known commercial disk drives which include a PRML channel benefit from the fact that, with proper choice of the data rate, binary partial-response class-4 (PR4) signaling with maximum-likelihood sequence detection (MLSD) or PRML provides nearly optimal performance at the presently used linear recording densities. Typically magnetic recording channels operate with 0.8T/R<p.sub.w50 <1.6T/R where T is the channel encoded bit period, R is the code rate and p.sub.w50 is the width at the 50%-level of the channel's step response. For example, p.sub.w50 =(.beta..sub.user /(.pi.R))T where .beta. user represents normalized user data rate and R is the code rate specific to each scheme, for example, such as, PRML advantageously uses R=8/9.

The performance loss of PRML with digital filter equalization caused by noise enhancement due to the equalizing filter becomes increasingly significant when the channel operates at linear recording densities such as p.sub.w50 >1.6T/R. As a consequence, PMRL may fail to meet product specifications at greater linear recording densities.

To increase area storage density, mainly by means of increasing the linear density, requires that the PRML channel be replaced or complemented with a more powerful scheme in order to meet competitive product specifications. However, development and implementation of an entirely new channel architecture is a complex and costly task whose scope contradicts today's requirement for cost-effective and quick-to-market solutions.

U.S. Pat. No. 4,786,890 discloses a class-IV PRML channel using a run-length limited (RLL) code. The disclosed class-IV partial response channel polynomial equals (1-D.sup.2), where D is a one-bit interval delay operator and D.sup.2 is a delay of two-bit interval delay operator and the channel response output waveform is described by taking the input waveform and subtracting from it the same waveform delayed by a two-bit interval. A (0,k=3/k1=5) PRML modulation code is utilized to encode 8 bit binary data into codewords comprised of 9 bit code sequences, where the maximum number k of consecutive zeroes allowed within a code sequence is 3 and the maximum number k1 of consecutive zeroes in the all-even or all-odd sequences is 5.

U.S. Pat. No. 5,196,849 discloses rate 8/9 block codes having maximum ones and run length constraints for use in a class-IV PRML channel.

Trellis coding techniques are used to provide a coding gain required in noisy or otherwise degraded channels. U.S. Pat. Nos. 4,888,775 and 4,888,779 describe trellis codes for PRML channels which provide significantly improved coding gains for transmission of digital data over PRML channels.

U.S. Pat. No. 4,609,907 discloses a method for bandwidth compression using partial response and run length limited coding. A first 1-D.sup.2 channel is used for detection of data with a 1+D channel for clocking.

A conventional EPRML channel design including extended (EPR4) equalization, timing and gain control represents a large jump in complexity as compared to a PRML channel. By conventional implementation methods, PRML and EPRML share very few common functional blocks. The conventional approach is considered unacceptable from a size, power and speed viewpoint. For EPRML, the calculations required for the 5-level gain and timing loops are more complex and slower. Also, the 5-level timing gradient calculation is considered to be less robust than the 3-level calculation for PRML. EPRML requires an 8-state non-interleaved Viterbi detector which by conventional implementation methods is not acceptable from a size, power and speed viewpoint. It is desirable to provide an EPRML implementation that allows for an acceptable size, cost and power to be achieved.

With a goal of increased linear density, it is desirable to implement an EPRML/PRML combination system to provide optimal performance over the entire disk radius.

SUMMARY OF THE INVENTION

It is a principal object of the present invention to provide data detection methods and apparatus for detecting data that overcomes many of the disadvantages of prior art arrangements.

In brief, the objects and advantages of the present invention are achieved by a method and apparatus for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention, together with the above and other objects and advantages, can best be understood from the following detailed description of the embodiment of the invention illustrated in the drawings, wherein:

FIGS. 1 and 2 are graphs illustrating pulse responses for partial-response maximum-likelihood (PRML) channels based on partial response class-4 (PR4) and extended partial response class-4 (EPR4), respectively;

FIGS. 3A and 3B together provide a block diagram representation of a combination extended partial-response maximum-likelihood (EPRML) and PRML channel according to the invention;

FIG. 4 is a block diagram representation of an alternative flexible channel architecture of the invention;

FIG. 4A is a flow chart illustrating sequential data detection steps in accordance with a data detection method of the invention;

FIGS. 5A and 5B together form a schematic diagram illustrating a survivor path memory for an EPR4 Viterbi detector arrangement;

FIG. 6 is an eight state EPR4 trellis transition diagram using modified metric computation with A=1/4, Y.sub.K =Y.sub.K.sup.EPR4 and C equal to a real constant;

FIG. 7 is a transformed eight state EPR4 trellis transition diagram using modified metric computation with A=1/4 and C=-1;

FIG. 8 is a schematic diagram illustrating add, compare and select (ACS) calculation circuitry for an EPR4 Viterbi detector derived directly from the trellis of FIG. 7 according to the invention;

FIG. 9 is a second alternative, transformed and expanded EPR4 trellis transition diagram enabling high-speed implementation; and

FIG. 10 illustrates the EPR4 trellis transition diagram of FIG. 7 transformed as a PR4 detector.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIGS. 1 and 2 of the drawing, there are shown graphs illustrating pulse responses for partial-response maximum-likelihood (PRML) channels based on partial response class-4 (PR4) and extended partial response class-4 (EPR4), respectively, assuming plus and minus one binary inputs. The system polynomial for PR4 is (1-D.sup.2). A natural extension of the PR4 response is the extended partial-response class-4 (EPR4) response which has a system polynomial of (1-D.sup.2) (1+D)=(1+D-D.sup.2 -D.sup.3). FIGS. 1 and 2 illustrate the equalized readback waveforms for PR4 and EPR4 due to a 1-length write current pulse. Equalized EPR4 samples occur at five levels (+4, +2, 0, -2, -4) as compared to three levels (+2, 0, -2) for PR4. Maximum-likelihood detection can be applied to either of these partial-response systems.

In accordance with the invention, the correct choice for using EPR4 or PR4 depends on the magnetic design point. Only the detection method is changed for improved error rate performance. As shown in Table I, either EPR4 or PR4 is the optimal solution for a range of magnetic design points. This is illustrated by Table I where T is the channel encoded bit period, R is the Run-Length-Limited code rate, and p.sub.w50 is the width at the 50%-level of the channel's step response.

TABLE I ______________________________________ Channel Selection versus Signal Resolution Best Solution over Channel Type Code Rate R this Range ______________________________________ Peak Detect (1,7) 2/3 P.sub.w50 .ltoreq. 0.8T/R PR4 (PRML) 8/9 0.8T/R < p.sub.w50 .ltoreq. 1.6T/R EPR4 (EPRML) 8/9 1.6T/R < p.sub.w50 ______________________________________

The EPRML/PRML combination system creates a new approach to maximizing both capacity and performance. By utilizing a PRML detection system towards the outer diameter (OD) of the disk and an EPRML system towards the inner diameter (ID) of the disk and maintaining the channel data rate at the maximum rate over the entire radius or slight zoned band recording (ZBR), it is possible to gain a significant capacity increase, for example, such as, approximately 15% while improving the overall data-rate performance of the file. This approach works because the detector type is matched to the channel magnetic design point, and thus the error-rate degrades less as the linear density is increased.

Preliminary experimental data has shown EPRML data detection to be less sensitive to ADC saturation, MR asymmetry, and uncompensated nonlinear bit shift as compared to PRML data detection. A significant performance/capacity increase is possible with the EPRML/PRML combination over what known ZBR systems have provided. ZBR provides increased capacity given the assumption that the channel error-rate always degrades as the linear density is increased. The capacity gain from ZBR always has the penalty of poorer sustained data-rate performance towards the ID of the disk.

Referring now to FIGS. 3A and 3B, there is shown a block diagram of a combination of a partial-response maximum-likelihood (PRML) and extended partial-response maximum-likelihood (EPRML) data detection for a partial-response recording channel 10 in a direct access storage device in accordance with the invention. Customer data to be written, such as in the form of a binary symbol string, is applied to an encoder 12. Encoder 12 produces a modulated coded output having pre-defined run length constraints or codewords which serve as an input to a class-IV partial-response (PR) channel described by a (1-D.sup.2) operation. As shown, the present invention provides a novel architecture and implementation of EPR4 Viterbi detection (EPRML) in a PRML channel for improved data detection in high-density digital magnetic recording devices.

Referring also to FIG. 3B, the novel architecture of the invention allows a combination system of PRML and EPRML to share all functional blocks as shown in FIG. 3A with either a PR4 Viterbi detector 14 or an EPR4 Viterbi detector 16. This architecture allows for the addition of EPRML capability to a PRML channel by the inclusion of only a simple (1+D) digital adder or filter circuit 18, the EPR4 Viterbi detector 16 and a one-bit multiplexer 20 for selecting the output of the PR4 Viterbi detector 14 or the EPR4 Viterbi detector 16.

A serializer 24 and a precoder 26 follows the encoder 12. Precoder 26 is described by a 1/(1.sym.D) operation where D is a unit delay operator and where .sym. means modulo 2 addition. A PRML precomp 28 coupled to the precoder 26 provides a modulated binary pulse signal applied to a write trigger circuit 30 that provides the modulated write current for writing to the disk surface. Write trigger circuit 30 is described by 1/(1.sym.D) operation. Precoder 26 in combination with write trigger circuit 30 together form a non-standard precoder 1/(1.sym.D.sup.2) for EPRML which has been proven to reduce the error event lengths and the number of Type I symbol errors as compared to the standard EPRML precoder.

An analog read signal is obtained at head and disk block 32. The read signal is applied via an arm electronics block 34 to a variable gain amplifier (VGA) 36. The amplified read signal is applied to a lowpass filter 38 that should preferably boost the higher frequencies to avoid saturation of an analog to digital converter (ADC) 40. The lowpass filtered read signal is converted to digital form by the ADC 40 that provides, for example, 64 possible 6-bit sampled values. Raw samples and noise are provided at a line labelled B at the output of the ADC 40.

The samples of the ADC 40 are applied to a timing recovery and gain control 42 and are applied to a digital filter 44, such as a 10-tap finite impulse response (FIR) digital filter. The timing recovery and gain control 42 provides a gain control signal to the VGA 36 and provides a timing control signal to the ADC 40. The EPRML/PRML combination system 10 uses common 3-level gain and timing loops for the PR4 equalized samples and noise provided at a line labelled A at the out-put of the digital filter 44. Gain and timing loops based upon the PR4 equalized samples are simpler and are considered more robust than 5-level loops for EPR4 samples.

PR4 equalized samples are transformed by the digital (1+D) adder or filter circuit 18 to obtain EPR4 5-level samples applied to the EPR4 Viterbi detector 16. The filtered signal from the digital filter 44 is applied to the PR4 Viterbi detector 14 and also is applied to the EPR4 Viterbi detector 16 via adder circuit 18. PR4 and EPR4 Viterbi detectors 14 and 16 are coupled to a decoder 46 to complete the maximum-likelihood (ML) detection process for data read back.

A postcoder 50 coupled to