Preprogramming testing in a field programmable gate array

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BACKGROUND OF THE INVENTION

The invention relates generally to the field of testing of integrated circuit devices and, more particularly, to the testing of user-programmable or field programmable gate arrays (FLAGS).

In a field programmable gate array (FAA), the connections between the transistors, logic blocks, and input and output circuits are made by the user of this type of integrated circuit. The transistors, logic blocks, and input and output circuits are connected to line segments which intersect or abut each other at various points. At most of these points programmable elements known as antifuses are located to make a connection between the line segments if desired.

In an unprogrammed state, each antifuse remains in a high impedance, or "open circuit" state. When programmed, the antifuse is in a low impedance, or "closed circuit" state. The antifuses in the FPGA are selectively programmed by the user to make desired interconnections between the transistors, logic blocks and input and output circuits of the FPGA for a particular application. In this manner an FPGA is configured for a particular application.

It is thus highly desirable for a FPGA to be tested prior to its programming to check the functionality of the various elements of the FPGA, including its line segments and antifuses. Heretofore, if provisions had been made for the testing of a FPGA, special test transistors and circuits were added to the integrated circuit. These additions increased the complexity and space requirements for what is typically an already complex and crowded integrated circuit.

A typical FPGA integrated circuit has specified programming pins by which large voltages are introduced into the circuit for the programming of antifuses. In the FPGA of the present invention, the input/output buffer circuits are provided with a serial scan path for test signals according to the IEEE 1149.1 test standards. During the programming of the antifuses, signals in the 1149.1 serial scan path become control signals for the programming circuits which address wiring segments to specify the particular antifuses to be programmed while the programming voltages are supplied through the specified pins.

In accordance to the present invention, the programming circuits controlled by signals in the serial scan path and the specified programming pins are used to provide paths for testing the FPGA prior to the programming of the antifuses. In this manner the present invention is able to achieve the goals of testing the elements and functions of an FPGA with a minimal amount of additional transistors and circuits.

SUMMARY OF THE INVENTION

Thus the present invention provides for an integrated circuit which has a plurality of terminals for providing electrical paths to and from said integrated circuit. The integrated circuit also has an array of functional units and a plurality of line segments connected to the functional units. Programmable elements are located between two line segments. These elements are programmable by a programming voltage across the two line segments. The integrated circuit has address circuits connected to each of the line segments for connecting a selected line segment responsive to address signals to a voltage supply or to one of the terminals. The units may be tested by selecting line segments connected to a unit and monitoring the unit through the line segments. The address circuits may also program the elements by selecting line segments having the elements between the selected line segments. Thus the address circuits may be used for programming the programmable elements and for testing units in the array.

The array of functional units include continuous series transistors and circuit blocks which may be configured for memory and logic functions.

Testing also includes testing of the functionality of each of these functional units, and the electrical continuity of various line segments.

The integrated circuit also has input/output buffer circuits which are programmable to set various operating parameters of the input/output buffer circuit. The present invention incorporates a serial scan path which is used nominally for testing an integrated circuit for carrying control signals to temporarily set the various operating parameters of the input/output buffer circuit for testing prior to programming.

The integrated circuit has clock circuits which are programmable to set or define the desired clock network path for the integrated circuit. In the serial scan path, the clock circuits are temporarily set by signals on the serial scan path so that the various network clock paths may be tested prior to programming. In this clock network testing the address circuits used for programming are also used.

The present invention also provides for process characterization tests of the integrated circuit without the requirement of high-speed test equipment. A small portion of the programmable elements is programmed to form a series of inverters. A ring oscillator loop is formed with the serial scan path through the input/output buffer circuits and the programmed series of inverters. A counter operating at much lower speeds than if the counter were testing the programmed inverter series by itself is sufficient for the process characterization.

Thus the present invention provides for these and other features which will be apparent below.

BRIEF DESCRIPTION OF THE DRAWINGS

A detailed understanding of the present invention may be attained by a perusal of the following Description of the Specific Embodiments with reference to the drawings below:

FIG. 1 is a general top view of a FPGA integrated circuit implementing the present invention.

FIG. 2 is a general top view of the core array of the integrated circuit of FIG. 1.

FIG. 3 is a detailed view of a CST row in the core array in FIG. 2.

FIG. 4 is a logic circuit schematic of a latch/logic block (LLB) in the core array in FIG. 2.

FIG. 5 shows how the LLBs are arranged with respect to each other in the core array.

FIGS. 6A to 6C show representationally different combinations of programming voltages in a grid of wiring segments.

FIG. 7 shows representationally X, Y addressing of wiring segments in the core array.

FIG. 8 illustrates the general arrangement of the programming circuits for each wiring segment in the core array of the FPGA.

FIG. 9 is a table of wiring segments of a four-tile section in a CST row, its programming grid, .+-.Y control line for a given .+-.Y address.

FIG. 10 details the isolation transistor circuitry for the transistors in the CST rows in the core array.

FIG. 11 is a logic circuit schematic of an input/output buffer circuit if the I/O section in FIG. 1.

FIG. 12 illustrates the general connection between the input/output buffer circuits of the I/O section and the core array of FIG. 1.

FIG. 13 is a logic circuit schematic of a programming unit in the input/output buffer circuit of FIG. 11.

FIG. 14A is a general view of the clock network of the FPGA integrated circuit; FIG. 14B illustrates the general serial scan path connection between the input/output buffer circuits of FIG. 11 and the various clock circuits of FIG. 14A.

FIG. 15 is a logic circuit schematic of the input clock enable circuit of FIG. 14A.

FIG. 16A illustrates the connection between a + programming grid and the V.sub.pp programming pin through a programming transistor; FIG. 16B illustrates the circuit which allows a + programming grid to be pulled low during testing; FIG. 16C illustrates the circuit which allows a -programming grid to be pulled high during testing.

FIG. 17 illustrates a representative group of PMOS transistors in a CST

FIGS. 18A-18D show the sequential steps for testing the PMOS transistors in FIG. 17.

FIG. 19 is a representative signal path through the core array in the testing of the clock network of the FPGA.

FIG. 20 is a representative signal path around the periphery in the testing of the clock network of the FPGA.

FIG. 21 illustrates the logic gate signal path used for characterizing the process used to manufacture the FPGA.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

For an understanding of the various test operations of the FPGA according to the present invention, an understanding of the various parts of the FPGA is very helpful. Thus an explanation of the organization of the FPGA and its parts follows. It should be understood, though, that many of the test operations described herein have applications beyond FPGAS.

Organization of the FPGA

A top view of an field programmable gate array (FPGA) integrated circuit according to the present invention is illustrated in FIG. 1. The drawing shows the general organizational layout of the FPGA. On a semiconductor substrate 10 the FPGA has a central core array section 11, which contains continuous-series transistors (CST), latch/logic blocks (LLB) and antifuses which are programmed to configure the transistors and blocks for the user's application.

Surrounding the core array section 11 is a programming section 12, here shown as four separate areas, which contain the circuits for programming the antifuses in the core array 11. Included in this section 12 is circuitry for controlling the special programming voltages, V.sub.pp and V.sub.ss, in the array 11 for programming the antifuses. On the outside of this programming section 12 is a control section 13, again shown as four separate areas, which contains the control circuitry used for addressing the wiring segments in programming the selected antifuses and for testing.

Finally, an input/output section 14 is located on the periphery of the substrate 10. The section 14 contains the input and output circuitry for receiving signals from the outside world into the FPGA interior and for driving signals from the interior of the FPGA to the outside world.

An antifuse is a programmable element which is placed between two conducting layers of the FPGA integrated circuit. The type of antifuse contemplated in the present invention has a high resistance of several giga-ohms in the unprogrammed state and a low resistance, say, 100-150 ohms, in the programmed state. The unprogrammed antifuses have a very low parasitic capacitance, below 2 fF.

A specific example of an antifuse useful in the present invention is a structure made of amorphous silicon which fits into a normal contact between a metal 1 layer and a polysilicon layer. This structure is disclosed in U.S. Pat. No. 4,796,074, issued to B. Roesner on Jun. 3, 1989. Another useful antifuse structure is formed between any two metal interconnection layers of an integrated circuit. This structure is disclosed in U.S. patent application Ser. No. 07/642,617, entitled, "AN IMPROVED ANTIFUSE CIRCUIT STRUCTURE FOR USE IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD 0F MANUFACTURE THEREOF," filed by M. R. Holzworth et al. on Jan. 17, 1991, and assigned to the present assignee.

The Core Array

FIG. 2 shows a representational view of the FPGA core array 11. The array 11 has horizontal CST rows 15 and LLB rows 16 which are interleaved with horizontal wiring channels 17 between the CST and LLB rows 15 and 16. The CST rows 15 are used to implement different logic cells, from standard drive to high drive inverters, from multiple input NAND and NOR gates, to more complex AOI (AND-or-invert) cells. These rows 15 can also implement multiplexer-based logic cells. However, the adjacent LLB rows 16, each of which contains a row of preconfigured logic blocks as indicated by the vertical lines in the rows 16, are more efficient for implementing such cells.

In the rows 15 and 16 and channel 17 are horizontal and vertical wiring segments. At the intersection of many of the segments are antifuses, which, when programmed, electrically connect intersecting segments together. These antifuses are located mostly at the intersection of the wiring segments in the CST rows 15 and the channels 17. The CST rows 15 can be flexibly configured into the desired logic cells and the channels 17 can make the required intercell connections.

Thus cell functions and circuit connections are defined by programming the appropriate antifuse element which then forms a low resistance connection between intersecting horizontal and vertical wiring segments. The CST rows 15 and LLB rows 16 are logically and interconnectedly configurable and can implement nearly any combinatorial logic or storage logic cell possible in present MPGAs. This is discussed in more detail below.

The Wiring Channels and Vertical Routing

For purposes of explanation, some terms are now defined. The term "column" is used to indicate a vertical slice in the core array 11 having a width occupied by an opposing pair of transistors, i.e. a PMOS and a NMOS transistor, in a CST row 15. The term "tile" refers to that portion of a column in a CST row 15.

Broadly speaking, the wiring channels 17 are used to make the horizontal connections between the configured cells in the CST rows 15 and the LLB rows 16. The channels 17, which are interleaved with the CST rows 15 and LLB rows 16, contain horizontal segmented wiring tracks of different segment lengths. These horizontal wiring track segments vary from a minimum length of eight columns to the entire width of the array 11. The different segment lengths serve different purposes and increase the utility of the channels 17. For example, the horizontal track segments which minimally span eight columns primarily are used to make feedback connections to the latch/logic blocks in the LLB rows 16 to configure the blocks into latches, flip-flops, and RAM cells, as explained below.

Included within each channel 17 are also clock lines to be used as global clock signals, global enable or reset signals, or any other high fanout signal in the user's application. The clocks are driven from driver circuits along the sides of each channel 17 of the array 11, as discussed more fully below.

Intersecting the horizontal segments in the channels 17 are vertical wiring segments to accommodate vertical connections between circuit nodes in the CST rows 15 and LLB rows 16. Antifuse elements, indicated by a square at the intersection of two lines in the drawings of this patent application, are located at the intersections of the horizontal and vertical wire segments in the channel 17. Each channel 17 is a grid of horizontal and vertical wiring segments which have an antifuse at nearly every intersection.

Three types of vertical wiring are used in the core array 11. The first type is formed by a segment connected to a PMOS or NMOS transistor gate or a latch segment. Both are described in more detail below with respect to FIG. 3. This type of vertical segment forms a route from a horizontal wire segment in an adjacent channel 17 to the cell in the CST row 16 or LLB row 15.

The second type of vertical wiring is a vertical chevron. As illustrated in FIG. 2, each of these vertical wiring segments 31 span four CST rows 15 and intervening LLB rows 16. The chevrons 31 start and end on the CST rows 15. The term "chevron" is used because these wiring segments have a diagonal wire portion (or half chevron) in the rows 15 in which the vertical chevrons 31 start and end. The diagonal wire portions horizontally span five tiles. The central vertical portion of each vertical chevron passes through three wiring channels 17 and two rows 15. As symbolically indicated in FIG. 2, each vertical chevron 31 may be connected through antifuses along either diagonal end portion to vertical segments in the rows 15 or along the center portion of the segment 31 which passes through the channels 17 and rows 15 to horizontal segments in the channels 17 and rows 15. In passing, it should be noted that the horizontal segments in the rows 15 are actually diagonal.

FIG. 3 described below with respect to the CST row 15 also shows how the vertical chevrons 31 are mapped on to the core array 11. The pattern is regular and repeats horizontally every four tiles and vertically every row 15. A full vertical chevron exists for every two tiles, with a diagonal segment every tile. Two vertical chevrons feed through every two CST tiles and end on different rows.

The third type of vertical wiring segment is a long line. Long lines extend long distances from the top to the bottom of the core array to make long vertical connections primarily. Generally these wiring segments extend either the entire distance, 1/2 the distance, or 1/3 (2/3 ) the distance of the core array height. Long lines are horizontally spaced so that a long line passes through a CST row 15 every two tiles. These line segments are lightly loaded since they are intended to be used to route signals over long distances. The primary means for driving a long line is with a standard or high drive inverter.

The CST Row

The CST rows 15 offer the configurability of a MPGA with nearly matching performance. Small logic gates, such as NAND, NOR, AND, OR and inverters, are efficiently configured in the CST rows 15. Each of the transistors in the rows 15 have wiring segments connected to its source/drains and gate electrode. Other wiring segments travel to different parts of the core array. All of these wiring segments intersect with each other and antifuses are placed between these intersecting segments. By programming selected antifuses, the transistors of the CST rows 15 may be configured into the desired block.

FIG. 3 illustrates the arrangement of a portion of a CST row 15 and related wiring segments. Each row 15 contains two strings of continuous-series transistors with one string formed from NMOS transistors and the other with PMOS transistors. In the drawings a PMOS transistor is denoted by a circle on the gate of the MOS transistor symbol. Furthermore, in FIG. 3 the merging of the source/drain of one CST transistor into the source/drain of another transistor is indicated by the double line connecting the source/drains of the transistors.

Four NMOS transistors 20A-20D and four PMOS transistors 21A-21D are shown. It should be understood that these transistors 20A-20D and 21A-21B are connected by their source/drains to other transistors in the row 15 which are not shown in the drawing.

Each of the gates of the NMOS transistors 20A-20D are connected to N gate wiring segments 22A-22D. Correspondingly, P gate wiring segments 23A-23D are respectively connected to each of the gates of the P transistors 21A-21D. These wiring segments 22A-22D and 23A-23D are run perpendicularly, or vertically, with respect to the alignment of the CST transistors 20A-20D and 21A-21D.

Wiring segments 24A-24D and 25A-25D are also connected to the respective source/drains (SD) of the NMOS and PMOS transistors 20A-20D and 21A-21D. For illustrative and labelling purposes, in FIG. 3 the source/drain to the fight of each MOS transistor 20A-20D and 21A-21D is associated with the transistor. Thus each NMOS transistor 20A-20D has N SD wiring segments 24A-24D respectively connected to the source/drain of each NMOS transistor and each PMOS transistor 21A-21D has P SD wiring segments 25A-25D respectively connected to the source/drain of each PMOS transistor. These SD wiring segments 24A-24D and 25A-25D also run vertically. All the P gate and P SD segments 22A-22D and 24A-24D can be connected to a V.sub.cc power supply wire 28 running along the length of each CST row 15. Likewise, all N gate and N SD segments 23A-23D and 25A-25D can be connected to a V.sub.ss power supply wire 29 running along the length of each CST row 15. As in some CMOS integrated circuits, V.sub.cc is at +3.5 volts and V.sub.ss is at ground, or O volts, but other voltages could be used.

All P gate segments 22A-22D and latch segments 33-36, which are connected to input and output terminals of the LLBs 40, discussed below, extend up into the channel 17 above and have connections to all wiring segments in the channel.

Running diagonally are an array of wiring segments 30 and 31. One half of these segments are vertical chevrons 31, mentioned previously, used for intercell routing. The other half are local chevrons 30 for intracell routing. The local chevrons 30 horizontally span nine tiles of a CST row 15. There is one local chevron 30 horizontally for every two tiles. The vertical chevrons 31 horizontally span five tiles and there is one diagonal portion of a vertical chevron 31 for each tile. The local and vertical chevrons 30 and 31 intersect the P gate wiring segments 22A-22D, P SD segments 24A-24D, vertical sections of vertical chev