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Document Number
US Patent 5625323
Issued Date
April 29, 1997
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Abstract
An FET gate bias circuit having a Schottky barrier gate incorporated therein is provided which can prevent gate voltage variations and thus provide a high-performance, high-reliability GaAs FET amplifier. The FET gate bias circuit includes a PNP transistor having a collector connected to a negative power supply, an NPN transistor having a collector thereof grounded and an emitter connected to the emitter of the PNP transistor, a Schottky barrier gate FET having a source grounded and a gate connected to the node between the emitters of the PNP transistor and NPN transistor, and a base voltage applying circuit for applying predetermined base voltages to the respective bases of the PNP transistor and NPN transistor.
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FET gate bias circuit - US Patent 5625323 Drawing
Drawing from US Patent 5625323
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Number of Claims:
5
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Owner
Fujitsu Limited (Kanagawa,JP)
Published
April 29, 1997
Application Number
08/544,606
Filed
October 18, 1995
US Classification
330/277   330/296
Int'l Classification
H03F   3/189   (20060101)   H03F   1/30   (20060101)   H03F   3/193   (20060101)  
Priority Data
Feb 15, 1995 [JP] 7-026634
USPTO Field of Search
330/277   330/296  
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