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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address transition detection circuit
for a memory device, and more particularly to an address transition
detection circuit in which an address transition detect signal having a
pulse width required for operating the memory, device is outputted
regardless of a pulse width of an address signal inputted to the memory,
device to thereby prevent any malfunction of the memory device.
2. Description of the Prior Art
A conventional address transition detection circuit for a memory device,
referring to FIG. 1, includes a NOR gate 1 for NORing an input chip select
signal CSb and an input address signal AD: a latch 2 for latching the
signal provided from the NOR gate 1 and outputting inverted latch signals
LS1 and LS2; signal delays 3 and 4 for delaying the latch signals LS1 and
LS2 provided from the latch 2 for a predetermined time and outputting
delayed signals DLS1 and DLS2; and a signal outputting unit 5 for
outputting an address transition detect signal ATDS in response to the
latch signal LS1 and LS2 provided from the latch 2 and the delay signals
DLS1 and DLS2 respectively provided from the signal delays 3 and 4.
The latch 2 includes a NAND gate 22 for NANDing both the signal provided
from the NOR gate 1 and inverted through an inverter 21 and an input
signal LS2 to output the latch signal LS1, and also a NAND gate 23 for
NANDing the signals respectively provided from both the NOR gate 1 and the
signal LS1 from the NAND gate 22 to output the latch signal LS2.
The signal delay 3 includes inverters 31 and 32 for sequentially inverting
the latch signal LS1 provided from the latch 2, and the signal delay 4
includes inverters 41 and 42 for sequentially inverting the latch signal
LS2 provided from the latch 2.
The signal outputting unit 5 includes a PMOS transistor MP1 having a source
to which a power supply voltage VCC is applied and a gate to which the
delayed signal line DLS1 from the signal delay 3 is applied; a PMOS
transistor MP2 having a source to which the drain of the PMOS transistor
MP1 is connected and a gate to which the latch signal LS1 from the latch 2
is applied and a drain connected to an address transition detect signal
ATDS output line; an NMOS transistor MN1 having its drain connected in
common with the drain of PMOS transistor MP2, and also having its gate
connected in common with the gate of PMOS transistor MP2; an NMOS
transistor MN2 having a drain to which a source of the NMOS transistor MN1
is connected, a gate to which the delay signal DLS2 from the signal delay
4 is applied, and a source connected to ground; a PMOS transistor MP3
having a source to which the power supply voltage VCC is applied, a gate
to which the gate of the NMOS transistor MN2 is connected; a PMOS
transistor MP4 having a source to which a drain of the PMOS transistor MP3
is connected, a gate to which the latch signal LS2 from the latch 2 is
applied and a drain connected to the address transition detect signal ATDS
output line; an NMOS transistor MN3 having its drain connected in common
with the drain of PMOS transistor MP4 and also having its gate connected
in common with the gate of PMOS transistor MP4; and an NMOS transistor NM4
having a drain to which a source of the NMOS transistor MN3 is connected,
a gate to which the gate of the PMOS transistor MP1 is connected, and a
source connected to ground.
The operation of the conventional address transition detection circuit for
a memory device as constructed above will now be described.
At an initial stage, when a low level chip select signal CSb and a low
level address signal AD are inputted, the NOR gate 1 outputs a high level
signal after NORing the inputted signals CSb and AD.
Then, the NAND gate 22 of the latch 2 receives at one input terminal
thereof the signal provided from the NOR gate 1 and inverted as a low
level signal through the inverter 21, and outputs a high level latch
signal LS1 regardless of a state of the signal provided from the NAND gate
23 and applied to the other input terminal thereof.
The NAND gate 23 receives at one input terminal thereof the high level
signal provided from the NOR gate 1 and at the other input terminal
thereof the high level latch signal LS1 provided from the NAND gate 22,
NANDing the high level signal and the high level latch signal LS1, to
output a low level latch signal LS2.
The high level latch signal LS1 provided from the NAND gate 22 is delayed
for a predetermined time by sequentially passing through the inverters 31
and 32 of the delay 3 so as to be outputted as a high level delay signal
DLS1, while the low level latch signal LS2 provided from the NAND gate 23
is delayed for a predetermined time by sequentially passing through the
inverters 41 and 42 of the delay 4 so as to be outputted as a low level
delay signal DLS2.
Then, the PMOS transistor MP1 and the NMOS transistor MN4 of the signal
output unit 5 receive the high level signal DLS1 provided sequentially
through the inverters 31 and 32 so as to be turned off and turned on,
respectively, while the PMOS transistor MP2 and the NMOS transistor MN1
commonly receive at each gate thereof the high level latch signal LS1
provided from the NAND gate 22 so as to be turned off and turned on,
respectively.
In the meantime, the NMOS transistor MN2 and the PMOS transistor MP3
receive at each gate thereof the low level signal DLS2 provided
sequentially through the inverters 41 and 42 so as to be turned off and
turned on, respectively, while the PMOS transistor MP4 and the NMOS
transistor MN3 commonly receive at each gate thereof the low level latch
signal LS2 provided from the NAND gate 23 so as to be turned on and turned
off, respectively.
Accordingly, a high level address transition detect signal ATDS is
outputted through the address transition detect signal ATDS output line.
Thereafter, under the condition that a low level address signal AD is
transitted to a high level address signal AD, when a pulse width of the
address signal AD transitted to the high level signal is longer than a
pulse width of an address transition detect signal required for operating
the memory device, the high level address signal AD having the pulse width
is inputted, with which when a low level chip select signal CSb is
inputted, the NOR gate 1 outputs a low level signal by NORing the inputted
signals CSb and AD.
Then, the NAND gate 23 receives at one input terminal thereof the low level
signal provided from the NOR gate 1, NANDing it with the high level signal
LS1 applied to the other input terminal thereof, to output a high level
signal LS2, while the NAND gate 22 receives at one input terminal thereof
the high level signal inverted through the inverter 21 and at the other
input terminal thereof the high level signal LS2 provided from the NAND
gate 23, NANDing the high level signals, to output a low level signal LS1.
Accordingly the PMOS transistor MP2 and the NMOS transistor MN1 commonly
receive at each gate thereof the low level signal LS1 provided from the
NAND gate 22 so as to be turned on and turned off, respectively, while the
PMOS transistor MP4 and the NMOS transistor MN3 commonly receive at each
gate thereof the high level signal LS2 provided from the NAND gate 23 so
as to be turned off and turned on, respectively.
And, the PMOS transistors MP1 and MP3 and the NMOS transistors MN2 and MN4
are maintained at their immediately preceding switched conditions until
the signals LS1 and LS2 respectively provided from the NAND gates 22 and
23 are outputted after passing the delays 3 and 4, so that the high level
signal ATDS being provided through the address transition detect signal
ATDS output line is transitted to be outputted as a low level signal.
Thereafter, when a low level signal DLS1 is outputted sequentially through
the inverters 31 and 32 and a high level signal DLS2 is outputted through
the inverters 41 and 42, the PMOS transistor MP1 and the NMOS transistor
MN4 receive at each gate thereof the output low level signal DLS1 so as to
be turned on and turned off, respectively, while the NMOS transistor MN2
and the PMOS transistor MP3 receive at each gate thereof the outputted
high level signal DLS2 so as to be turned on and turned off, respectively.
Since the PMOS transistors MP2 and MP4 and the NMOS transistors MN1 and MN3
are maintained at their immediately preceding switched conditions, the low
level address transition detect signal ATDS being provided through the
address transition detect signal ATDS output line is transitted to a high
level signal to be outputted.
Thereafter, when the high level address signal AD is transitted to the low
level address signal AD to be inputted and the low level chip select
signal CSb is inputted, the NOR gate 1 outputs a high level signal after
NORing the inputted signals AD and CSb.
Then, the NAND gate 23 receives at one input terminal thereof the high
level signal provided from the NOR gate 1, NANDing it with the low level
signal LS1 applied to the other input terminal thereof, to output a high
level signal LS2, while the NAND gate 22 receives at one input terminal
thereof the low level signal inverted through the invertor 21 and at the
other input terminal thereof the high level signal LS2 provided from the
NAND gate 23, NANDing the low level signal and the high level signal LS2,
to output a high level signal LS1.
Accordingly, the NAND gate 23 receives at the other input terminal thereof
the high level signal LS1 from the NAND gate 22, NANDing it with the high
level signal applied to one input terminal thereof, to output a low level
signal LS2.
Therefore, the PMOS transistor MP2 and the NMOS transistor MN1 commonly
receive at each gate thereof the high level signal LS1 provided from the
NAND gate 22 so as to be turned on and turned off, respectively, while the
PMOS transistor MP4 and the NMOS transistor MN3 commonly receive at each
gate thereof the low level signal LS2 provided from the NAND gate 23 so as
to be turned on and turned off, respectively.
And, since the PMOS transistors MP1 and MP3 and the NMOS transistors MN2
and MN4 are maintained at their immediately preceding switched conditions
until the signals LS1 and LS2 respectively provided from the NAND gates 22
and 23 are outputted, respectively, the high level address transition
detect signal ATDS being provided through the address transition detect
signal ATDS output fine is transitted to be outputted as a low level
address transition detect signal ATDS.
Thereafter, when the high level signal LS1 provided from the NAND gate 22
is delayed for a predetermined time after sequentially passing through the
inverters 31 and 32 to be outputted as a high level signal DLS1 and a low
level signal LS2 provided from the NAND gate 23 is delayed for a
predetermined time after sequentially passing through the inverters 41 and
42 to be outputted as a low level signal DLS2, the PMOS transistor MP1 and
the NMOS transistor MN4 receive at each gate thereof the high level signal
DLS1 provided from the inverter 32 so as to be turned on and turned off,
respectively, while the NMOS transistor MN2 and the PMOS transistor MP3
receive at each gate thereof the low level signal DLS2 provided from the
inverter 42 so as to be turned off and turned on, respectively.
Since the PMOS transistors MP2 and MP1 and the NMOS transistors MN1 and MN3
are maintained at their immediately preceding switched conditions, the low
level address transition detect signal ATDS provided through the address
transition detect signal ATDS output line is transitted to a high level
address transition detect signal to be outputted.
Consequently, when the address signal AD is transitted from a low level
signal to a high level signal, the pulse width of the address transition
detect signal ATDS is determined according to the delay time of the signal
delay 3, while when the address signal AD is transitted from a low level
to a high level, the pulse width of the address transition detect signal
ATDS is determined according to the delay time of the signal delay 4.
In the meantime, when the address signal AD having a pulse width shorter
than that of the high level address transition detect signal ATDS required
for operating the memory device is inputted and the low level chip select
signal CSb is also inputted, the address transition detection circuit is
operated in the same manner as described above, so that a low level
address transition detect signal ATDS is outputted through the address
transition detect signal ATDS output line which has a pulse width shorter
than that of the address transition detect signal required for operating
the memory device.
However, in the conventional address transition detection circuit for the
memory device, when an address signal is inputted having a pulse width
shorter than that according to a delay time of a signal delay, that is, a
pulse width shorter than that of the address transition detect signal
required for operating the memory device, an address transition detect
signal having the same pulse width as that of the inputted address signal
is outputted to the memory device, causing a problem that an operation of
the memory device is rendered unstable and unreliable.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an address
transition detection circuit for a memory device in which an address
transition detect signal having a pulse width required for operating the
memory device is outputted regardless of a pulse width of an address
signal provided to the memory device to thereby prevent a malfunction of
the memory device.
In order to obtain the above object, there is provided an address
transition detection circuit including: a NOR gate for NORing an inputted
address signal and an inputted chip select signal: a latch for latching
the signal provided from the NOR gate in response to first through third
delay signals to output first and second latch signals; first and second
delays for delaying the first and second latch signals respectively
provided from the latch for a predetermined time to output first and
second delay signals, respectively; a signal output unit for outputting an
address transition detect signal in response to the first and second latch
signals respectively provided from the latch and the first and second
delay signals respectively provided from the first and the second delays;
a third signal delay for logically operating the first and second latch
signals and the first and second delay signals provided to the signal
output unit, and delaying and outputting the address transition detect
signal provided from the signal output unit.
Also, there is provided another embodiment of an address transition
detection circuit to obtain the above object according to the present
invention including: a NOR gate for NORing an inputted address signal and
an inputted chip select signal; a latch for latching a signal provided
from the NOR gate in response to first through third delay signals to
output first and second latch signals; first and second delays for
delaying the first and second latch signals respectively provided from the
latch for a predetermined time to respectively output the first and second
delay signals; a logical operation unit for logically operating the first
and second latch signals respectively provided from the latch to output an
address transition detect signal; a third signal delay for logically
operating the first and second latch signals provided to the logical
operation unit and the first and second signals respectively provided from
the first and second delays, and outputting the third delay signal in
order to delay the address transition detect signal provided from the
logical operation unit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing an address transition detection circuit
of a conventional memory device;
FIG. 2 is a circuit diagram showing an address transition detection circuit
for a memory, device according to one embodiment of the present invention;
FIGS. 3A to 3C show input and output waveforms in each part of the circuit
of FIG. 2;
FIG. 4 is a circuit diagram showing an address transition detection circuit
for a memory device according to another embodiment of the present
invention;
FIGS. 5A to 5C show input and output waveforms in each part of the circuit
of FIG. 4:
FIG. 6 is a circuit diagram showing an address transition detection circuit
for a memory device according to still another embodiment of the present
invention;
FIGS. 7A to 7C show input and output waveforms in each part of the circuit
of FIG. 6:
FIG. 8 is a circuit diagram showing an address transition detection circuit
for a memory device according to still further embodiment of the present
invention; and
FIGS. 9A to 9C show input and output waveforms in each part of the circuit
of FIG. 8.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described in detail with reference to the
accompanying drawings.
With reference to FIG. 2, an address transition detection circuit for a
memory device according to a first embodiment of the present invention
includes a NOR gate 100 for NORing an inputted address signal ADS and a
chip select signal CSTb; a latch 200 for latching the output signal of the
NOR gate 100 in response to inputted delay signals DS1-DS3 to respectively
output latch signals LAS1 and LAS2; signal delays 300 and 400 each for
delaying the latch signals LAS1 and LAS2 respectively provided from the
latch 200 for a predetermined time to output delay signals DS1 and DS2,
respectively; a signal output unit 500 for outputting an address
transition detect signal ATD in response to the latch signals LAS1 and
LAS2 respectively provided from the latch 200 and the delay signals DS1
and DS2 respectively provided from the signal delays 300 and 400: and a
signal delay 600 for logically operating the latch signals LAS1 and LAS2
and the delay signals DS1 and DS2 provided to the signal output unit 500
and outputting a delay signal DS3 to the latch 200 to delay the outputting
of the address transition signal ATD provided from the signal output unit
500.
The latch 200 includes a logical operation unit 202 for logically operating
the signal provided from the NOR gate 100 and inverted through an inverter
201 and the delay signals DS2 and DS3 respectively provided from the
signal delays 400 and 600; and a logical operation unit 203 for logically
operating the signal provided from the NOR gate 100 and the delay signals
DS1 and DS3 respectively provided from the signal delays 300 and 600.
The signal output unit 500 includes a PMOS transistor Q1 having a source to
which a power supply voltage terminal is connected and a gate to which a
delay signal DS1 line of the signal delay 300 is connected; a PMOS
transistor Q2 having a source to which a drain of the PMOS transistor Q1
is connected and a gate to which a latch signal LAS1 line of the latch 200
is connected; an NMOS transistor Q3 having a drain to which a drain of the
PMOS transistor Q2 is connected so as to be connected commonly therewith
to an address transition detect signal ATD line and a gate to which a
latch signal LAS2 line of the latch 200 is connected; an NMOS transistor
Q4 having a drain to which a source of the NMOS transistor Q3 is
connected, a gate connected in common with the gate of the PMOS transistor
Q2 and a source connected to ground: a PMOS transistor Q5 having a source
to which a power supply voltage terminal is connected and a gate to which
a delay signal DS2 line of the signal delay 400 is connected; a PMOS
transistor Q6 having a source to which a drain of the PMOS transistor Q5
is connected, and a gate connected in common with the gate of the NMOS
transistor Q3; an NMOS transistor Q7 having a drain to which a drain of
the PMOS transistor Q6 is connected so as to be commonly connected
therewith to the address transition detect signal ATD line and a gate
commonly connected to the gate of the PMOS transistor Q5; and an NMOS
transistor Q8 having a drain to which a source of the NMOS transistor Q7
is connected, a gate commonly connected with the gate of the PMOS
transistor Q1 and a source connected to ground.
The signal delay 600 includes a logical operation unit 601 for logically
operating the delay signals DS1 and DS2 respectively provided from the
signal delays 300 and 400: and a logical operation unit 602 for logically
operating an output signal provided from the logical operation unit 601
and the latch signals LAS1 and LAS2 respectively provided from the latch
200.
The logical operation units 202 and 203 include NAND gates ND1 and ND2,
respectively, and the logical operation units 601 and 602 include NAND
gates ND3 and ND4, respectively.
The operation of the address transition detection circuit for a memory
device according to the first embodiment of the present invention as
constructed above will now be described in detail with reference to FIGS.
3A to 3C.
First, at an initial stage, when a low level chip select signal CSTb shown
in FIG. 3A and a low level address signal ADS1 shown in FIG. 3B are
respectively inputted to the NOR gate 100, the NOR gate 100 outputs a high
level signal after NORing the input signals CSb and ADS1.
The NAND gate ND1 of the logical operation unit 202 receives at a first
input terminal thereof a low level signal inverted through the inverter
201 and outputs a high level latch signal LAS1 regardless of a state of
delay signals DS2 and DS3 provided to its second and third input
terminals, while the NAND gate ND2 receives at a first input terminal
thereof the high level signal provided from the NOR gate 100 and outputs a
low level latch signal LAS2 or a high level latch signal LAS1 according to
the state of delay signals DS1 and DS2 respectively applied to the second
and third input terminals thereof.
In this respect, assuming that the low level latch signal LAS2 is outputted
from the NAND gate ND2, the signal delays 300 and 400 delay the high level
latch signal LAS1 and the low level latch signal LAS2 respectively
provided from the NAND gates ND1 and ND2 for a predetermined time, to
output a high level delay signal DS1 and a low level delay signal DS2.
Then, the NAND gate ND3 receives at the respective input terminals thereof
the high level delay signal DS1 and the low level delay signal DS2 from
the signal delays 300 and 400, respectively, NANDing the high level delay
signal DS1 and the low level delay signal DS2, to output a high level
signal, while the NAND gate ND4 receives at the first and second input
terminals thereof the high level latch signal LAS1 and the low level latch
signal LAS2 from the NAND gates ND1 and ND2 and at the third input
terminal thereof the high level signal from the NAND gate ND3, NANDing the
high level latch signal LAS1, the low level latch signal LAS2 and the
latter high level signal, to output a high level delay signal DS3.
Accordingly, the NAND gate ND1 receives at the second input terminal
thereof the low level delay signal DS2 from the signal delay 400 and at
the third input terminal thereof the high level signal DS3 from the NAND
gate ND4, NANDing the signals DS2 and DS3 with the low level signal
applied to the first input terminal thereof, to output a high level latch
signal LAS1, while the NAND gate ND2 receives at the second input terminal
thereof the high level delay signal DS1 from the signal delay 300 and at
the third input terminal thereof the high level delay signal DS3 from the
NAND gate ND4, NANDing the signals DS1 and DS3 with the high level signal
applied to the first input terminal thereof, to output a low level latch
signal LAS2.
On the other hand, assuming that the high level signal LAS2 is outputted
from the NAND gate ND2, the signal delays 300 and 400 delay the high level
signals LAS1 and LAS2 provided from the NAND gates ND1 and ND2 for a
predetermined time, to output high level delay signals DS1 and DS2.
Then, the NAND gate ND3 receives at both input terminals thereof the high
level delay signals DS1 and DS2 from the signal delays 300 and 400,
respectively, NANDing them, to output a low level signal, while the NAND
gate ND4 receives at first through third input terminals thereof the high
level signals LAS1 and LAS2 and the low level signal respectively provided
from the NAND gates ND1-ND3, to output a high level delay signal DS3.
Accordingly, the NAND gate ND2 receives at the second input terminal
thereof the high level signal DS1 from the signal delay 300 and at the
third input terminal thereof the high level signal DS3 from the NAND gate
ND4, NANDing the signals DS1 and DS3 with the high level signal applied to
the first input terminal thereof, to output a low level latch signal LAS2.
Therefore, the PMOS transistor Q1 and the NMOS transistor Q8 of the signal
output unit 500 commonly receive at respective gates thereof the high
level signal DS1 from the signal delay 300 to thereby be turned off and
turned on, respectively, and the PMOS transistor Q2 and the NMOS
transistor Q4 commonly receive at respective gates thereof the high level
signal LAS1 from the NAND gate ND1 so as to be turned off and turned on
thereby, respectively, while the NMOS transistor Q3 and the PMOS
transistor Q6 receive at respective gates thereof the low level signal
LAS2 from the NAND gate ND2 so as to thereby be turned off and turned on,
respectively.
The PMOS transistor Q5 and the NMOS transistor Q7 receive at respective
gates thereof the low level signal DS2 from the signal delay 400 so as to
thereby be turned on and turned off, respectively, thereby outputting a
high level address transition detect signal ATD through the address
transition detect signal ATD line.
Thereafter, when a low level chip select signal CSb shown in FIG. 3A and a
high level address signal ADS2 shown in FIG. 3B having a pulse width "a"
smaller than one-half of a pulse width "Z" of the address transition
detect signal shown in FIG. 3C required for operating the memory device
are inputted, the NOR gate 100 outputs a low level signal after NORing the
input signals ADS2 and CSb.
Then, the NAND gate ND1 receives at the first input terminal thereof a high
level signal from inverter 201, NANDing it with a low level signal DS2 and
a high level signal DS3 respectively applied to the second and third input
terminals thereof, to output a high level signal LAS1, while the NAND gate
ND2 receives at the first input terminal thereof the low level signal from
the NOR gate 100, NANDing it with the high level signals DS1 and DS3
respectively applied to the second and third input terminals thereof, to
output a high level signal LAS2.
Accordingly, the NMOS transistor Q3 and the PMOS transistor Q6 commonly
receive at their gates thereof the high level signal LAS2 from the NAND
gate ND2 so as to be thereby turned on and turned off, respectively, while
the PMOS transistors Q1, Q2 and Q5 and the NMOS transistor Q4, Q7 and Q8
are maintained at their immediately preceding switched conditions, so that
the high level signal ATD provided through the address transition detect
signal ATD line is transitted to be output as a low level signal.
At this time, the NAND gate ND3 outputs a high level signal after NANDing
the high level signal DS1 and the low level signal DS2 respectively
applied to the input terminals thereof, while the NAND gate ND4 receives
at the first and second input terminals thereof the high level signals
LAS1 and LAS2 from the NAND gates ND1 and ND2, respectively, and at the
third input terminal thereof the high level signal from the NAND gate ND3,
NANDing the signals LAS1 and LAS2 and the latter high level signal, to
output a low level signal DS3.
Then, the NAND gate ND1 receives at the third input terminal thereof the
low level signal DS3 from the NAND gate ND4, NANDing it with the high
level signal and the low level signal DS2 respectively applied to the
first and second input terminals thereof, to output a high level signal
LAS1, while the NAND gate ND2 receives at the third input terminal thereof
the low level signal DS3 from the NAND gate ND4, NANDing it with the low
level signal and the high level signal DS1 respectively applied to the
first and second input terminals thereof, to output a high level signal
LAS2.
Therefore, the low level signal ATD is continuously outputted through the
address transition detect signal ATD line.
Thereafter, when the high level signal LAS2 provided from the NAND gate ND2
is outputted as a high level delay signal DS2 through the signal delay
400, the PMOS transistor Q5 and the NMOS transistor Q7 receive at their
gates the high level signal DS2 from the signal delay 400 so as to thereby
be turned off and turned on, respectively, while the PMOS transistors Q1,
Q2 and Q6 and the NMOS transistors Q3, Q4 and Q8 are maintained at their
immediately preceding switched conditions, so that the low level signal
ATD is continuously output through the address transition detect signal
ATD line.
At this time, the NAND gate ND3 receives at the other input terminal
thereof the high level signal DS2 from the signal delay 400, NANDing it
with the high level signal DS1 applied to one input terminal thereof, to
output a low level signal, while the NAND gate ND4 receives at the third
input terminal thereof the low level signal from the NAND gate ND3,
NANDing it with the high level signals LAS1 and LAS2 respectively applied
to the first and second input terminals thereof, to output a high level
signal DS3.
Accordingly, the NAND gate ND1 receives at the second and third input
terminals thereof the high level signals DS2 and DS3 respectively from the
signal delay 400 and the NAND gate ND4, NANDing them with the high level
signal applied to the first input terminal thereof, to output a low level
signal LAS1, while the NAND gate ND2 receives at the third input terminal
thereof the high level signal DS3 from the NAND gate ND4, NANDing it with
the low level signal and the high level signal respectively applied to the
first and second input terminals, to output a high level signal LAS2.
Therefore, the PMOS transistor Q2 and the NMOS transistor Q4 commonly
receive at their gates the low level signal LAS1 from the NAND gate ND1 so
as to thereby be turned on and turned off, respectively, while the PMOS
transistors Q1, Q5 and Q6 and NMOS transistors Q3, Q7 and Q8 are
maintained at their immediately preceding switched conditions, so that the
low level signal ATD is continuously outputted through the address
transition detect signal ATD line.
Thereafter, when the low level signal LAS1 provided from the NAND gate ND1
is outputted as a low level delay signal DS1 through the signal delay 300,
the PMOS transistor Q1 and the NMOS transistor Q8 commonly receive at
their gates the outputted low level signal DS1 so as to thereby be turned
on and turned off, respectively, while the PMOS transistors Q2, Q5 and Q6
and the NMOS transistors Q3, Q4 and Q7 are maintained at their immediately
preceding switched conditions, so that the high level signal ATD is
outputted through the address transition detect signal ADS line.
Consequently, the pulse width of the low level address transition detect
signal ATD provided through the address transition detect signal ATD line
is determined relying on a delay time of the signal delays 300 and 400 and
a logical operating time of the NAND gates ND3 and ND4, and when a high
level address signal ADS2 having a pulse width "a" as shown in FIG. 3B is
inputted to the address transition detection circuit, a low level address
transition detect signal ATD having a pulse width "Z" as shown in FIG. 3C
is outputted.
On the other hand, as shown in FIG. 3B, under the condition that a low
level address signal ADS1 is transitted to a high level address signal
ADS3, if a pulse width "b" of the transitted address signal ADS3 is larger
than one-half of the pulse width "Z" of the address transition detect
signal required for operating the memory device but smaller than the pulse
width "Z" of the address transition detect signal, the high level address
signal ADS3 having the pulse width "b" is inputted, by which when a low
level chip select signal CSb shown in FIG. 3A is inputted, then the
address transition detect circuit is operated in the same way as described
above, so that the low level signal ATD having a pulse width "Z+b" shown
in FIG. 3C is outputted through the address transition detect signal ATD
line.
On the other hand, as shown in FIG. 3B, under the condition that the low
level address signal ADS1 is transitted to a high level address signal
ADS4, if a pulse width "c" of the transitted address signal ADS4 is larger
than the pulse width "Z" of the address transition detect signal required
for operating the memory device, the high level address signal ADS4 having
the pulse width "c" is inputted, by which when a low level chip select
signal CS shown in FIG. 3C is inputted, the address transition detection
circuit is operated in the same way as described above, so that the
address transition detect signal ATD having the pulse width "Z" as shown
in FIG. 3C is outputted.
Thereafter, as shown in FIGS. 3B and 3A, when the high level address signal
ADS4 transits to a low level address signal ADS5 to be input and a low
level chip select signal CSb is inputted, the NOR gate 100 outputs a high
level signal after NORing the input signals ADS5 and CSb.
Then, the NAND gate ND1 receives at the first input terminal thereof a low
level signal through the inverter 201, NANDing it with high level signals
DS2 and DS3 respectively applied to the second and the third input
terminals thereof, to output a high level signal LAS1, while the NAND gate
ND2 receives at the first input terminal thereof a high level signal from
the NOR gate 100, NANDing it with the low level signal DS1 and the high
level signal DS3 respectively applied to the second and third input
terminals thereof, to output a high level signal LAS2.
Therefore, the PMOS transistor Q2 and the NMOS transistor Q4 commonly
receive at their gates the high level signal LAS1 from the NAND gate ND1
so as to thereby be turned off and turned on, respectively, while the PMOS
transistors Q1, Q5 and Q6 and the NMOS transistors Q3, Q7 and Q8 are
maintained at their immediately preceding switched conditions, so that the
high level signal ATD being provided through the address transition detect
signal ATD line is transitted to be outputted as a low level signal ATD.
At this time, the NAND gate ND3 outputs a high level signal after NANDing
the low level signal DS1 and the high level signal DS2 respectively
applied to the input terminals thereof, while the NAND gate ND4 receives
at the first input terminal thereof the high level signal LAS1 from the
NAND gate ND1 and at the third input terminal thereof the high level
signal from the NAND gate ND3, NANDing the high level signal LAS1 and the
latter high level signal with the high level signal LAS2 applied to the
second input terminal thereof, to output a low level signal DS3.
Then, the NAND gate ND1 receives at the third input terminal thereof the
low level signal DS3 from the NAND gate ND4, NANDing it with the low level
signal and the high level signal respectively applied to the first and
second input terminals thereof, to output continuously a high level signal
LAS1, while the NAND gate ND2 receives at the third input terminal thereof
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