According to the present invention, the semiconductor integrated circuit including the reference current generating circuit free from both the influence of a power supply voltage and the influence of the variation of the threshold voltage of the transistors related to the generation of the reference current. In the reference current generating circuit, a P-channel MOS transistor (Qp1), a N-channel MOS transistor (Qn1), a resistor element (R1), and a N-channel MOS transistor (Qn2) are connected in series between the power supply voltage and the ground. The gate and the drain of the N-channel MOS transistor (Qn2) are connected by a short circuit to output the reference current I.sub.ref from a transistor (Qn6) through the resistor element. The integrated circuit is provided with a level shifter connected to the reference current generating circuit such that the threshold voltages of the N-channel transistors (Qn1, Qn2) are added to a reference voltage V.sub.ref by N-channel transistors (Qn3, Qn4) in the level shifter, and the resultant reference voltage V.sub.ref is applied to the gate of the N-channel transistors (Qn1).

A semiconductor integrated circuit includes the reference current generating circuit free from both the influence of a power supply voltage and the influence of the variation of the threshold voltage of the transistors related to the generation of the reference current. In the reference current generating circuit, a P-channel MOS transistor (Qp1), a N-channel MOS transistor (Qn1), a resistor element (R1), and a N-channel MOS transistor (Qn2) are connected in series between the power supply voltage and the ground. The gate and the drain of the N-channel MOS transistor (Qn2) are connected by a short circuit to output the reference current I.sub.ref from a transistor (Qn6) through the resistor element. The integrated circuit is provided with a level shifter connected to the reference current generating circuit such that the threshold voltages of the N-channel transistors (Qn1, Qn2) are added to a reference voltage V.sub.ref by N-channel transistors (Qn3, Qn4) in the level shifter, and the resultant reference voltage V.sub.ref is applied to the gate of the N-channel transistors (Qn1).

The invention relates to an electric circuit for generating a periodic signal comprising: a capacitor device which has a first terminal and a second terminal; a signal node that is connected, via a first signal having a first period is applied; a discharging device that is connected, via a third switching device, to the first terminal and, via a fourth switching device, to the second terminal, whereby the second terminal, via a fifth switching device, and the first terminal, via a sixth switching device, are connected to a first reference potential; and comprising a clock pulse generating device for receiving the first signal and for generating a first switch clock pulse, a second switch clock pulse, and the periodic signal. The first and the second switch clock pulse do not overlap and are inverse with regard to one another. The first, third and fifth switch device can be controlled by the first switch clock pulse, and the second, fourth and sixth switch device can be controlled by the second switch clock pulse. The first and second switch clock pulse and the periodic signal have a second period, which is an even multiple of the first period.

A first PMOS transistor is connected between a supply terminal of a power supply voltage VCC and a connection node MON. A first NMOS transistor and a second NMOS transistor are connected between the connection node MON and ground. The first PMOS transistor and the first NMOS transistor are driven by an input signal. The second NMOS transistor is driven by a constant current IREF. In cooperation with the first NMOS transistor, the second NMOS transistor discharges the charge across a capacitor C1 connected to the connection node MON. A differential amplifier compares a potential at the connection node MON with a potential depending upon the constant current IREF, and outputs a result of the comparison.

An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state. The input circuit includes: four resistor elements serially provided between different fixed potentials; an input terminal connected to a connection point of two of the resistor elements; a switching transistor controlled to turn on and off by a voltage at a connection point of two of the resistor elements; a current supplying circuit outputting a supply current when the switching transistor is on and not outputting the supply current when the switching transistor is off; a constant voltage generating circuit receiving the supply current to output a constant voltage; a constant voltage output buffering circuit that brings its output into a high-impedance state when the switching transistor is off, and that receives the constant voltage to output a prescribed voltage to a connection point of two of the resistor elements when the switching transistor is on; a switching transistor controlled to turn on and off by a voltage between opposing ends of the resistor element; and a combinational circuit outputting identify signals based on combinations of on and off states of the two switching transistors.