A data conversion method, wherein a sequence of first r-bit datawords is divided into groups of x bits where x is the least common multiple of r and m, an arbitrary first dataword selected from x/r groups of first datawords is divided into x/m, an m-bit second dataword is formed by appending r/(x/m)-bit data, obtained by dividing the first dataword into x/m, to the LSB or MSB side of one or other of the non-divided first datawords, and the word-converted m-bit second dataword is converted to an n-bit codeword (m<n).
A bit error measurement circuit is designed to measure a number of bit errors by comparing receiving data with a reference Pseudo-Noise pattern. Herein, a certain PN pattern is used as the receiving data in order to perform testing in performance of communications and transmission by evaluating the receiving data. There are provided multiple kinds of PN patterns each having a specific PN-stage number. The bit error measurement circuit is capable of automatically detecting a PN-stage number with respect to the receiving data. One method to do so is to perform comparison between the receiving data and an arbitrary pattern at timings which are periodically set to correspond to all PN-stage numbers each having a probability to be related to the receiving data, wherein the arbitrary pattern is extracted from the receiving data. Thus, the PN-stage number is automatically detected in response to the timing at which the receiving data coincide with the arbitrary pattern. Another method is to extract consecutive-0s patterns and consecutive-1s patterns from the receiving data and to perform comparison between a count value, corresponding to a number of bits of a longest consecutive-0s pattern, and a count value corresponding to a number of bits of a longest consecutive-1s pattern. So, a PN-stage number and a logic are detected based on result of the comparison between the count values. Thus, a reference PN pattern is generated based on the PN-stage number and the logic.
A method for converting a multi-byte dataword in a first extended interchange code to a multi-byte dataword in a second extended interchange code is disclosed. In accordance with the method and system of the present invention, multiple offset arrays and a conversion matrix are provided. Each entry in each of the offset arrays contains an offset index for indexing to the conversion matrix. First, an index value is returned from a corresponding one of the offset arrays, for each byte of a multi-byte dataword in a first interchange code. Then, all of the returned index values are added together to obtain a multi-byte dataword in a second interchange code from the conversion matrix.
A succession of input data words is converted into a first succession of information code words including first candidate one and a second succession of information code words including second candidate one different from first candidate one. One is selected from the first succession of information code words and the second succession of information code words as a final succession of information code words in a manner such that the absolute value of a DSV relating to the final information-code-word succession will be smaller. Check bits are generated in response to the final information-code-word succession and a predetermined parity generation matrix of LDPC encoding. The check bits are changed to conversion code words. The final information-code-word succession and the conversion code words are combined into an output-code-word sequence which obeys (1, k) RLL, where "k" is a predetermined natural number in the range of 9 to 12.
The information blocks are converted into the code blocks by dividing the information blocks, which are extracted sequentially from an information sequence and acts as a conversion unit, into a plurality of original subblocks, generating a plurality of inverted subblocks containing inverted information, which are obtained by inverting all original information being allocated to one or more segments contained in original subblocks, while correlating the original subblocks with the inverted subblocks respectively, and converting the information blocks into the code blocks by combining the plurality of original subblocks and the plurality of generated inverted subblocks together. Then, the code blocks derived by conversion are restored to the original information blocks by sampling the original information, which are allocated to one or more segments contained in the original subblocks respectively, from respective original subblocks of the code blocks obtained by the conversion.
A method of adding auxiliary data, e.g., audio data, to a high-speed serial video link in such a way that it is invisible to existing receiver and such that auxiliary data, e.g., audio, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data. Some of the DC balancing bits are used to transport the auxiliary data information over the link in a manner that does not change the data recovered by a DVI-CE receiver, or a legacy receiver (installed base). DC balancing is also maintained, but with differences over known techniques. Since the auxiliary data bits (which are occupying the time slots of the DC balance bits) will be interpreted by legacy receivers as DC balance bits, the data must be optionally inverted to remain consistent with the value of the auxiliary data bit being transmitted. The DC balance bit that is transmitted at the beginning of each group of four words must also invert the value of the auxiliary data to allow the DC balancing to be achieved independent of the auxiliary data.
