Within an integrated circuit a source of digital data is coupled to a distant destination by a serial data path that is characterized by being either an imperfect and lossy transmission line or as possessing significant high frequency attenuation. A single phase clock accompanies the data over the serial data path. A single phase to three phase clock generator at the destination creates the three phase clock. If the destination is a shift register, then the three phase clock can be used for stage-to-stage clocking within the shift register, as well as for getting data into the input bit of the shift register.
A shift register matrix including a matrix of cells having a plurality of rows and a plurality of columns, each cell storing one bit of data. A plurality of pulse generators is included to generate pulses to the cells which cause new data to be shifted into the cells. One pulse generator is included for each column of the matrix. The pulse generator for each column is coupled to all the cells in the column. Each pulse generator supplies a pulse to each of the cells in its respective column to cause new data to be shifted into the cells of that column. The pulses are sent to the respective columns in sequential order, one column at a time, until all the data in the matrix has been shifted by one bit.
The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted into any vacated bit positions, and arithmetic shifts in which the value of the original most significant bit is shifted into any vacated bit positions. The present invention includes a general 32-bit shifter that can shift an arbitrary number of places in a single cycle, using any of the modes described above.
