Method and apparatus for manufacturing known good semiconductor die

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FIELD OF THE INVENTION

This invention relates to semiconductor manufacture and more particularly to a method and apparatus for manufacturing known good die.

BACKGROUND OF THE INVENTION

One of the fastest growing segments of the semiconductor industry is the manufacture of multi-chip modules (MCM). Multi-chip modules are being increasingly used in computers to form PC chip sets and in telecommunication items such as modems and cellular telephones. In addition, consumer electronic products such as watches and calculators typically include multi-chip modules.

With a multi-chip module, non-packaged or bare dice (i.e., chips) are secured to a substrate (e.g., printed circuit board) using an adhesive. Electrical connections are then made directly to the bond pads on each die and to electrical leads on the substrate. Non-packaged dice are favored because the costs associated with manufacturing and packaging the dice are substantially reduced. This is because the processes for packaging semiconductor dice are extremely complex and costly.

This is illustrated with reference to FIG. 1. A fabrication process for a packaged die begins with a semiconductor wafer on which a large number of semiconductor dice have been formed by doping, masking, deposition of metals, and etching a silicon substrate. Initially the wafer is probed and mapped, step 10. Wafer mapping is performed to test the gross functionality of the dice on the wafer. The nonfunctional dice are mechanically marked or mapped in software. Next, the mapped wafer is mounted on a carrying film, step 12. The carrying film allows the wafer to be mechanically transported and provides support for the saw cutting procedure.

Next, the dice are singulated using a diamond saw, step 14. Each singulated die must then be attached to a metal lead frame, step 16. A single lead frame supports several semiconductor dice for packaging and provides the leads for the packaged die. Die attach to the lead frame is typically accomplished using a liquid epoxy adhesive that must be cured with heat, step 18. Next, a wire bond process, step 20, is performed to attach thin bond wires to the bond pads on the die and to the lead fingers of the lead frame. A protective coating such as a polyimide film is then applied to the wire bonded die, step 22, and this coating is cured, step 24.

The semiconductor die is then encapsulated using an epoxy molding process, step 26. Alternately premade ceramic packages with a ceramic lid may be used to package the die. Next, the encapsulated die is laser marked for identification, step 28. This is followed by an electrolytic deflash for removing excess encapsulating material, step 30, an encapsulation cure, step 32 and cleaning with a citric bath, step 34. Next, the lead frame is trimmed and formed, step 36, to form the leads of the package, and the leads are plated using a wave solder process (tin or plating), step 38. This is followed by scanning, step 40, in which the packaged dice are optically scanned for defects and then an inventory, step 42.

The packaged die is then subjected to a hot pregrade test, step 44 in which it is tested and then marked, step 46. A series of burn-in tests, steps 48 and 50, and a hot final test, step 52 are then performed to complete the testing procedure. This is followed by another scan, step 54, a visual inspection, step 56, a quality control check, step 58, and packaging for shipping, step 60. The finished goods are represented at step 62.

As is apparent, the packaging process (steps 16-40) for manufacturing packaged dice requires a large amount of time, materials and capital investment to accomplish. Thus one advantage of manufacturing bare or unpackaged dice is that the above manufacturing process can be greatly simplified because all of the packaging steps are eliminated. A disadvantage of manufacturing unpackaged dice is that transport and testing of the dice is more difficult to accomplish.

With unpackaged dice, semiconductor manufacturers are required to supply dice that have been tested and certified as known good die (KGD). Known-good-die (KGD) is a collective term that connotes unpackaged die having the same quality and reliability as the equivalent packaged product. This has led to a need in the art for manufacturing processes suitable for fabricating and testing bare or unpackaged semiconductor die.

For test and burn-in of bare die, a carrier must replace a conventional single chip package in the manufacturing process. The carrier includes an interconnect that allows a temporary electrical connection to be made between external test circuitry and the bond pads of the die. In addition, such a carrier must be compatible with semiconductor manufacturing equipment and allow the necessary test procedures to be performed without damaging the die. The bond pads on a die are particularly susceptible to damage during the test procedure.

In response to the need for unpackaged die, different semiconductor manufacturers have developed carriers for testing known good die. As an example, carriers for testing unpackaged die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc. Other carriers for unpackaged die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.

One of the key design considerations for a carrier is the method for establishing electrical communication between the die and interconnect. With some carriers, the die is placed face down in the carrier and biased into contact with the interconnect. The interconnect includes contacts that physically align with and contact the bond pads or test pads of the die. Exemplary contact structures include wires, needles, and bumps. The mechanisms for making electrical contact include piercing the native oxide of the bond pad with a sharp point, breaking or burnishing the native oxide with a bump, or moving across the native oxide with a contact adapted to scrub away the oxide. In general, each of these contact structures is adapted to form a low-resistance "ohmic contact" with the bond pad. Low-resistance is a negligible resistance. An ohmic contact is one in which the voltage appearing across the contact is proportional to the current flowing for both directions of current flow. Other design considerations for a carrier include electrical performance over a wide temperature range, thermal management, power and signal distribution, and the cost and reusability of the carrier.

The present invention is directed to a method for manufacturing known good die. In addition, the present invention is directed to an apparatus for manufacturing known good die including carriers for testing bare die and apparatus for automatically loading and unloading bare die into the carriers.

OBJECTS OF THE INVENTION

Accordingly, it is an object of the present invention to provide an improved method for manufacturing known good die.

It is yet another object of the present invention to provide improved apparatus for manufacturing known good die.

It is a further object of the present invention to provide an improved method for manufacturing known good die utilizing carriers adapted to test and burn-in a bare, unpackaged die without damage to the die.

It is a still further object of the invention to provide a method for manufacturing known good die utilizing carriers that are reusable and easy to assemble, that provide a reliable electrical connection with contact locations on a die over a wide temperature range, and that can be easily adapted to testing of different types of dice.

It is a still further object of the present invention to provide a method and apparatus for manufacturing known good die that are efficient, reliable and suitable for large scale semiconductor manufacture.

Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method and apparatus for manufacturing known good die are provided. The method of the invention, generally stated, includes the steps of: fabricating a semiconductor wafer containing a plurality of dice; testing the gross functionality of the dice and mapping the wafer; sawing the wafer into discrete die; assembling each discrete die in a carrier having an interconnect and a force distribution mechanism adapted to bias the die and interconnect together; testing the die using the carrier and recording the test data; disassembling the carrier to remove the tested die; and then continuing processing of the tested die for shipment.

The carrier is adapted to retain the die under test and provide a temporary electrical connection between the die and external test circuitry. This enables burn-in and other test procedures to be performed on the die. The carrier includes a carrier base with external connectors and an interconnect for establishing temporary electrical communication between the die and the external connectors.

In addition to the base and temporary interconnect, the carrier includes a force distribution mechanism for retaining and biasing the die and the interconnect together. The force distribution mechanism includes a bridge clamp, a spring clip and a pressure plate. The carrier base, interconnect and force distribution mechanism are designed for efficient assembly and disassembly of the carrier with a die.

The temporary interconnect is formed in a configuration which accommodates a particular die bondpad configuration (e.g., peripheral, array, edge connect, end connect, lead over chip (LOC)) and bondpad structure (e.g., flat pad, solder ball, bumped pad). Different types of interconnects are thus interchangeable to allow testing of the different types of semiconductor dice using a universal carrier. The interconnect includes raised contact members for contacting contact locations (e.g., bond pads, test pads) on the die to form an electrical connection. The contact members are shaped to accommodate flat or raised (e.g., bumped pad) contact locations on the die. Electrical communication between the contact members on the interconnect and the external connectors on the carrier base is provided by conductive traces on the interconnect. The conductive traces are electrically attached to the external connectors on the carrier using wire bonding or a mechanical connection.

Different contact technologies may be employed to form the interconnect. As an example, the interconnect may be formed with a rigid electrically non-conductive substrate (e.g., ceramic, silicon) and thick film contact members formed using an ultrasonic forging process. Alternately the interconnect may formed with silicon substrate and raised silicon contact members having oxide-penetrating blades. The interconnect may also be formed with microbump contact members mounted on a rigid substrate. The microbump contact members can be plated with an oxide penetrating textured metal layer.

During assembly of the carrier and die, the interconnect is placed in the carrier and the die is attached to the pressure plate of the force distribution mechanism using a vacuum. The die and interconnect are optically aligned using a vision system. The die is then placed into contact with the interconnect with a predetermined force so that the contact members on the interconnect form an electrical connection with the contact locations on the die. At the same time the bridge clamp of the force distribution mechanism is attached to the carrier for biasing the die and interconnect together to maintain the electrical connections. The assembled carrier is then tested using suitable burn-in test equipment. Following the test procedure, the carrier is disassembled and the tested die is removed.

This assembly procedure may be performed manually using an optical alignment system similar to an aligner bonder used for flip chip bonding. Alternately an apparatus for automatically assembling and disassembling the carrier can be provided. The automated assembly/disassembly apparatus includes a pick and place system for picking a die from a mapped, saw-cut wafer; a vision alignment system for aligning the die and interconnect; and a robot, responsive to the vision alignment system, that attaches the die to the force distribution mechanism and then attaches the force distribution mechanism to the carrier base. Each carrier is marked with a bar code so that a die can be tracked through the assembly and testing procedures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a prior art semiconductor manufacturing process for manufacturing packaged die;

FIG. 2 is a block diagram illustrating the method of the invention for manufacturing known good die;

FIG. 3 is a perspective view of a carrier suitable for manufacturing known good die in accordance with the method of the invention;

FIG. 3A is a cross sectional view taken along section line 3A--3A of FIG. 3;

FIG. 4 is a plan view showing an interconnect for the carrier of FIG. 3 and illustrating the wire bonding between the interconnect and carrier;

FIG. 4A is a cross section showing a contact member for the interconnect of FIG. 4;

FIG. 4B is a cross section taken along section line 4B--4B of FIG. 4 showing the contact member in contact with a bond pad of a semiconductor die;

FIG. 5 is a cross sectional view of an interconnect having a raised contact member formed of silicon shown engaging a die and illustrating the self limiting raised portions of the contact member;

FIG. 5A is an enlarged portion of the raised silicon contact member shown in FIG. 5 and showing the oxide penetrating raised portions of the contact members;

FIGS. 5B-5G are plan views illustrating different layouts of raised portions for forming contact members;

FIGS. 6-6B are cross sectional views of alternate embodiment interconnects formed with microbump contact members;

FIG. 7 is a schematic diagram illustrating an assembly procedure for aligning the die and interconnect;

FIG. 8 is a block diagram illustrating a process flow for automatically assembling and disassembling the die and carrier; and

FIG. 9 is a schematic plan view of an assembly/disassembly apparatus suitable for use with the method of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 2, the method of the invention is illustrated in a flow diagram. During the semiconductor manufacturing process a semiconductor wafer is fabricated with a large number of dice. The wafer is formed by patterning and doping a semiconducting substrate and then depositing, patterning and etching various layers of material on the substrate to form integrated circuits. Initially, the wafer is subjected to probe testing to ascertain the gross functionality of the dice contained on the wafer. Each die is given a brief test for functionality, and the nonfunctional die are mechanically marked or mapped in software, step 64. Wafer probe includes various functional and parametric tests of each die. Test patterns, timing voltage margins, limits and test sequence are determined by individual product yields and reliability data.

Four testing level