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Claims  |
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What is claimed is:
1. A method of examining a semiconductor wafer that includes a substrate,
at least a region of thin oxide, and determining whether any defects in
the thin oxide are due to weak oxide or are due to charge-damaged oxide,
the method comprising the following steps:
(a) fabricating on said wafer first and second conductive regions overlying
said thin oxide, the first conductive region defining a greater surface
area than the second conductive region;
(b) applying respective first and second stress-inducing current sources
between said first and second conductive regions and said substrate,
wherein magnitudes of said first and second current sources are scaled
proportionately to areas of said first and second conductive regions such
that a substantially constant current density is created;
(c) after step (b), applying a voltage between said first conductive region
and a portion of said substrate, and measuring any first leakage current
flow therebetween;
(d) after step (b), applying a voltage between said second conductive
region and a portion of said substrate, and measuring any second leakage
current flow therebetween; and
(e) comparing said first leakage current and said second leakage current to
ascertain a defect status of said thin oxide;
wherein following step (e) a determination is made that said thin oxide is
substantially defect free, that said thin oxide is weak oxide, or that
said thin oxide is charge-damaged.
2. The method of claim 1, wherein at step (e), if the first and second
leakage currents are each less in magnitude than a predetermined threshold
value, said thin oxide is substantially defect free;
if only the first leakage current exceeds said predetermined threshold
value, defects in said thin oxide are area-dependent and said thin oxide
is weak oxide; and
if the first and second leakage currents each exceed said predetermined
threshold value, defects in said thin oxide are area-independent and said
thin oxide is charge-damaged.
3. The method of claim 1, wherein fabricating said first and second
conductive regions at step (a) is carried out at a first polysilicon level
of formation.
4. The method of claim 1, wherein at least one of said first and second
conductive regions has at least one characteristic selected from the group
consisting of (i) the region includes polycide, (ii) the region includes
polysilicon, and (iii) the region defines a rectangular surface area.
5. The method of claim 1, wherein said first and second conductive regions
define respective areas A.sub.L and A.sub.S that define an area ratio
A=A.sub.L /A.sub.S, where 5.ltoreq.A.ltoreq.100.
6. The method of claim 1, wherein said second conductive region defines an
area A.sub.S, where 1 .mu.m.sup.2 .ltoreq.A.sub.S .ltoreq.100 .mu.m.sup.2.
7. The method of claim 1, wherein at step (b), each of said first and
second stress-inducing current sources provides a current magnitude for a
time duration sufficient to create a current density J such that 0.02
coulombs/cm.sup.2 .ltoreq.J .ltoreq.50 coulombs/cm.sup.2.
8. The method of claim 1, wherein at least one of said first and second
stress-inducing current sources is fabricated on said wafer.
9. The method of claim 1, wherein at least one of said first and second
conductive regions is fabricated in an area of said wafer whereon said
wafer will be scribed.
10. The method of claim 1, wherein prior to step (b), steps are carried out
to form an integrated circuit on said wafer.
11. The method of claim 10, wherein steps (b), (c), (d), and (e) are
carried out before packaging of said integrated circuit.
12. The method of claim 1, wherein steps (c) and (d) include applying
voltage whose magnitude is at least a desired operating voltage of an
active device on said wafer.
13. A method of examining a semiconductor wafer that includes a substrate
and at least a region of thin oxide, and determining whether any defects
in the thin oxide are due to weak oxide or are due to charge-damaged
oxide, the method comprising the following steps:
(a) fabricating on said wafer first and second metal-oxide-semiconductor
devices that each have a source region, a drain region, and a conductive
gate overlying said thin oxide, said gate of the first device defining a
surface area greater than a surface area of said gate of the second
device, wherein neither conductive gate is coupled to a larger surface
area conductive region;
(b) applying respective first and second stress-inducing current sources
between each said gate and said substrate, wherein magnitudes of said
first and second current sources are scaled proportionately to areas of
each said gate such that a substantially constant current density is
created;
(c) after step (b), applying a voltage between said gate of said first
device and a portion of said substrate, and measuring at least one
parameter of said first device;
(d) after step (b), applying a voltage between said gate of said second
device and a portion of said substrate, and measuring at least one
parameter of said second device; and
(e) comparing parameters measured at step (c) and step (d) to determine
whether any deviation from an acceptable parameter range is a function of
surface area of a said gate of one of said devices;
wherein following step (e) a determination is made that said thin oxide is
substantially defect free, that said thin oxide is weak oxide, or that
said thin oxide is charge-damaged.
14. The method of claim 13, wherein at step (e),
if step (e) determines that neither of said first and second devices
exhibits a greater than acceptable parameter deviation, said thin oxide is
substantially defect free;
if only a parameter associated with said first device exceeds an acceptable
parameter range, defects in said thin oxide are area-dependent and said
thin oxide is weak oxide; and
if a parameter associated with said first device and with said second
device exceeds an acceptable parameter range, defects in said thin oxide
are area-independent and said thin oxide is charge-damaged.
15. The method of claim 13, wherein at least one of said first and second
devices is fabricated in an area of said wafer whereon said wafer will be
scribed.
16. The method of claim 13, wherein at least one of said first and second
stress-inducing current sources is fabricated on said wafer.
17. The method of claim 13, wherein the gates have at least one
characteristic selected from the group consisting of (i) the first and
second gate regions define respective areas An and A.sub.s that define an
area ratio A=A.sub.L /A.sub.S, where 5.ltoreq.A.ltoreq.100, (ii) the
second gate region defines an area A.sub.S, where 1 .mu.m.sup.2
.ltoreq.A.sub.S .ltoreq.100 .mu.m.sup.2, and (iii) during step (b), each
of said first and second stress-inducing current sources provides a
current magnitude for a time duration sufficient to create a current
density J across each of said gate regions such that 0.02
coulombs/cm.sup.2 .ltoreq.J .ltoreq.50 coulombs/cm.sup.2.
18. The method of claim 13, wherein prior to step (b), steps are carried
out to form an integrated circuit on said wafer.
19. For fabrication with a semiconductor wafer that includes a substrate
and at least a region of thin oxide, said wafer being subjected to charged
energetic species during fabrication of an integrated circuit thereon, a
differential antenna structure used to determine whether any defects in
the thin oxide are due to weak oxide or are due to charge-damaged oxide,
the structure comprising:
first and second conductive regions defining unequally sized respective
first and second surface areas A.sub.L and A.sub.S, fabricated on said
wafer overlying said thin oxide, neither of said first and second
conductive regions being coupled to a larger area conductive region;
said first and second conductive regions having at least one characteristic
selected from the group consisting of (i) an area ratio A=A.sub.L /A.sub.S
is limited by 5.ltoreq.A.ltoreq.100, and (ii) A.sub.S is limited by 1
.mu.m.sup.2 .ltoreq.A.sub.S 100 .mu.m.sup.2 ; and
means for coupling first and second stress-inducing current sources between
said first and second conductive regions and said substrate;
wherein when first and second stress-inducing current sources are so
coupled, regions of said thin oxide underlying said first and second
conductive regions are stressed, and
during subsequent testing, measurement of a parameter affected by leakage
current between each of said first and second conductive regions and said
substrate identifies any defects in said thin oxide.
20. The structure of claim 19, wherein said structure includes first and
second metal-oxide-semiconductor devices, each having a source region and
a drain region; and wherein said first and second conductive regions are
gates for said first and second metal-oxide-semiconductor devices. |
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Claims |
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Description |
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FIELD OF THE INVENTION
The invention relates to methods and apparatuses for predicting the
reliability of integrated circuits ("ICs"), and more specifically to
predicting reliability of ICs containing a thin oxide layer such as
associated with a metal-oxide-semiconductor ("MOS") device, an IC
capacitor dielectric layer, and the like.
BACKGROUND OF THE INVENTION
Using well known techniques, integrated circuits ("ICs") are fabricated on
a wafer substrate by forming various depositions, layer by layer in a
production facility that is often termed a "lab". For example, an IC
containing metal-oxide-semiconductor ("MOS") devices has a thin layer of
oxide over which a layer of conductive gate material (e.g., polysilicon)
is formed and then defined. The MOS device source and drain regions are
then formed, either by photolithography or by using the defined gates as a
self-aligning mask. In some ICs, a capacitor may be formed by forming a
layer of conductive material such as polysilicon over a thin layer of
oxide. Normal backend processing completes the fabrication of the IC.
The IC is then functionally tested to detect and hopefully screen-out
defective units. Understandably, defective units should not be packaged
and delivered to customers.
In ICs containing MOS devices or IC capacitors, thin oxide (e.g., thin gate
oxide or dielectric oxide) is a substantial factor contributing to IC
failure. Two types of defective oxide are generally recognized in the art:
weak oxide, and charge-damaged oxide.
Weak oxide is oxide that was formed inherently weak during fabrication,
typically due to imperfections in the fabrication process. For example,
the wafers may have been cleaned with contaminated wet chemicals, or
contamination may be present in the gate oxide tube used during
fabrication. In any event, such defects may exist randomly anywhere within
the IC structure, and will affect the reliability of every structure
formed on the wafer that utilizes thin oxide, e.g., every MOS device, and
every capacitor.
By contrast, charge-damaged oxide is oxide that has been subjected to
damage when the IC wafer was exposed to an environment with charged,
energetic species. Such exposure can occur during such fabrication steps
as plasma etching, plasma ashing, plasma deposition, ion implantation, and
sputtering.
It is believed that the primary cause of charge-damaged oxide is charging
of conductors overlying the oxide, typically due to plasma
non-uniformities across the wafer surface. This non-uniformity produces
electron currents and ion currents that do not balance locally. The
resultant imbalance (e.g., net current flux to the wafer) appears to cause
wafer surface charge, with increased voltage across the thin gate or
capacitor oxide. The charging continues until the currents become
balanced, or the thin oxide becomes damaged and begins to conduct,
apparently via Fowler-Nordheim tunnelling.
If weak oxide formation could be identified, one might know to reexamine
certain portions of the fabrication process, perhaps with respect to
removing contamination from the wafer before oxidation. On the other hand,
if charge-damaged oxide could be identified, one might know to reexamine
the charge-producing portions of the fabrication process, perhaps with
respect to generating a more uniform plasma field.
Unfortunately, prior art testing techniques cannot readily differentiate
between an IC containing weak oxide and an IC containing charge-damaged
oxide. Such testing is generally carried out using so-called antenna
structures such as shown in FIG. 1.
In FIG. 1, at least in a preliminary state, an IC is formed on a wafer
whose semiconductor substrate 10 that includes a layer of thin oxide 20
covered by a preferably polysilicon level 1 conducting region 30, as well
as regions of thick field oxide 40. Whereas the thin oxide may be less
than perhaps a few 100 .ANG. in thickness, the field oxide may exceed
several thousand .ANG. in thickness. A relatively large conductive region
50, also preferably fabricated at the polysilicon 1 level, is formed atop
the field oxide 40, and is coupled by a conductive segment 60, e.g.,
polysilicon, to the smaller conducting region 30 that overlies the thin
oxide 20.
The formation of regions 30 and 50 produces two parallel-coupled capacitors
C1 and C2 on a region of the IC wafer that is sufficiently large for
implementation of capacitor C1. The "plates" of capacitor C1 are the large
conductive region 50 and a region of the underlying substrate 10, which
regions are separated by the thick field oxide 40. The "plates" of
capacitor C2 are the smaller conductive region 30, and a region of the
underlying substrate 10, which regions are separated by the thin oxide 20.
The area of conductive region 50 divided by the area of conductive region
30 defines a ratio (A.sub.R) for the antenna structure. Thus, if
conductive region 30 has an area of perhaps 5 .mu.m.sup.2 and conductive
region 50 has an area of 50 .mu.m.sup.2, the antenna ratio A.sub.R is 10;
if conductive region 50 has an area of say 500,000 .mu.m.sup.2, A.sub.R is
100,000, and so on.
As shown in FIG. 1, the thin oxide dielectric layer of capacitor C2 is
substantially thinner than the field oxide dielectric layer of capacitor
C1. As a result, capacitor C2's "plates" are closer together. On one hand,
because capacitance is inversely proportional to the separation between
the capacitor "plates", capacitor C2 exhibits substantially greater
capacitance per unit area than capacitor C1. However, total capacitance
for a capacitor is proportional to plate area. Because the plate area
ratios may well be in the range of several thousand or more, whereas the
ratio between the thick field oxide and the thin oxide may be in the ten
to one hundred range, the area effect will tend to dominate the plate
separation or thickness effect.
Because the two capacitors are coupled in parallel, C1 and C2 see the same
voltage. If a voltage V is induced across the capacitors, e.g., during
plasma etching 100, the following equation governs:
Q1/C1=V=Q2/C2
Thus, any charge Q resulting from the plasma etching 100 will be shared
such that substantially most of the charge will appear across the
relatively large capacitance C1 (e.g., assuming that area effect dominates
thickness effect), e.g., Q=Q1+Q2, where Q1>>Q2. As such, much of the
plasma induced charge Q is collected by conductor region 50. However, any
charge Q2 that exists over the thin oxide 20 covered by plate 30 will have
the greatest impact due to the thinness of the oxide layer 20. Further,
because leakage will occur through the thin oxide layer 20 and not through
the thick field oxide 40, charge Q1 associated with capacitor C1 will be
drained through capacitor C2 to the underlying substrate 10.
Shown generically in FIG. 1 are two types of oxide damage: weak oxide 110
(shown as circles) and charge-damaged oxide 120 (shown as triangles).
These defects behave as if there were a resultant localized thinning of
the oxide layer 20. Thus, while the defects are depicted as circles and
triangles for ease of illustration, it is to be understood that these
symbols do not literally represent the "shape", the "size", or the exact
location of the defects.
Within the thin oxide layer 20, charge sharing can occur between regions of
the layer having a nominal thickness and regions of the layer that are
effectively thinner. The localized capacitance associated with the
effectively thinner regions of layer 20 will be greater than the
capacitance associated with the nominal thickness of layer 20. Thus,
within the capacitor C2 defined over the thin oxide layer 20, there will
be regions of higher capacitance associated with thinner regions of the
oxide, per unit area. Charge distribution within capacitor C2 will tend to
be maximized over the thinned oxide regions that include the defects 110,
120. As a result, the thinner, defect-containing, regions will tend to
breakdown first relative to the nominally thick regions of thin oxide
layer 20.
As suggested by FIG. 1, the weak oxide defects 110 can be found randomly
and perhaps uniformly throughout the thin oxide layer. By contrast, the
charge damage to the oxide will tend to occur beneath the conductive
region 30, since any charge associated with capacitor C2 appears across a
relatively thin oxide region. Any defects in the thick oxide 40 tend to be
buried within and cannot appreciably thin or weaken the thick oxide.
Capacitors C1 and C2 may be formed using the same process steps carried out
on the remainder of the IC wafer. For example, in subsequent process
steps, an inter-layer dielectric may be formed over the polysilicon level
1 regions 30, 50, 60, (and other regions on the wafer). An overlying metal
1 region may then be added, followed by an inter-metal-oxide layer, and
then perhaps an overlying metal 2 region, and so on. These additional
process steps are not depicted in FIG. 1. However, many of these steps may
involve charged energetic species, which can cause substantial charge to
be collected in the conductive region 30. As noted, this charge can give
rise to charge damage 120 in the underlying thin oxide 30. Because C1 and
C2 are used only for testing, they need not be electrically coupled to the
remainder of the IC.
Conventional antenna structures such as capacitors C1 and C2 are used in
the prior art in an attempt to determine quality of thin oxide layer 20.
At the simplest level, oxide testing can include coupling an over-voltage
across the thin oxide, and measuring to determine whether any leakage
current exceeds a predetermined threshold. For example, current exceeding
say 1 nA may indicate either weak oxide, charge-damaged oxide, or both.
Failed parts may be subjected to failure analysis to determine the root
cause of failure.
Unfortunately, while leakage current measurements can identify a wafer
containing weak oxide or charge-damaged oxide, prior art testing cannot
readily discriminate between the two types of damage. A part evidencing
excessive leakage current will be rejected using prior art techniques,
even though the lot may still be usable if the leakage current resulted
from charge-damaged rather than from weak oxide. Because it is not readily
known whether weak oxide or charge-damaged oxide is at hand, one does not
know whether to look for contamination in the fabrication process, or to
re-examine the plasma-generating equipment.
It is also known in the art to test completed ICs using a so-called high
temperature operation life ("HTOL") test that is performed at elevated
temperature and perhaps over-voltage conditions. Industry accepted
protocols for HTOL testing may be found in the "MIL.sub.-- STD.sub.-- 883C
Handbook, Method 1005, Steady State Life". HTOL testing measures
reliability of actual, completed IC products.
In HTOL testing, completed ICs on the wafer are packaged and then a sample,
e.g., perhaps 1,000 parts, is tested to determine oxide reliability.
Because what is HTOL-tested are finished parts, no antenna structures will
be present. The sample ICs are first tested to ensure that they are
functional. If so, the sample parts are mounted on dedicated printed
circuit boards that are installed in an oven maintained at a higher
temperature, perhaps 125.degree. C. The test parts are then electrically
cycled by the application of operating power and test signals.
Understandably at high temperature, the degradation mechanisms are
accelerated, wherein the acceleration factor is known from prior
experiments. To further accelerate testing, over-voltages are coupled to
the parts, such that an IC containing 5 V devices will be tested at an
operating level of perhaps 5.5 VDC, or higher.
The sample parts are tested for a fixed time, removed (or "pulled") from
the oven, cooled, and then re-tested. Any part not passing the test is
considered a failure and is removed from the sample, and perhaps subjected
to failure analysis.
The remaining parts are subjected to further HTOL cycling. A typical
sequence of "pull points" might be after 6, 24, 48, 96, 168, 500 and 1,000
hours of cumulative HTOL testing. At each pull point, about two days of
manpower are required to test the parts. Typically, parts failing before
168 hours are termed "infant mortality", while parts surviving beyond 168
hours are used to calculate the expected failure rate in the field.
Unfortunately, prior art HTOL testing is an expensive and time consuming
undertaking, as is any accompanying failure analysis. Typically the
results of HTOL testing are not available for 2-3 months after the wafer
was fabricated. Thus, prior art testing results in a significant delay
before reliability information for a particular lot of wafers is
available. In the interim, the fab that produced the sample lot may still
be producing ICs with defective oxides, perhaps by using a contaminated
diffusion tube or unbalanced plasma-generating equipment. Further, HTOL
results are applicable primarily to the lot from which the samples were
prepared. However defective oxide may vary from wafer to wafer, and from
lot to lot. Thus, one lot tested for HTOL may have reliable oxide, whereas
the next lot may not, or vice versa.
What is needed is a rapid and inexpensive way to test thin oxides,
preferably at the wafer level before packaging. Such testing should
require less than perhaps an hour per test lot, and should readily discern
between weak oxide and charge-damaged oxide. Testing should be carried out
using test structures and equipment that are not dedicated to the
particular type of IC product being tested. Preferably, such test
structures should be sufficiently small so as not to require substantial
wafer area for implementation.
The present invention provides such a method and testing apparatus.
SUMMARY OF THE INVENTION
Integrated circuits containing MOS devices or IC capacitors have a thin
oxide whose oxide quality can determine reliability and yield of the MOS
devices or capacitors. Applicants have discovered that there is no
significant degradation in the reliability of oxide that has been exposed
to charging, providing the oxide itself was not weak to begin with. Thus,
wafers containing charge-damaged oxide may be used to fabricate MOS
devices and/or capacitors, providing that the MOS gate or capacitor
"plate" is not coupled to a relatively large or long conductive lead that
may act as an antenna.
To discern charge-damaged oxide from weak oxide, the parent application
discloses providing each wafer with at least one pair of differentiating
antenna structures. The structures have an identical antenna ratio A.sub.R
but have different antenna plate areas. Thus, although one antenna
structure is "large" and the other antenna structure is "small" each
structure has the same ratio, e.g., A.sub.R =A.sub.Rlarge =A.sub.Rsmall.
In the embodiments described and claimed in the parent application, each
antenna structure includes coupled-together conductive plate regions of
polysilicon, polycide, or the like.-One plate is formed over thick field
oxide and the other plate is formed over thin oxide on the IC. While
useful to discern charge-damaged oxide from weak oxide, the plates formed
over the thick field oxide region are relatively large, requiring
dedicated wafer area that could otherwise be used for normal IC
fabrication.
In the embodiments described and claimed in the present application,
charge-damaged oxide is discerned from weak oxide using at least first and
second differentially sized gate-like plate regions having respective
"large" and "small" areas A.sub.L and A.sub.S. These regions may be gates
associated with first and second MOS devices, or may merely be the upper
"plates" of first and second capacitors whose dielectric is the thin
oxide. After wafer fabrication but before individual dies are cut, first
and second current sources I.sub.S-L and I.sub.S-S are, respectively,
coupled between these plate regions and the substrate to induce stress in
the thin oxide. The stress current magnitudes are scaled such that
I.sub.S-L /A.sub.L .apprxeq.I.sub.S-S /A.sub.S .apprxeq.K, a constant.
Thus, the thin oxide under the large and small plate regions is subjected
to a constant density current-induced stress. The current-induced charge
simulates charge collected by the "large" antenna structures overlying the
field oxide in the previously described embodiments. Further, the stress
current scaling and resultant constant current density is analogous to the
constant area ratios between coupled-together large and small antennae
pair in the embodiments claimed in the parent application. In the present
application, it is seen that while the larger capacitor or MOS gate plate
may overlie more weak oxide defects, the thin oxide beneath the large and
small plate areas will nonetheless be subjected to a constant current
density stress.
Weak oxide may be characterized by defects that occur randomly and somewhat
uniformly throughout the thin oxide. Thus, in the earlier-described and
claimed embodiments, the region of the larger antenna structure formed
over the thin oxide will overlie more weak oxide defects than will the
corresponding portion of the smaller antenna structure. If wafer test
leakage current across the larger antenna structure exceeds leakage
current across the smaller antenna structure, weak oxide is indicated
because the oxide defect is area dependent. Thus, the wafer under test
should not be used, and the fab should be examined with respect to
contamination and the like that gave rise to the weak oxide. In the more
preferred embodiments described and claimed herein, if wafer test leakage
current across the larger-gate or plate regions exceeds the current across
the smaller-gate or plate, weak oxide is indicated because the oxide
defect is area dependent.
By contrast, charge-induced damage will be substantially independent of the
area ratio of the antenna plates, or of the gate or plate regions in the
presently preferred embodiments. In the earlier described embodiments,
since A.sub.Rlarge .apprxeq.A.sub.Rsmall, the charge per unit capacitor
"plate" area associated with the thin oxide was substantially constant. As
a result, if test leakage current on the wafer was substantially the same
across each antenna structure, charge-damaged oxide was indicated because
the damage was not area dependent. Similarly, in the more preferred
embodiment, if test leakage current on the wafer is substantially the same
across each stressed gate or plate region, charge-damaged oxide is
indicated because the damage is not area dependent. In either embodiment,
the wafer under test may still be used, providing that the completed IC
does not include a large antenna-like structure over the thin oxide.
Further, it is also known that the fab should be re-examined with respect
to possible imbalances in the plasma-generating or other energetic species
generating equipment.
In the various embodiments described in the parent application and herein,
source and drain regions may be formed adjacent the small capacitor plate
region to define a MOS device whose gate is the small plate and whose gate
oxide is the thin oxide. So doing would permit testing MOS device
parameters to discern the state of the gate oxide, rather than solely
testing for leakage current through the gate oxide.
Even if the wafer were never subjected to a field-induced charge during
fabrication (e.g., if no plasma-type process steps were involved, or in
only perfect plasma generators were used), the present invention could
still discern area-dependent weak oxide from any charge-damaged oxide.
Other features and advantages of the invention will appear from the
following description in which the preferred embodiments have been set
forth in detail, in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 depicts an antenna structure for testing thin oxide, according to
the prior art;
FIG. 2 depicts a differential antenna structure for testing thin oxide and
discerning between weak oxide and charge-damaged oxide, according to the
present invention;
FIG. 3A depicts differential antenna test identification of good thin
oxide, according to the present invention;
FIG. 3B depicts differential antenna test identification of weak thin
oxide, according to the present invention;
FIG. 3C depicts differential antenna test identification of charge-damage
thin oxide, according to the present invention;
FIG. 4 depicts differentially-sized gate or plate regions for testing thin
oxide and discerning between weak oxide and charge-damaged oxide,
according to the present invention;
FIG. 5A depicts test identification of good thin oxide using
differentially-sized gate or plate regions, according to the present
invention;
FIG. 5B depicts test identification of weak thin oxide using
differentially-sized gate or plate regions, according to the present
invention;
FIG. 5C depicts identification of charge-damage thin oxide using
differentially-sized gate or plate regions using on-chip stress current
sources, according to the present invention;
FIG. 6 depicts data showing proper identification of weak oxide and
charge-damaged oxide according to the present invention, as contrasted
with incorrect identification according to the prior art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Applicants have discovered that there is no significant degradation in the
reliability of oxide that has been exposed to charging, providing the
oxide itself was not weak to begin with. Thus, wafers containing
charge-damaged oxide may be used to fabricate MOS devices and/or
capacitors, providing that the MOS gate or the capacitor "plate" is not
coupled to a relatively large or long conductive lead that may act as an
antenna. With this limitation, the resultant MOS devices and capacitors
can still have acceptable device yield and reliability.
Thus, in functionally testing ICs, it is important to learn whether the
oxide on a given wafer was defective to begin with (e.g., weak oxide), or
whether subsequent wafer processing produced charge damage. A wafer
containing weak oxide should not be used to form ICs, whereas a wafer
containing charge-damaged oxide may safely be used to form ICs, with
certain exceptions explained later herein. As will now be described, the
present invention permits discerning weak oxide from charge-damaged oxide.
FIG. 2 depicts a first embodiment of the present invention wherein at least
one pair of antenna structures are fabricated on an IC wafer. In several
regards, FIG. 2 is similar to FIG. 1, and similar element reference
numerals are used to refer to similar elements. Thus, in FIG. 2, the IC is
formed from a wafer on a semiconductor substrate 10 that includes a thin
layer of oxide 20, as well as a region of thick field oxide 40. As noted,
thickness of thin oxide 20 is typically in the range of a few hundred
angstrom or less, whereas thickness of the field oxide 40 may be in the
range of several thousand angstrom, or more. Those skilled in the art will
recognize that thin oxide 20 may be used as gate oxide in the formation of
MOS devices on the wafer, or as a dielectric oxide in the formation of
capacitors on the wafer.
The first antenna structure includes a conductive region 30L having area
A.sub.C2L that overlies a region of thin oxide 20, a conductive region 50L
having area A.sub.C1L that overlies a region of thick field oxide 40, and
a conductive segment 60L coupling region 30L to region 50L. The ratio
A.sub.C1L /A.sub.C2L defines an antenna ratio A.sub.R. Regions 30L, 50L
and segment 60L are formed of conductive polysilicon during normal
formation of the gate layer of the IC. In the preferred embodiment,
regions 30L, 50L and segment 60L are formed from conductive polycide,
e.g., tungsten silicide atop polysilicon. Conductive region 50L, the
underlying portion of thick oxide 40, and an underlying portion of the
bottom of substrate 10 collectively define a capacitor C1L. Similarly,
conductive region 30L, the underlying portion of thin oxide 20, and an
underlying portion of the bottom of substrate 10 collectively define a
capacitor C2L.
Generally the area of plate 50L is substantially larger than the area of
plate 30L, and the plate separation for capacitor C2L (e.g., the thickness
of dielectric layer 20) is less than the plate separation of capacitor C1L
(e.g., the thickness of dielectric layer 40). As a result, much of the
charge collected by capacitor C1L will remain over the thick field oxide
layer 40. However, any charge present at capacitor C2L will have a greater
impact due to the thinness of the underlying thin oxide layer 20. Further,
as noted, any leakage across C2L will result in charge transferring from
capacitor C1L to C2L.
It is appreciated from FIG. 2 that because segment 60L couples the upper
"plates" or conductive regions 30L and 50L, capacitor C2L is coupled in
parallel with capacitor C1L. In the present invention, C1L, C2L, C1S and
C2S are used only for testing, and thus need not be electrically coupled
to the remainder of the IC.
Similarly, the sec | | |
