 |
Claims  |
|
|
What is claimed is:
1. A signal processing method for transforming N-bit digital signals into
M-bit digital signals, where M is larger than N, the N-bit digital signals
being obtained by converting an analog signal into digital signals, the
method comprising the steps of:
detecting transition points on a time axis and intervals between the
transition points at which successive digital signals of the N-bit digital
signals vary in value, and at least one interval length in accordance with
the transition points;
generating (M-N) bit additional signals in the interval length in such a
way that an integral value of a first analog value represented by the
M-bit digital signals is substantially equal to an integral value of a
second analog value represented by the N-bit digital signals and the first
analog value is a value within a range of .+-.0.5 least significant bit of
the N-bit digital signals with respect to the second analog value;
delaying the (M-N) bit additional signals so as to correspond to least
significant bits of the N-bit digital signals; and
combining the delayed (M-N) bit additional signals with the N-bit digital
signals to generate the M-bit digital signals.
2. The signal processing method of claim 1, wherein the detecting step
comprises the steps of:
detecting successive first, second and third transition points; and
detecting a first interval length between the first and second transition
points and a second interval length between the second and third
transition points, and
the generating step comprises the step of generating the additional signals
so that the N-bit digital signals are linearly interpolated by the
additional signals in a first signal processing period, the first signal
processing period being from a midpoint of the first and second transition
points and another midpoint of the second and third transition points when
the first and second interval lengths are the same and transition
directions in value of the digital signals at both the second and third
transition points are the same or the first signal processing period
corresponding to either of the first and second intervals which is shorter
than the other and the transition directions at both the second and third
transition points are the same, and generating the additional signals in a
second signal processing period predetermined in accordance with the
second interval length when the transition directions at the second and
third transition points are different from each other, the additional
signals being generated in the second signal processing period in such a
way that the integral value of the first analog value represented by the
M-bit digital signals is substantially equal to the integral value of the
second analog value represented by the N-bit digital signals.
3. A signal processing apparatus for transforming N-bit digital signals
into M-bit digital signals, where M is larger than N, the N-bit digital
signals being obtained by converting an analog signal into digital
signals, the apparatus comprising:
means for detecting transition points on a time axis and intervals between
the transition points at which successive digital signals of the N-bit
digital signals vary in value, and at least one interval length in
accordance with the transition points;
means for generating (M-N) bit additional signals in the interval length in
such a way that an integral value of a first analog value represented by
the M-bit digital signals is substantially equal to an integral value of a
second analog value represented by the N-bit digital signals and the first
analog value is a value within a range of .+-.0.5 least significant bit of
the N-bit digital signals with respect to the second analog value;
means for delaying the (M-N) bit additional signals so as to correspond to
least significant bits of the N-bit digital signals; and
means for combining the delayed (M-N) bit additional signals with the N-bit
digital signals to generate the M-bit digital signals.
4. The signal processing apparatus of claim 3, wherein the detecting means
comprises:
means for detecting successive first, second and third transition points;
and
means for detecting a first interval length between the first and second
transition points and a second interval length between the second and
third transition points, and
the generating means comprises means for generating the additional signals
so that the N-bit digital signals are linearly interpolated by the
additional signals in a first signal processing period, the first signal
processing period being from a midpoint of the first and second transition
points and another midpoint of the second and third transition points when
the first and second interval lengths are the same and transition
directions in value of the digital signals at both the second and third
transition points are the same or the first signal processing period being
corresponding to either of the first and second intervals which is shorter
than the other and the transition directions at both the second and third
transition points are the same, and generating the additional signals in a
second signal processing period predetermined in accordance with the
second interval length when the transition directions at the second and
third transition points are different from each other, the additional
signals being generated in the second signal processing period in such a
way that the integral value of the first analog value represented by the
M-bit digital signals is substantially equal to the integral value of the
second analog value represented by the N-bit digital signals.
5. The signal processing apparatus of claim 3, wherein the detecting means
comprises:
means for delaying the N-bit digital signals by a specific sampling period
carried by first clock signals to generate the successive digital signals;
means for comparing values of the generated successive digital signals to
generate comparison signals when the values are not equal to each other;
means, responsive to the comparison signals and second clock signals 180
degree out of phase from the first clock signals, for generating
transition point signals indicative of the transition points only when the
values of the successive digital signals spaced by the specific sampling
period are not equal to each other; and
means, responsive to the first clock signals and the transition point
signals, for counting a specific number of the first clock signals between
successive transition points to detect the periods.
6. The signal processing apparatus of claim 5, wherein the generating means
comprises:
means, responsive to the comparison signals and the transition point
signals, for generating transition status signals synchronized with the
transition point signals, the transition status signals being indicative
of value transition of the successive digital signals at the transition
points;
means for delaying the transition status signals by means of the transition
point signals;
means, based on the delayed transition point signals, for generating
extreme period signals indicative of periods for the N-bit digital signals
in extreme value;
means for detecting differences in length of the periods;
means storing first (M-N) bit additional signals corresponding to the
periods of extreme value and second (M-N) bit additional signals
corresponding to periods of value transition;
means for reading the first (M-N) bit additional signals in response the
differences in length and the extreme period signals;
means for reading the second (M-N) bit additional signals in response the
transition status signals; and
means for selectively outputting the read first and second (M-N) bit
additional signals.
7. A signal processing method for transforming N-bit digital signals into
M-bit digital signals, where M is larger than N, the N-bit digital signals
being obtained by converting an analog signal into digital signals, the
method comprising the steps of:
detecting transition patterns of successive digital signals of the N-bit
digital signals over transition points on a time axis, at the transition
points the successive digital signals varying;
generating (M-N) bit additional signals in such a way that an integral
value of a first analog value represented by the M-bit digital signal is
substantially equal to an integral value of a second analog value
represented by the N-bit digital signals and the first analog value is a
value within a range of .+-.0.5 least significant bit of the N-bit digital
signals based on the transition patterns;
combining the (M-N) bit additional signals with the N-bit digital signals
so that the (M-N) bit additional signals correspond to least significant
bits of the N-bit digital signals to generate the M-bit digital signals.
8. The signal processing method of claim 7, wherein the detecting step
comprises the steps of:
detecting successive first, second, third and fourth transition points at
which two successive digital signals vary in value; and
detecting transition patterns represented by the detected four transition
points, and
the generating step comprises the step of generating interpolation signals
in accordance with the detected transition patterns so that a linear
interpolation is executed to modified digital signals within a range of
.+-.0.5 least significant bits between the second and third transition
points in correspondence to another linear interpolation already executed
between the first and second transition points, the modified digital
signals being obtained by limiting an N-bit digital signal value at a
transition point between the second and third transition points down to
one least significant bit, thus generating (M-N) bit additional signals
based on the generated interpolation signals.
9. A signal processing apparatus for transforming N-bit digital signals
into M-bit digital signals, where M is larger than N, the N-bit digital
signals being obtained by converting an analog signal into digital
signals, the apparatus comprising:
means for detecting transition patterns of successive digital signals of
the N-bit digital signals over transition points on a time axis, at the
transition points the successive digital signals varying;
means for generating (M-N) bit additional signals in such a way that an
integral value of a first analog value represented by the M-bit digital
signals is substantially equal to an integral value of a second analog
value represented by the N-bit digital signals and the first analog value
is a value within a range of .+-.0.5 least significant bit of the N-bit
digital signals based on the transition patterns; and
means for combining the (M-N) bit additional signals with the N-bit digital
signals so that the (M-N) bit additional signals correspond to least
significant bits of the N-bit digital signals to generate the M-bit
digital signals.
10. The signal processing apparatus of claim 9, wherein the detecting means
comprises:
means for detecting successive first, second, third and fourth transition
points at which two continuous digital signals vary in value; and
means for detecting transition patterns represented by the detected four
transition points, and
the generating means comprises means for generating interpolation signals
in accordance with the detected transition patterns so that a linear
interpolation is executed to modified digital signals within a range of
.+-.0.5 least significant bits between the second and third transition
points in correspondence to another linear interpolation already executed
between the first and second transition points, the modified digital
signals being obtained by limiting an N-bit digital signal value at a
transition point between the second and third transition points down to
one least significant bit, thus generating (M-N) bit additional signals
based on the generated interpolation signals.
11. The signal processing apparatus of claim 9, wherein the detecting means
comprises:
means for delaying the N-bit digital signals by a specific sampling period
carried by first clock signals to generate the successive digital signals;
means for comparing values of the generated successive digital signals to
generate comparison signals and transition status signals indicative of
increase or decrease in value at the transition points when the values are
not equal to each other;
means, responsive to the comparison signals and second clock signals 180
degree out of phase from the first clock signals, for generating
transition point signals indicative of the transition points only when the
values of the successive digital signals spaced by the specific sampling
period are not equal to each other;
means for counting the first clock signals to generate count signals;
means for synchronizing the transition status signals and the count signals
with the transition point signals; and
means, responsive to the synchronized transition status signals and count
signals, for generating transition patterns of the successive digital
signals.
12. The signal processing apparatus of claim 11, wherein the generating
means comprises:
means for detecting differences between the transition points on the time
axis using the count signals and the transition point signals;
means for conducting a specific linear interpolation to the N-bit digital
signals based on the differences and the transition pattern signals; and
means for taking least significant (M-N) bits from the interpolated N-bit
digital signals to generate the (M-N) bit additional signals.
13. The signal processing apparatus of claim 12, wherein the conducting
means conducts the linear interpolation per four successive transition
points.
14. The signal processing apparatus of claim 12, wherein the conducting
means comprises:
means for generating interpolation signals for transition point group each
including specific number of successive transition points;
means for averaging the interpolation signals; and
means for applying the averaged interpolation signals to conduct the linear
interpolation to the N-bit digital signals. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing method and a signal
processing apparatus, and more specifically to a method and apparatus for
transforming N-bit codes such as audio signals, video signals, etc. into
M-bit codes on the condition that M is larger than N.
2. Description of the Prior Art
In the case where signals such as audio or video signals are converted into
digital signals, digital signals having a predetermined number of bits are
generated per sample in conformity with a standard prescribed under due
consideration of various conditions (e.g., transmission, fidelity of
recording and reproduction, apparatus cost, etc.). For instance, in the
case of a compact disk, 16-bit digital signals are recorded per sample.
In FIG. 1, a plurality of thick solid lines S as
a.fwdarw.b.fwdarw.c.fwdarw.d.fwdarw. . . . k.fwdarw.1.fwdarw.m.fwdarw.n,
represent digital signals obtained by quantizing an original analog signal
(by resolution of 1/2.sup.N for each specific sampling period Ts) in a
form of analog signal. Here, the original analog signal resides in the
ranges enclosed by dashed lines including the solid lines S shown in FIG.
1. In other words, there exists an error of less than .+-.0.5 LSB (the
least significant bit) between the original analog signal and the restored
analog signal (obtained by restoring the original analog signal).
Therefore, in the N-bit digital signal obtained by converting the analog
signal in the resolution of 1/2.sup.N, the minute signal as fine as is
obtained by a resolution to more than 1/2.sup.N cannot be restored.
Further, in FIG. 1, t1, t2, t3, . . . denote sequential sampling points,
and Ts denotes a sampling period.
However, there exists so far a need to restore the minute signal using a
resolution of more than a value determined by the number of bits of
digital signals. Therefore, for instance, Japanese Published Unexamined
(Kokai) Patent Application No. 5-304474 has proposed such a method of
transforming N-bit codes into M-bit codes on the condition that M is
larger than N. In a technique of increasing the number of bits disclosed
in this prior art patent, digital signals are smoothed through a digital
low-pass filter so that even the minute level signals can be DA
(Digital-to-Analog) converted without distortion. In other words, data
less than one LSB of the original number of bits can be outputted for DA
conversion.
In this prior art technique, although the N-bit digital signals are
converted into M-bit digital signals (M>N) by use of the digital low-pass
filter, it is impossible to correct the errors of 0.5 LSB involved in the
N-bit digital signals. In addition, since the digital low-pass filter is
used for waveform smoothing, the signal waveform changes. As a result,
when this method is applied to the DA conversion of audio digital signals,
for instance, there exists a problem in that the quality of the audio
digital signals varies.
SUMMARY OF THE INVENTION
The object of the present invention is to obtain high-quality audio signals
and/or video signals with a high resolution on the basis of the
digitalized audio and/or video signals.
To achieve the above-mentioned object, the present invention provides a
signal processing method for transforming N-bit digital signals into M-bit
digital signals, where M is larger than N, the N-bit digital signals being
obtained by converting an analog signal into digital signals, the method
comprising the steps of: detecting transition points on a time axis and
intervals between the transition points at which successive digital
signals of the N-bit digital signals vary in value; generating (M-N) bit
additional signals which correct errors of the N-bit digital signals
within a range of .+-.0.5 least significant bit of the N-bit digital
signals in response to the transition points and the intervals; delaying
the (M-N) bit additional signals so as to correspond to least significant
bits of the N-bit digital signals; and combining the delayed (M-N) bit
additional signals with the N-bit digital signals to generate the M-bit
digital signals.
The detecting step may comprise the steps of: detecting successive first,
second and third transition points; and detecting a first interval length
between the first and second transition points and a second interval
length between the second and third transition points, and the generating
step may comprise the step of generating the additional signals so that
the N-bit digital signals are linearly interpolated by the additional
signals in a first signal processing period, the first signal processing
period being from a midpoint of the first and second transition points and
another midpoint of the second and third transition points when the first
and second interval lengths are the same and transition directions in
value of the digital signals at both the second and third transition
points are the same or the first signal processing period being
corresponding to either of the first and second intervals which is shorter
than the other and the transition directions at both the second and third
transition points are the same, and generating the additional signals in a
second signal processing period predetermined in accordance with the
second interval length when the transition directions at the second and
third transition points are different from each other, the additional
signals being generated in the second signal processing period in such a
way that an integral value of an analog value represented by the M-bit
digital signals is substantially equal to an integral value of an analog
value represented by the N-bit digital signals.
Further, the present invention provides a signal processing apparatus for
transforming N-bit digital signals into M-bit digital signals, where M is
larger than N, the N-bit digital signals being obtained by converting an
analog signal into digital signals, the apparatus comprising: means for
detecting transition points on a time axis and intervals between the
transition points at which successive digital signals of the N-bit digital
signals vary in value; means, responsive to the transition points and the
intervals, for generating (M-N) bit additional signals which correct
errors of the N-bit digital signals within a range of .+-.0.5 least
significant bit of the N-bit digital signals; means for delaying the (M-N)
bit additional signals so as to correspond to least significant bits of
the N-bit digital signals; and means for combining the delayed (M-N) bit
additional signals with the N-bit digital signals to generate the M-bit
digital signals.
The detecting means may comprise: means for detecting successive first,
second and third transition points; and means for detecting a first
interval length between the first and second transition points and a
second interval length between the second and third transition points, and
the generating means comprises means for generating the additional signals
so that the N-bit digital signals are linearly interpolated by the
additional signals in a first signal processing period, the first signal
processing period being from a midpoint of the first and second transition
points and another midpoint of the second and third transition points when
the first and second interval lengths are the same and transition
directions in value of the digital signals at both the second and third
transition points are the same or the first signal processing period being
corresponding to either of the first and second intervals which is shorter
than the other and the transition directions at both the second and third
transition points are the same, and generating the additional signals in a
second signal processing period predetermined in accordance with the
second interval length when the transition directions at the second and
third transition points are different from each other, the additional
signals being generated in the second signal processing period in such a
way that an integral value of an analog value represented by the M-bit
digital signals is substantially equal to an integral value of an analog
value represented by the N-bit digital signals.
Further, the detecting means may comprise: means for delaying the N-bit
digital signals by a specific sampling period carried by first clock
signals to generate the successive digital signals; means for comparing
values of the generated successive digital signals to generate comparison
signals when the values are not equal to each other; means, responsive to
the comparison signals and second clock signals 180 degree out of phase
from the first clock signals, for generating transition point signals
indicative of the transition points only when the values of the successive
digital signals spaced by the specific sampling period are not equal to
each other; and means, responsive to the first clock signals and the
transition point signals, for counting a specific number of the first
clock signals between successive transition points to detect the periods.
Further, the generating means may comprise: means, responsive to the
comparison signals and the transition point signals, for generating
transition status signals synchronized with the transition point signals,
the transition status signals being indicative of value transition of the
successive digital signals at the transition points; means for delaying
the transition status signals by means of the transition point signals;
means, based on the delayed transition point signals, for generating
extreme period signals indicative of periods for the N-bit digital signals
in extreme value; means for detecting differences in length of the
periods; means storing first (M-N) bit additional signals corresponding to
the periods of extreme value and second (M-N) bit additional signals
corresponding to periods of value transition; means for reading the first
(M-N) bit additional signals in response the differences in length and the
extreme period signals; means for reading the second (M-N) bit additional
signals in response the transition status signals; and means for
selectively outputting the read first and second (M-N) bit additional
signals.
Further, the present invention provides a signal processing method for
transforming N-bit digital signals into M-bit digital signals, where M is
larger than N, the N-bit digital signals being obtained by converting an
analog signal into digital signals, the method comprising the steps of:
detecting transition patterns of successive digital signals of the N-bit
digital signals over transition points on a time axis, at the transition
points the successive digital signals varying; generating (M-N) bit
additional signals which correct errors of the N-bit digital signals
within a range of .+-.0.5 least significant bit of the N-bit digital
signals based on the transition patterns; combining the (M-N) bit
additional signals with the N-bit digital signals so that the (M-N) bit
additional signals correspond to least significant bits of the N-bit
digital signals to generate the M-bit digital signals.
The detecting step may comprise the steps of: detecting successive first,
second, third and fourth transition points at which two successive digital
signals vary in value; and detecting transition patterns represented by
the detected four transition points, and the generating step may comprise
the step of generating interpolation signals in accordance with the
detected transition patterns so that a linear interpolation is executed to
modified digital signals within a range of .+-.0.5 least significant bits
between the second and third transition points in correspondence to
another linear interpolation already executed between the first and second
transition points, the modified digital signals being obtained by limiting
an N-bit digital signal value at a transition point between the second and
third transition points down to one least significant bit, thus generating
(M-N) bit additional signals based on the generated interpolation signals.
Further, the present invention provides a signal processing apparatus for
transforming N-bit digital signals into M-bit digital signals, where M is
larger than N, the N-bit digital signals being obtained by converting an
analog signal into digital signals, the apparatus comprising: means for
detecting transition patterns of successive digital signals of the N-bit
digital signals over transition points on a time axis, at the transition
points the successive digital signals varying; means for generating (M-N)
bit additional signals which correct errors of the N-bit digital signals
within a range of .+-.0.5 least significant bit of the N-bit digital
signals based on the transition patterns; and means for combining the
(M-N) bit additional signals with the N-bit digital signals so that the
(M-N) bit additional signals correspond to least significant bits of the
N-bit digital signals to generate the M-bit digital signals.
The detecting means may comprise: means for detecting successive first,
second, third and fourth transition points at which two continuous digital
signals vary in value; and means for detecting transition patterns
represented by the detected four transition points, and the generating
means comprises means for generating interpolation signals in accordance
with the detected transition patterns so that a linear interpolation is
executed to modified digital signals within a range of .+-.0.5 least
significant bits between the second and third transition points in
correspondence to another linear interpolation already executed between
the first and second transition points, the modified digital signals being
obtained by limiting an N-bit digital signal value at a transition point
between the second and third transition points down to one least
significant bit, thus generating (M-N) bit additional signals based on the
generated interpolation signals.
Further, the detecting means may comprise: means for delaying the N-bit
digital signals by a specific sampling period carried by first clock
signals to generate the successive digital signals; means for comparing
values of the generated successive digital signals to generate comparison
signals and transition status signals indicative of increase or decrease
in value at the transition points when the values are not equal to each
other; means, responsive to the comparison signals and second clock
signals 180 degree out of phase from the first clock signals, for
generating transition point signals indicative of the transition points
only when the values of the successive digital signals spaced by the
specific sampling period are not equal to each other; means for counting
the first clock signals to generate count signals; means for synchronizing
the transition status signals and the count signals with the transition
point signals; and means, responsive to the synchronized transition status
signals and count signals, for generating transition patterns of the
successive digital signals.
Further, the generating means may comprise: means for detecting differences
between the transition points on the time axis using the count signals and
the transition point signals; means for conducting a specific linear
interpolation to the N-bit digital signals based on the differences and
the transition pattern signals; and means for taking least significant
(M-N) bits from the interpolated N-bit digital signals to generate the
(M-N) bit additional signals.
The conducting means may conduct the linear interpolation per four
successive transition points.
Further, the conducting means may comprise: means for generating
interpolation signals for transition point group each including specific
number of successive transition points; means for averaging the
interpolation signals; and means for applying the averaged interpolation
signals to conduct the linear interpolation to the N-bit digital signals.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram for assistance in explaining the error of digital
signals obtained by D/A conversion of an analog signal;
FIGS. 2A and 2B are waveform diagrams for assistance in explaining the
operation of the first embodiment according to the present invention,
respectively;
FIGS. 3A to 6B are a series of waveform diagrams for assistance in
explaining the operation of the first embodiment according to the present
invention;
FIG. 7 is a block diagram showing a construction of the first embodiment
according to the present invention;
FIG. 8 is a block diagram showing a more practical construction of a part
of the apparatus shown in FIG. 7;
FIGS. 9 is a waveform diagram showing the respective portions of the
apparatus shown in FIG. 7;
FIG. 10 is a block diagram showing a more practical construction of a part
of the apparatus shown in FIG. 7;
FIGS. 11A to 11C are waveform diagrams for assistance in explaining the
operation of the first embodiment according to the present invention;
FIGS. 12A to 12C are waveform diagrams for assistance in explaining the
operation of the first embodiment according to the present invention;
FIG. 13 is a block diagram showing a part of the apparatus and a waveform
diagram for assistance in explaining the operation of the first embodiment
according to the present invention in combination;
FIG. 14 is a block diagram showing a construction of the second embodiment
according to the present invention;
FIG. 15 is a block diagram showing a more practical construction of a part
of the apparatus shown in FIG. 14;
FIGS. 16A to 16E are waveform diagrams for assistance in explaining the
operation of the second embodiment according to the present invention;
FIGS. 17 to 24 are tables and waveform diagrams for assistance in
explaining the operation of the second embodiment according to the present
invention;
FIGS. 25A to 25D are waveform diagrams for assistance in explaining the
operation of the second embodiment according to the present invention;
FIG. 26 is a block diagram showing a more practical construction of a part
of the apparatus shown in FIG. 14;
FIG. 27 is a block diagram showing a more practical construction of a part
of the apparatus shown in FIG. 14;
FIG. 28 is a waveform diagram for assistance in explaining the operation of
the second embodiment according to the preset invention; and
FIG. 29 a block diagram showing a construction of another embodiment for
adding an additional signal to the digital signals.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The method and apparatus according to the present invention will be
described hereinbelow with reference to the attached drawings. First, the
case will be explained where M-bit codes are obtained with
bit-transformation of N-bit codes (where M>N) obtained by converting an
analog signal into digital signals on the basis of a resolution of
1/2.sup.N.
In the signal processing method and apparatus according to the present
invention, when the values of the N-bit codes increase or decrease in
sequence on the time axis, the length of period (indicated by the number
of sampling periods) during which N-bit code values continue at a constant
level is compared with the length of adjacent period during which N-bit
code values continue also at a constant level.
Further, when a difference in N-bit code value between the two adjacent
periods is one LSB and further when the lengths of the two periods are
different from each other, (M-N)-bit additional signals are generated in
such a way that an N-bit value at a midpoint of the shorter period of the
two adjacent periods can be connected to an N-bit value at another point
of the longer period of the two periods, where the distance from the
border between the two periods to the midpoint equals to the distance from
the border to the other point. The additional signal generated as
described above is added to the N-bit codes so that the M-bit codes can be
generated. Further, in the case of the period at which an M-bit codes
correspond to extreme (maximum or minimum) value, (M-N)-bit additional
signals previously determined on the basis of that period length are added
to the N-bit codes so that the M-bit codes can be generated. On the other
hand, when a difference in N-bit code value between the two adjacent
periods is larger than one LSB, (M-N)-bit additional signals are generated
as described above on the assumption that the difference in code value is
one LSB, and the generated additional signals are added to the N-bit
codes.
FIGS. 2A and 2B show M-bit codes generated by adding the (M-N)-bit
additional signals to the least significant bit of the N-bit codes, by way
of example. In FIG. 2A, the lines Sn represent the codes whose number of
bits are not yet transformed and the lines Sm show generated M-bit codes.
In FIG. 2B, the lines S(m-n) represent the (M-N)-bit additional signals.
In the signal processing method and apparatus according to the present
invention, when the N-bit codes increase or decrease in sequence on the
time axis, the period length during which the N-bit codes of the same
value continue (e.g., the period length between a and b in FIG. 2A) is
compared with the adjacent period (e.g., the period length between c and d
in FIG. 2A). When the two adjacent periods are the same in length, an
additional signal is generated in such a way that two midpoints of the two
adjacent periods can be connected to each other by a line. In other words,
when the period length between a and b is the same as that between c and
d, the additional signal is generated in such a way that the midpoint h of
the period between a and b can be connected to the midpoint i of the
period between c and d by a line.
On the other hand, when the periods of the two adjacent period lengths are
different from each other, the additional signal is generated in such a
way that an N-bit value at a midpoint of the shorter period of the two
adjacent periods can be connected to an N-bit value at another point of
the longer period of the two periods, where the distance from the border
between the two periods to the midpoint equals to the distance from the
boarder to the other point. That is, in FIG. 2A, since the period between
e and f is longer than the period between c and d, an additional signal is
generated in such a way that the midpoint i at the period of the shorter
length between c and d is connected to the point 1 of the longer period
length between e and f. The length between i and the border d equals the
length between the border e and l
Further, in the case of the period at which the M-bit codes indicate an
extreme value, (M-N)-bit additional signals previously determined on the
basis of that period length are added to the N-bit codes, to generate
M-bit codes.
FIGS. 3A to 6B show a series of the N-bit codes Sn', the generated M-bit
codes Sm' and the additional signals S(m-n)' in a form of analog signal in
such a way that the period lengths having the maximum values correspond to
one sampling period (1Ts) to 16 sampling periods (16Ts). As shown in FIGS.
3B, 4B, 5B and 6B, the additional signal S(m-n)' is generated in such a
way that the rectangular area of the maximum portion becomes roughly equal
to the region of the M-bit code Sm' corresponding to the maximum value.
Further, since the N-bit code includes an error of .+-.0.5 LSB, as already
explained, it is also possible to generate the additional signal S(m-n)'
in such a way that the rectangular area of the extreme portion whose
height changes within a range of .+-.0.5 LSB becomes roughly equal to the
area of the region of the M-bit code (Sm) corresponding to the maximum
value.
FIG. 7 shows an example of the signal processing apparatus by which the
signal processing method according to the preset invention can be
realized. In FIG. 7, the signal processing apparatus includes a delay
circuit 3 having a fixedly set delay time, an adder 4, a detector 5 for
detecting the change modes of the signal waveforms, an additional signal
generator 6 for generating an (M-N)-bit additional signal (where M>N), a
variable delay circuit 7 and a delay control signal generator 8.
In FIG. 7, N-bit digital signals to be processed are supplied to the delay
circuit 3 and the detector 5 through an input terminal 1. After having
been delayed by a predetermined constant time by the delay circuit 3, the
N-bit digital signals are supplied to the adder 4. The detector 5 detects
data related to the waveform change modes and the waveform change periods
of the N-bit digital signals supplied through the input terminal 1. The
detected data is supplied to the additional signal generator 6 and then to
the variable delay circuit 7.
According to the change modes and the change periods of the signal
waveforms of the N-bit digital signals, the additional signal generator 6
generates the (M-N)-bit additional signals, and the generated additional
signals are then supplied to the variable delay circuit 7. In other words,
the additional signal generator 6 generates the additional signals
described later, according to whether the signal waveforms increase or
decrease in sequence or whether the period length during which the signal
waveform continues at a constant level is the same in the two adjacent
periods or whether the change of the signal waveform indicates the extreme
point.
The variable delay circuit 7 generates a time delay required to add the
generated additional signal to the least significant bit of the
corresponding N-bit codes. The rate of the generated time delay is
controlled by a delay control signal outputted by the delay control signal
generator 8. In more detail, the delay control signal generator 8
generates a delay control signal on the basis of the signal waveform
change data, the signal waveform change mode data, and the signal waveform
change period data all supplied by the detector 5, and supplies the
generated delay control signal to the variable delay circuit 7.
The adder 4 adds the N-bit digital signals to be processed delayed by the
delay circuit 3 to the (M-N)-bit additional signals delayed by the
variable delay circuit 7, and transmits the resultant M-bit digital
signals through an output terminal 2.
With reference to FIGS. 8 and 9, the practical construction and operation
of the detector 5 will be explained in more detail hereinbelow. In FIG. 8,
the detector 5 is composed of a transition point detector 51 for detecting
transition points of the signal waveforms, a transition state detector 52
for generating a signal indicative of the transition state of the signal
waveform, and an interval detector 53 for detecting the intervals between
the transition points of the signal waveform. The N-bit digital signals to
be processed are supplied to an input terminal 25 of the detector 5, and a
clock pulse Pfs is supplied to another input terminal 26. As the clock
pulse Pfs, a pulse having a frequency the same as the sampling frequency
fs (used when the digital signals to be processed are generated) is used.
In the case where the digital signals to be processed are audio signals, a
pulse having a frequency of 44.1 KHz, for instance is used as the clock
pulse Pfs.
The N-bit digital signals 81 (as shown in FIG. 9) supplied through the
input terminal 25 are given to an A-input terminal of a magnitude
comparator 10 and a data terminal of a D-type flip-flop (DFF) 9. On the
other hand, the clock pulse Pfs (as shown by 82 in FIG. 9) is given to a
clock terminal of the DFF 9. Further, the output signal of a Q terminal of
the DFF 9 is supplied to a B-input terminal of the magnitude comparator
10.
On the basis of the clock pulse Pfs supplied to the clock terminal of the
DFF 9, the DFF 9 delays the N-bit digital signals supplied to the data
terminal by one sampling period, and supplies the delayed digital signals
to the B-input terminal of the magnitude comparator 10.
The magnitude comparator 10 compares the digital signal A supplied to the
A-input terminal thereof with the digital signal B supplied to the B-input
terminal thereof. When the value of the digital signal A is larger than
that of the digital signal B, the magnitude comparator 10 sets an output
terminal A>B to a high level (as shown by 83 in FIG. 9). At this time,
another output terminal A<B is set to a low level (as shown by 85 in FIG.
9). Further, when the value of the digital signal A is equal to that of
the digital signal B, the magnitude comparator 10 sets an output terminal
A=B to a high level (as shown by 84 in FIG. 9) and the other output
terminals A>B and A<B to the low level. Further, when the value of the
digital signal B is larger than that of the digital signal A, the
magnitude comparator 10 sets only the output terminal A<B to the high
level (as shown by 85 in FIG. 9), and sets the other output terminals A>B
and A=B to the low level.
The output signals 83 and 85 of the output terminals A>B and A<B of the
magn | | |
