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Description  |
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TECHNICAL FIELD OF THE INVENTION
The invention relates to mounting a semiconductor device, or integrated
circuit (IC) to a lead frame, flexible lead frame, or tape, for final
packaging. The present invention further relates to an apparatus and
method for testing semiconductor ICs prior to final packaging. More
particularly, the semiconductor IC testing aspects of the present
invention relate to a wafer probe card which utilizes a multi-layer TAB
tape to facilitate in-process testing of IC dies formed on a semiconductor
wafer.
BACKGROUND OF THE INVENTION
Generally speaking, there are three distinct techniques of packaging a
semiconductor device, in any case said package having leads or the like
exiting the package for electrically connecting the packaged die to other
components, either by mounting directly to a printed circuit board or by
plugging the packaged device into a socket which in turn is mounted to a
printed circuit board. These are: (1) plastic molding; (2) ceramic
packaging; and (3) flat packing.
U.S. Pat. No. 5,051,813 (Schneider, et al.), incorporated by reference
herein, provides an example of a plastic-packaged semiconductor device.
Present plastic packaging techniques involve molding a plastic "body"
around a semiconductor die. Prior to molding, the die is attached to a
lead frame having a plurality of leads ultimately exiting the package for
connecting the semiconductor device to external circuits, such as via
conductors on a printed circuit board. Various forms of plastic packs are
known, including DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack)
and PLCC (plastic leaded chip carder). The lead frame is formed from a
single thin layer (foil) of conductive material, which is punched out to
form individual leads. The inner ends of the leads are usually wire bonded
to the active side (components, bond pads) of the die. When handling the
lead frame, prior to the encapsulation, it is exceptionally important to
avoid damaging the closely-spaced, delicate leads.
U.S. Pat. No. 4,972,253, incorporated by reference herein, provides an
example of multi-layer ceramic packages which are laminated structures of
alternate conducting and non-conducting layers, formed of thick conductive
film and nonconductive ceramic, respectively. Generally, the conductive
layers carry only one of signals, power or ground. This approach,
particularly separating the signal plane (layer) from the ground and power
planes, has distinct electrical advantages, which are well known. In this
type of package, the conductive layers are screened or otherwise disposed
between the nonconductive layers, and a very rigid, stable package is
formed. For the signal-carrying layers, lead traces are typically screened
onto an underlying ceramic layer. A die is eventually disposed into an
opening in the package and connected to inner (exposed) ends of the lead
traces. Generally, there is little problem in damaging the lead traces,
since they are well supported by an underlying ceramic layer. Generally,
vias are formed in the package to connect power and ground planes to
particular leads in the signal plane.
U.S. Pat. No. 4,965,702, incorporated by reference herein, provides another
example of a multi-layer package, using polymeric (e.g.) insulating layers
and a copper foil (e.g.) for the conductive layers. Again, an object of
such a multi-layer package is to provide for an electrical multi-layer
conductive package which partitions (separates) the power supply system of
the package from the signal transmission system as much as practical in
order to optimize the performance of both.
These two multi-layer ceramic and polymer packages are also known as "chip
carriers". Both are preferably completely formed prior to mounting the
semiconductor die within an opening in the chip carrier, and in both the
inner leads are well-supported. Hence, both of these chip carriers
inherently avoid the problem of lead damage during handling and mounting
of the die.
FIGS. 1A and 1B show an example of tape-based flat packing. As illustrated
herein, a semiconductor device assembly 10 includes an upper, segmented
plastic film layer 14 (formed of segments 14A, 14B, 14C and 14D), a lower
plastic film layer 16, metallic leads 18 sandwiched between the two
plastic layers 14 and 16, a metallic (preferably copper) die attach pad 20
supported between the two plastic layers 14 and 16, a semiconductor device
22 mounted on the die attach pad 20 and bond leads 24 connecting the
semiconductor device 22 to the leads 18. It is also known to employ
conductive "bumps" on the inner ends of the leads, rather than bond wires,
to connect the leads to the semiconductor die 22, in a tape automated
bonding (TAB) process. The upper and lower plastic layers are suitably
formed of polyimide, and form a thin, insulating supportive structure for
the leads 18. A square, insulating ring ("body frame" or "dam") 26 is
disposed atop the leads 18 between portions 14B and 14C of the upper
plastic fill layer, outside the die area. A layer-like quantity of
silicone gel 28 is disposed over the die 22 and bond wires 24, and acts as
an ionic contamination barrier for the die and as a stress relief for the
leads 24 during assembly of the semiconductor device assembly, and further
prevents an ultimate encapsulation epoxy 30 from contacting the
semiconductor die. Evidently, the inner ends of the leads 18 are very
fragile, and extreme care must be exercised when assembling the die 22 to
the leads 18. In this respect, tape mounting a semiconductor die requires
a similar degree of extreme care when mounting the die to the fine-pitch
conductive leads.
Further examples of mounting semiconductor devices to a tape structure are
shown in U.S. Pat. Nos. 4,800,419 and 4,771,330, incorporated by reference
herein.
As used herein, the term "semiconductor device" refers to a silicon chip or
die containing circuitry and bond sites on one face, and the term
"semiconductor device assembly" refers to the semiconductor chip and
associated packaging containing the chip, including external package leads
or pins for connecting the semiconductor device assembly to a socket or a
circuit board, and including internal connections (such as bond wires,
TAB, or the like) of the chip to inner ends of the leads.
The aforementioned patents relate to semiconductor device assemblies having
a high lead count, which is "de rigueur" in modern semiconductor devices.
The plastic packaging and tape mounting techniques are generally
indicative of methods of mounting semiconductor devices to preformed lead
frames having a plurality of extremely delicate conductors connecting to
the die.
As mentioned above, there are generally two techniques for connecting a die
to inner ends of lead frame conductors, namely wire bonding and
tape-automated bonding (TAB). In TAB, "bumps," typically formed of gold,
are located on either the die ("bumped die") or on the inner ends of the
lead fingers ("bumped tape"). See, e.g., U.S. Pat. No. 4,842,662, FIGS. 5
and 6, respectively.
U.S. Pat. No. 4,842,662, incorporated by reference herein, discloses
bonding integrated circuit components directly to a TAB tape, without the
intermediary of a gold bump, by use of a process employing ultrasonic
energy, pressure, time, heat and relative dimensions of the TAB tape.
Generally, the end of a lead is "downset" (urged down) onto a die. (See
column 6, lines 5-8). This may be thought of as a "bumpless" TAB process.
While the above-referenced patents teach various techniques of forming lead
frames, TAB tapes, and the like, and various techniques for connecting
semiconductor dies to same, these techniques generally involve only one
layer, or plane, of patterned metal conductors (lead fingers), which
single conductive layer represents a single plane carrying signals, power
and ground to the semiconductor die.
As mentioned hereinabove, it is electrically desirable to provide distinct
planes for carrying signal, power and ground from leads (or pins) exiting
the package to the die within the package.
U.S. Pat. No. 4,933,741, incorporated by reference herein, discloses a
multi-layer package for integrated circuits having a ground plane (20)
electrically isolated from a plane of conductors (14) by means of an
insulating layer (16) formed of polyimide. The ground plane (20) is
connected to selected conductors (14) by means of vias (18) extending
through the insulating layer (16). The remaining (non-grounded conductors)
carry signals and power to/from the integrated circuit device (11). As
pointed out therein, "[b]ecause of the small physical size of the
electrical conductors 14, they represent a significant impedance to
operating potential and current 15 applied to the integrated circuit 11
causing an undesirable voltage drop along the length of the conductors 14.
Additionally, capacitive coupling between the conductors 14 causes cross
talk on the conductors 14 which apply signals to and/or derive signals
from the integrated circuit 11. Further, the impedance of the conductors
14 create switching noise when the DC operating current 15 applied to the
integrated circuit varies." And, as noted therein, "the capacitive cross
coupling between the conductors 14 can be reduced by a [separate] ground
plane 20 which also surrounds the integrated circuit 11 and is located
adjacent the plurality of conductors." (See, especially, column 2, lines
31-46).
Despite the generally accepted notion that providing a separate ground
plane has desirable electrical characteristics, the examples set forth
above are limited to rigid, multi-layer ceramic or polyimide or polymer
chip carriers. In both of these multi-layer approaches, it is relatively
feasible to provide vias between separate metal layers and the intervening
insulating layers.
On the other hand, in a tape-mounted, flexible substrate, semiconductor
device assembly, it has generally not been very practical to consider or
implement incorporating a distinct ground plane, since this type of
"flexible" packaging does not lend itself readily to such a multi-layer
approach employing vias spanning insulating layers.
For example, commonly-owned, co-pending U.S. patent application Ser. No.
07/829,977, entitled RIGID BACKPLANE FOR A SEMICONDUCTOR DEVICE ASSEMBLY,
filed on Jan. 31, 1992, by Michael D. Rostoker, discloses an integrated
circuit device package (semiconductor device assembly) having a flexible
substrate including an upper patterned insulative layer, and a lower
patterned conductive layer including a plurality of package leads (lead
fingers). The assembly further includes a rigid or semi-rigid lower
protective layer, formed of ceramic, glass, metal, plastic, and
combinations thereof, which provides enhanced protection from mechanical
and electrical degradation of the packaged device, and which may also
serve as a heat sink. Thus we see that even though it is contemplated to
have a rigid lower layer, which may be metal (i.e., electrically
conductive), it is not contemplated to use the rigid lower layer as a
ground plane connecting electrically to the die. (This is to be
distinguished from the possibility that the rigid lower layer could be
grounded to provide some shielding, but not connected within the package
to the die.) The disclosure of this application is non-essential material.
Prior to packaging IC dies or other semiconductor devices in accordance
with the above-described techniques, it is often desirable to test
individual dies before separating them from a semiconductor wafer.
On-wafer testing significantly improves manufacturing efficiency and
product quality by detecting IC defects at the earliest possible stages in
the manufacturing and assembly process. Wafer probe cards are commonly
used to perform this type of in-process IC testing. A wafer probe card
typically includes a printed circuit board and a number of probe leads
capable of making electrical contact with power, ground and signal bond
sites or test pads on the IC surface. The printed circuit board includes a
pattern of traces which make electrical contact with the probe leads to
carry signals or voltages from external test equipment through the probe
leads to the IC. Individual ICs can thus be powered up and tested without
separating them from the wafer.
One known technique of wafer probe card construction uses manual alignment
and attachment of discrete probe leads to the printed circuit board. The
probe leads are usually long, thin and constructed of either tungsten or
beryllium-copper alloys. Each IC probe is typically individually soldered
to the printed circuit board. The soldering process is particularly
difficult in the case of complex ICs given the large number of probe leads
which must be attached to the printed circuit board within a limited area.
Manual wafer probe card assembly under current practice is therefore
time-consuming and expensive. Manual assembly limits the density of probe
leads which can be accurately aligned and soldered to about 300 probe
leads per printed circuit board. A center-to-center spacing between
adjacent probe leads is generally referred to as "pitch". Manual assembly
also requires that adjacent probe leads have a pitch of greater than about
80 micrometers.
FIG. 8A shows a side sectional view of an exemplary prior art wafer probe
card assembly. A wafer probe card shown generally at 800 includes a
printed circuit board 812 with an inner peripheral edge 813 defining a
central opening. An anodized aluminum insulating ring 814 is disposed
within the central opening 813. Wafer probe card 800 is used to test an IC
die 818 formed on a semiconductor wafer 817. The portion of the wafer
including the die 818 under test is positioned under the insulating ring
814 and central opening 813. A number of wafer probe leads 820 are
manually soldered at an outer end 828 to printed circuit traces 821 formed
on a lower surface 822 of printed circuit board 812. A via hole 823 plated
through with a conductive material connects each lower surface trace 821
to a respective overlying upper surface trace 824. The probe leads 820 are
secured to insulating ring 814 with epoxy 825. Epoxy 825 holds the probe
leads in place a suitable distance apart such that a probe tip of each
probe lead is properly positioned for contacting IC die 818. An external
tester board 826 includes a number of pins 827 for making electrical
contact with upper traces 824 along the outer periphery of printed circuit
board 812. The external tester board 826 applies appropriate test signals
to probe leads 820 by plated through via holes 823 and lower surface
traces 821 and thereby to IC die 818.
In order to test a typical IC, a relatively large number of probe leads 820
are required to interface with the die 818. As the complexity of the IC
increases the required number of probe leads also increases. Each of the
probe leads 820 must be connected to traces 821 in order to interface the
IC to external test equipment. Since the connection typically involves
manual soldering it can be seen that the difficulty of connecting probe
leads 820 with traces 821 is a function of the density and pitch of the
probe leads required on the wafer probe card to test a given IC.
A number of techniques have been developed which use TAB tape or other
types of flexible substrates with etched leads to avoid the problems
associated with the manual alignment and assembly process described above.
U.S. Pat. No. 5,189,363 discloses a technique for improving probe lead
density and pitch by using etched TAB tape leads as wafer probe leads. The
TAB tape leads are brought into contact with the die under test by
applying downward pressure to the inner end of the leads with a pressure
anvil. U.S. Pat. No. 5,036,380 discloses a technique of using TAB tape
etched leads for die probing and connecting certain of the etched leads to
bum-in testing pads on the tape to provide improved IC burn-in testing.
U.S. Pat. No. 4,968,589 discloses a probe card having a number of etched
leads on a dielectric substrate. A ground plane is formed on the opposite
surface of the substrate. The etched leads are used as probes to connect
pads on an IC chip to leads on a printed circuit board.
None of the above techniques includes a suitable means for attaching
certain of the etched leads to a ground plane layer. Attachment is
therefore normally performed in a manner similar to that shown in FIGS. 2A
and 2B of the present invention. U.S. Pat. No. 5,036,380 specifically
provides that "the ground plane is connected to the ground conductors on
the first surface by way of vias formed through the TAB tape." See column
3, lines 41-44. Furthermore, none of the TAB tapes presently used for
wafer probe cards include an efficient means for attaching certain probe
leads to one of several metallized reference planes. A wafer probe card
incorporating presently available TAB tapes such as these will therefore
suffer from drawbacks similar to those discussed above and in conjunction
with FIGS. 1A, 1B, 2A and 2B in the context of IC packages.
The above described techniques for utilizing TAB tape in wafer probe cards
suffer from additional drawbacks. These techniques generally involve using
an etched lead to probe an IC die. In many cases the etched lead material
is not optimal for wafer probing. When a TAB tape is used in a packaging
application, the desirable physical properties of the etched lead material
include tensile strength and elongation. In a typical TAB tape these
properties are optimized for bonding to the IC die. When the TAB tape is
used for wafer probing, a different set of properties are desirable for
the probe tips of the probe leads in order to provide repetitive contacts
to the IC bond sites with adequate lead deflection and form retention.
These properties include stiffness and hardness of the probe tip. The
probe tip should be designed such that it deflects under pressure during
probing and yet is able to return to its original position when pressure
is removed. The probe tip should also maintain its formed shape despite
repeated probing. It may be difficult to meet these conflicting
requirements in many applications by simply using the end of an etched
lead. U.S. Pat. No. 5,189,363 suggests forming or coining the ends of the
etched leads into various shapes. See column 8, lines 46-54. The use of
alternative materials for the etched leads are also suggested. See column
8, line 55 to column 9, line 42. These suggestions all involve using the
same material for the entire etched lead. It is therefore not possible to
optimize the probing properties of the probe tip end of the lead while
simultaneously optimizing the desirable properties of those portions of
the probe lead which do not contact the die. The TAB tape within the wafer
probe card will therefore have to be replaced frequently, resulting in
additional expense and delay.
Presently available wafer probe cards therefore limit the efficiency and
capacity of IC testing. The density and pitch of wafer probe leads is
unduly restricted since the TAB tape used in the wafer probe card
presently requires vias or other inefficient means of interconnecting
specific probe leads to one or more reference planes. Connections to
ground or power planes will continue to take up excessive space on the
tape which could otherwise be used to provide more signal line
interconnections to the IC. It may therefore not be possible to detect a
desirable level of circuit defects in a particular IC using present
techniques. Furthermore, the probe tip portion of the TAB tape probe lead
wears out frequently thereby requiring replacement of the TAB tape and
resulting in additional delay and expense. The limited test capabilities
of existing wafer probe cards will become an even greater problem as more
complex and densely packed ICs are developed.
Hence, we see that there are various desirable and unfulfilled objectives
in the design and implementation of tape-mounted, flexible-substrate
semiconductor device assemblies. It can also be seen from the foregoing
that there is a need for an improved wafer probe card with a higher
density of fine pitch probe leads.
DISCLOSURE OF THE INVENTION
It is an object of the present invention to provide an improved
semiconductor device assembly.
It is a further object of the present invention to provide a multi-layer,
relatively-flexible, tape-like substrate for mounting a semiconductor
device, said substrate [having at least a signal layer distinct from at
least a ground plane.]
It is a further object of the present invention to incorporate at least one
additional electrically conductive plane into a semiconductor device
assembly using tape automated bonding (TAB) assembly techniques.
It is a further object of the present invention to provide a rigid
supportive structure in a TAB package.
It is a further object of the present invention to provide an improved
technique for manufacturing a semiconductor device assembly.
It is a further object of the present invention to provide tooling for
practicing the inventive techniques disclosed.
It is a further object of the present invention to provide a wafer probe
card which includes a multi-layer, relatively flexible tape-like substrate
having a number of conductive probe leads thereon, several of which are
connected to one or more additional conductive layers.
It is a further object of the present invention to provide a wafer probe
card having attached probe tips with desirable probing properties.
According to the invention, a relatively flexible, tape-like substrate for
mounting a semiconductor device has a patterned, conductive layer of
fine-pitch leads extending into a central area in which a semiconductor
die may be connected to the inner ends of the leads. The substrate
includes an underlying insulating (e.g., plastic film) layer supporting
the leads, with an opening larger than the area defined by the inner ends
of the leads so that inner end portions of the leads remain exposed past
the opening in the insulating layer for connecting the leads to the
semiconductor device. Preferably, all of the leads are connected to the
semiconductor device.
A second, additional conductive layer underlies the insulating layer and is
not patterned to form distinct leads, but rather forms a planar ring-like
layer, the inner edge of which extends past the opening in the insulating
layer, but is larger than the die. Hence, the substrate can be viewed as a
sandwich of two conductive layers, one of which is patterned into discrete
conductors (traces) and the other of which is not patterned, and an
insulating layer interposed between the two conductive layers.
According to the invention, a first group (portion) of the total number of
lead traces in the patterned conductive layer are connected to the die,
preferably by TAB bonding or similar process (i.e., rather than by wire
bonding). A remaining, selected portion of the lead traces in the
patterned conductive layer are also connected at their inner ends to the
die, and are then: (1) broken off at or just within the edge of the
opening in the insulating layer, leaving an inner end portion of the
selected lead traces disconnected from the remaining portion of the
selected lead traces, one end of the inner end portion bonded to the die
and the other end of the inner end portion being a "free" end, and are
then (2) bent downwards past the insulating layer so that the free ends of
the inner end portions of the traces contact an inner edge portion of the
additional conductive layer extending into the opening of the insulating
layer, and are then (3) bonded at their free ends to the inner edge
portion of the ring. In this manner, the additional conductive layer can
act as a ground (or power) plane connected to the die.
The additional conductive layer also extends under window-like slits near
the outer edges of the insulating layer, where a similar process of
cutting, bending and bonding outer portions of the selected lead traces,
beyond the outer portions, exit the ultimate semiconductor device
assembly, and can be connected to external ground (or power).
Hence, the additional conductive layer can be used to conduct ground (or
power) from external portions of the selected lead traces to inner end
portions of the lead traces, to the die, bypassing on a different plane
the remaining intermediate portions of the lead traces which are intended
(primarily) to carry signals to and from the die. In this manner, a
distinct ground (or power) plane is established which is isolated from the
patterned conductive layer (primarily signal paths), and the beneficial
electrical characteristics discussed above accrue to a flexible,
tape-mounted semiconductor device assembly.
Further according to the invention, two additional conductive layers are
formed, one for ground and one for power. In a manner similar to that set
forth with respect to one additional conductive layer, selected leads are
cut, bent and connected to inner and outer edge portions of one additional
conductive layer, and selected other leads are cut, bent and connected to
inner and outer edge portions of the second additional conductive layer.
Further according to the invention, the selected and other selected lead
traces are cut at an edge of the insulating (plastic) layer between the
patterned conductive layer and the first additional (or simply
"additional" if only one) conductive layer by urging downward on the
selected and selected other lead traces with a bonding tool.
Further according to the invention, in a first bonding step, a bonding tool
is used to cut, bend and partially bond a free end of the selected and
selected other (if applicable) traces to the first and second (if
applicable) additional conductive layers. In a second bonding step, the
bonding tool is repositioned and bonds the already stabilized (tacked to
the additional layer) free end of the lead trace to the additional
conductive layer.
Further according to the invention, various methods of TAB bonding a
conductive trace to an additional conductive layer, avoiding the use of
bias, are disclosed.
Further according to the invention, various bonding tools for effecting TAB
bonding of lead traces to an additional conductive layer are disclosed.
Further according to the invention, a tool (die pedestal) for aiding in the
assembly of the die to the tape substrate, and for aiding in cutting,
bending and bonding the selected and selected other lead traces to the
additional conductive layer(s) is disclosed.
Further according to the invention a multi-layer, relatively flexible
tape-like substrate having a first conductive layer patterned to have a
number of probe leads thereon is incorporated into a wafer probe card. The
first conductive layer of probe leads are formed on an insulating layer
having an inner peripheral edge defining a central opening in which an IC
die is placed for testing. The inner ends of the probe leads extend toward
the die in the central opening in order to apply test signals to the die
during testing. The insulating layer further includes an inner peripheral
opening near its inner peripheral edge and a second conductive layer on a
side of the insulating layer opposite the probe leads. An inner edge
portion of the second conductive layer is also exposed through the inner
peripheral opening in the insulating layer. In accordance with this
further aspect of the present invention, selected probe leads are cut
substantially at an outer edge of the first inner peripheral opening in
the insulating layer, bent past the insulating layer and bonded to the
exposed inner edge portion of the second conductive layer. An inner edge
of the inner peripheral opening provides additional support for the inner
end portion of the probe lead after it is broken and attached to the
conductive layer.
Further according to the invention, an outer peripheral opening is provided
in the insulating layer near an outer peripheral edge of the insulating
layer and an outer edge portion of the second conductive layer is also
exposed through the outer peripheral opening. The selected probe leads are
cut substantially at an inner edge of the outer peripheral opening in the
insulating layer, bent past the insulating layer and bonded to the outer
edge portion of the second conductive layer. The second conductive layer
thereby provides a path for power or ground signals from outer ends of the
probe leads to the inner ends of the probe leads and thus to an IC bond
site during IC testing. The outer ends of the probe leads may further be
attached to traces on a printed circuit board in order to facilitate
electrical interconnection of the outer ends of the probe leads to
external test equipment.
Further according to the invention the inner ends or inner end portions of
the probe leads may have a distinct probe tip attached thereto such that
the material of the probe tip may be selected to provide desirable probe
tip properties. The probe tip material may be selected such that the
properties of the probe tip are substantially different than the
properties of the probe lead formed on the insulating layer.
Other objects, features and advantages of the invention will become
apparent in light of the following description thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a plan view of a prior art technique of tape-mounting a
semiconductor device to a flexible substrate.
FIG. 1B is a cross-sectional view of the prior art technique of FIG. 1A,
taken on a line 1B--1B through FIG. 1A.
FIG. 2A is a cross-sectional view of a prior art technique of forming a
two-metal-layer, TAB-type semiconductor device assembly, using vias to
connect the two metal layers together.
FIG. 2B is a top plan view of a portion of the assembly of FIG. 2A.
FIG. 3A is a perspective view, partially in cross-section, of a multi-layer
flexible substrate mounting a semiconductor die, with one additional
conductive layer, according to the present invention.
FIG. 3B is a top plan view of a semiconductor device assembly formed
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