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Description  |
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BACKGROUND OF THE INVENTION
The present invention relates to a data transmission circuit, data line
driving circuit and amplifying circuit for use in the data transmission
circuit, and semiconductor integrated circuit and semiconductor memory
each of which comprises the data transmission circuit.
In recent years, the capacity of a dynamic RAM (DRAM), which is among
semiconductor integrated circuits (LSI), has been increasing at a rate of
quadrupling in three years. With the increasing capacity, the chip area of
the DRAM has also multiplied 1.5-fold between every adjacent generations
(e.g., between the 1M-bit and 4M-bit generations). With the increasing
chip area, the wire length of signal lines for transmitting data in the
DRAM has also increased, thus inviting an increase in wiring capacitance.
Furthermore, an increase in the number of wired signal lines due to a
tendency of the DRAM toward a multi-bit configuration has also spurred the
increase in wiring capacitance.
In the DRAM, charging and discharging of the signal lines accounts for the
most part of its power consumption. The above increase in wiring
capacitance in turn increases a charging and discharging current and
eventually brings about an increase in the total power consumption of the
DRAM. The increase in wiring capacity also induces an increase in signal
delay.
With the increasing miniaturization of a MOS transistor element in the
DRAM, a voltage-withstand ability of its oxide film has also raised a
problem.
To overcome the problem, there has been an effort to reduce an internal
source voltage in a conventional DRAM in order to improve the reliability
of the oxide film as well as reduce the power consumption and signal
delay. In the conventional DRAM, a reduced voltage VINT which was
generated inside a DRAM chip based on an external source voltage VCC is
supplied to a MOS transistor circuit on the chip.
Reducing the voltage amplitude of a signal line is extremely effective in
reducing the total power consumption of an LSI: Japanese Laid-Open Patent
Publication No. 4-211515 discloses a data transmission circuit which
operates with a small amplitude based on an internal source voltage that
has been reduced (reduced voltage). In the data transmission circuit, a
driver circuit composed of CMOS transistors drives a single data line for
transmitting data with a small amplitude. A receiver circuit, as shown in
FIG. 18, receives a signal having a small amplitude from the data line and
converts it to a signal having a larger amplitude.
However, the conventional data transmission circuit mentioned above is
disadvantageous in that, if a wire for transmitting data becomes
considerably long, an input IN of the receiver circuit shown in FIG. 18
changes only slowly, resulting in a lower operating speed. This is because
the receiver circuit will not operate till the input IN thereof reaches
(VCL-Vtn) or (VSL-Vtp) and that it is composed of a source-follower
circuit, so that Vtn and Vtp are increased due to a body effect. In
addition, the conventional data transmission circuit requires two power
supplies VCL and VSL, which causes an increase in power consumption
accordingly.
To increase the operating speed, it is possible to compose the input part
of the receiver circuit of an NMOS and PMOS, each having lower Vtn and
Vtp. In order to reduce the threshold voltages of the MOS transistors,
however, more steps and more masks are needed in their fabrication
processes. To reduce the transition time of a signal inputted to the
receiver circuit, it can also be considered to provide a CMOS inverter in
the upper stage of the receiver circuit, which disadvantageously generates
a leakage current between the VCL and VSL in the off state.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of the foregoing. It is
therefore an object of the present invention to implement higher-speed
data transmission consuming lower power even if a long wire is installed.
To attain the above object, a data transmission circuit for use in a
semiconductor integrated circuit according to the present invention
comprises, as shown in FIG. 6: a first circuit (driver circuit) 6a for
converting a first pair of differential signals, each having a first
amplitude, to a second pair of differential signals, each having a second
amplitude smaller than the above first amplitude; a pair of signal lines
(pair of data lines) 20 for transmitting the second pair of differential
signals obtained through the conversion by the above first circuit 6a; a
second circuit (amplifying circuit) 30 for converting the second pair of
differential signals transmitted through the above pair of signal lines 20
to a third pair of differential signals, each having a third amplitude;
and a third circuit (latch circuit) 40 for latching the third pair of
differential signals obtained through the conversion by the above second
circuit 30.
With the above structure, data transmission through the pair of data lines
20 can be implemented by means of the second pair of differential signals,
each having a voltage amplitude smaller than that of the first pair of
differential signals (pair of differential input signals). Consequently,
even when the wire length of the pair of data lines 20 is large, the
influence on data transmission of the parasitic resistance and parasitic
capacitance of the pair of data lines 20 on data transition can be
suppressed as well as a charging and discharging current and signal delay
can be reduced, thus realizing a semiconductor integrated circuit which
operates at a high speed and consumes lower power. Moreover, since a peak
current can be reduced due to the reduced charging and discharging
current, the reliability and noise resistance of signal lines can be
improved. Furthermore, since the third circuit 40 is provided in the lower
stage of the second circuit 30, the output load on the second circuit 30
is reduced so that the second circuit 30 can be reduced in size, thereby
suppressing a current flowing from a power-source terminal to a ground
terminal.
Preferably, in the above data transmission circuit, a ground line of the
above first circuit is provided independently of ground lines of other
circuits in the above semiconductor integrated circuit. With the above
structure, a stable operation is ensured for the first circuit without
being affected by a variation in the ground level due to the operation of
the other circuits.
Preferably, in the above data transmission circuit, the operation of the
above second circuit is halted in synchronization with the latching of the
above third pair of differential signals by the above third circuit. With
the above structure, power consumption of the semiconductor integrated
circuit can further be reduced.
Preferably, the above data transmission circuit further comprises, as shown
in FIG. 11, a fourth circuit (equalizing circuit) 60 for equalizing the
potentials of the above pair of signal lines (pair of data lines) 20. With
the above structure, the time required for a potential difference between
the pair of signal lines 20 to reach a specified value is shortened, so
that data transmission is performed at a higher speed.
To attain the above object, a data line driving circuit (driver circuit) 6a
for differentially driving a pair of data lines 20 in a semiconductor
integrated circuit according to the present invention comprises, as shown
in FIG. 6: a pair of differential input terminals 11 and 12 for accepting
a first pair of differential signals each having a first amplitude; a pair
of differential output terminals 14 and 15 connected to the above pair of
data lines 20 so as to output a second pair of differential signals each
having a second amplitude; a first NMOS transistor Qn11 having a gate
connected to one terminal 11 of the above pair of differential input
terminals 11 and 12, a drain connected to one terminal 14 of the above
pair of differential output terminals 14 and 15, and a source connected to
a power source line; a second NMOS transistor Qn12 having a gate connected
to the other terminal 12 of the above pair of differential input terminals
11 and 12, a drain connected to the drain of the above first NMOS
transistor Qn11, and a source connected to a ground line; a third NMOS
transistor Qn13 having a gate connected to the gate of the above second
NMOS transistor Qn12, a drain connected to the other terminal 15 of the
above pair of differential output terminals 14 and 15, and a source
connected to the above power source line; and a fourth NMOS transistor
Qn14 having a gate connected to the gate of the above first NMOS
transistor Qn11, a drain connected to the drain of the above third NMOS
transistor Qn13, and a source connected to the above ground line.
With the above structure in which the data line driving circuit 6a is
composed of the NMOS transistors, a large voltage can be obtained between
the gate and source of each of the NMOS transistors Qn11 to Qn14. Even
when the lower-limit value of the threshold voltages of the NMOS
transistors is constrained to 0.3 V to 0.6 V, a large force to drive the
pair of signal lines can be obtained, so that high-speed data transmission
can be implemented with a voltage amplitude smaller than 1.5 V without
increasing leakage currents flowing in the off state. Moreover, the data
line driving circuit 6a according to the present invention requires only
one power source, whereas a conventional data line driving circuit
composed of CMOS transistors requires two power sources, so that power
consumption of the semiconductor integrated circuit can further be
reduced. Furthermore, since the data line driving circuit can be composed
solely of the NMOS transistors, it can be fabricated easily.
Preferably, in the above data line driving circuit 6a, the threshold
voltages of the above first and third NMOS transistors Qn11 and Qn13 are
lower than the threshold voltages of the above second and fourth NMOS
transistors Qn12 and Qn14. With the above structure, even when the
threshold voltages of the first and third NMOS transistors Qn11 and Qn13
positioned on the power-source side are set to a value lower than a
conventional lower-limit value (approximately 0.3 to 0.6 V), leakage
currents flowing through the Qn11 and Qn13 in the off state are prevented
by the second and fourth NMOS transistors Qn12 and Qn14 positioned on the
ground side. Consequently, by setting the threshold voltages of the Qn11
and Qn13 lower than the threshold voltages of the Qn12 and Qn14, the
driving forces of the Qn11 and Qn13 can further be enhanced without
increasing the leakage currents flowing in the off state.
To attain the above object, an amplifying circuit for amplifying a pair of
differential signals inside a semiconductor integrated circuit according
to the present invention comprises, as shown in FIG. 17: a pair of
differential input terminals 31 and 32 for accepting the above pair of
differential signals; an amplifier 36 for amplifying the pair of
differential signals inputted via the above pair of differential input
terminals 31 and 32; a pair of differential output terminals 34 and 35 for
outputting the pair of differential signals which have been amplified by
the above amplifier 36; and a power source controller 37 for controlling
power supply to the above amplifier 36 based on outputs from the above
pair of differential output terminals 34 and 35.
With the above structure, power supply to the above amplifier 36 is
controlled based not on the pair of differential input signals, each
having the smaller amplitude, but on the pair of differential output
signals which have been amplified by the amplifier 36. Consequently, the
operation of the amplifier 36 can surely be halted, thereby further
reducing the power consumption of the semiconductor integrated circuit.
Preferably, in the above amplifying circuit, the above power source
controller 37 comprises, as shown in FIG. 17, first and second PMOS
transistors Qp37 and Qp38 which are connected in series to each other and
which are interposed between a power source line and the above amplifier
36, wherein the above first PMOS transistor Qp37 has its gate connected to
one terminal 35 of the above pair of differential output terminals 34 and
35, and the above second PMOS transistor Qp38 has its gate connected to
the other terminal 34 of the above pair of differential output terminals
34 and 35. With the above structure, since outputs are the pair of
differential signals, at least either of the first and second PMOS
transistors Qp37 and Qp38 constituting the power source controller 37 is
surely turned off.
To attain the above object, a semiconductor integrated circuit according to
the present invention comprises, as shown in FIG. 9: a main source wiring
system 56 and a subordinate source wiring system 57, each having a power
source line and a ground line; a first circuit block 51 connected directly
to the above main source wiring system 56; a second circuit block 52
connected directly to the above subordinate source wiring system 57; and a
source-system coupled circuit 70 interposed between the above main source
wiring system 56 and subordinate source wiring system 57 so as to prevent
noise propagation from the above first circuit block 51 to the above
second circuit block 52.
With the above structure, the source-system coupled circuit 70 interposed
between the main source wiring system 56 and subordinate source wiring
system 57 suppresses the noise propagation from the first circuit block 51
to the second circuit block 52.
Preferably, in the above semiconductor integrated circuit, the above
source-system coupled circuit 70 comprises, as shown in FIG. 9, first and
second NMOS transistors Qn71 and Qn72 which are connected in parallel to
each other and which are interposed between the ground line of the above
main source wiring system 56 and the ground line of the above subordinate
source wiring system 57, the above first NMOS transistor Qn71 has its gate
supplied with a control clock, and the above second NMOS transistor Qn72
has its gate connected to the ground line of the above subordinate source
wiring system 57. With the above structure, if the first NMOS transistor
Qn71, which is one of the two NMOS transistors Qn71 and Qn72 constituting
the source-system coupled circuit 70, is turned on in response to the
control clock, the ground line 56 for the main source wiring system is
connected to the ground line 57 for the subordinate source wiring system
with a low impedance. While the first NMOS transistor Qn71 is in the off
state, the second NMOS transistor Qn72 functions as a MOS diode for
preventing the noise propagation from the ground line 56 for the main
source wiring system to the ground line 57 for the subordinate source
wiring system. Consequently, even when the second circuit block 52 has a
driver circuit which handles the above pair of differential signals, each
having the smaller voltage amplitude, the malfunction thereof can be
prevented.
To attain the above object, a first semiconductor memory according to the
present invention comprises, as shown in FIG. 1 or FIG. 2: a data
processing unit 3 and at least one memory unit 2 disposed on a single
semiconductor chip 1; and a pad 4 disposed on the above semiconductor chip
1 so as to perform at least either of the inputting of a signal from the
outside of the semiconductor chip 1 or the outputting of a signal to the
outside thereof, the above pad 4 being disposed between that portion of
the above semiconductor chip 1 in which the above memory unit 2 is
disposed and that portion of the above semiconductor chip 1 in which the
above data processing unit 3 is disposed.
With the above structure, since the memory unit 2 and data processing unit
3 are provided on the same semiconductor chip 1, a conventional data
exchange between a memory chip and a data processing chip becomes no more
necessary, so that the data transmission speed can be increased easily,
thus providing a data processing system that is simple and densely packed.
Moreover, since it is no more necessary to provide a data bus for
connecting the memory chip to the data processing chip on the board, a
current for driving the data bus on the board can be saved, thereby
reducing power consumption of the data processing system. In addition,
since the pad 4 is disposed at precisely the midpoint between the memory
unit 2 and data processing unit 3, the lengths of wires connecting the pad
4 to the memory unit 2 and connecting the pad 4 to the data processing
unit 3 can be reduced. As a result, a delay in the operating speed can be
prevented. Furthermore, since a wired region can be reduced, an increase
in chip area can be prevented and an input capacitance of a signal line
terminal viewed from the outside can also be reduced. Consequently, a
simple data processing system which allows high-speed processing can be
constituted and an optimum layout in a semiconductor chip can be achieved.
Preferably, in the above first semiconductor memory provided with a
plurality of memory units 2, as shown in FIG. 1, the above data processing
unit 3 is disposed in the central portion of the above semiconductor chip
1, the above plurality of memory units 2 are disposed in the marginal
portion of the above semiconductor chip 1, and the above pad 4 is disposed
in the intermediate portion positioned between the central portion and
marginal portion of the above semiconductor chip 1. With the above
structure, the data processing unit 3 is disposed in the central portion
of the semiconductor chip 1 and the plurality of memory units 2 are
disposed in the marginal portion of the semiconductor chip 1, so that the
lengths of wires connecting the memory units 2 to the data processing unit
3 are equal. Consequently, and undesired reduction in the operating speed
which results from the access of the processing unit 3 to a specific
memory unit 2 can be prevented.
To attain the above object, a second semiconductor memory according to the
present invention comprises, as shown in FIG. 3(a) and 3(b): a memory
array 122 and data processing unit 3 disposed on a single semiconductor
chip 1; a source voltage terminal (source voltage pad) 125 disposed on the
above semiconductor chip 1 so as to supply a source voltage to the above
memory array 122 and data processing unit 3; a ground voltage terminal
(ground voltage pad) 126 disposed on the above semiconductor chip 1 so as
to supply a ground voltage to the above memory array 122 and data
processing unit 3; a memory array supply voltage generating circuit
(reference voltage generating circuit) 127 disposed on the above
semiconductor chip 1 so as to receive the source voltage from the above
source voltage terminal 125 and the ground voltage from the above ground
voltage terminal 126 and generate a memory array supply voltage to be
supplied to the above memory array 122; and a means for cutting off a
current (switching element) 129 disposed on the above semiconductor chip 1
so as to cut off a current flowing from the above source voltage terminal
125 through the above memory array supply voltage generating circuit 127
to the above ground voltage terminal 126.
With the above structure, in the case of inspecting a source current
flowing through the data processing unit 3 on standby, a current flowing
from the source voltage terminal 125 through the memory array supply
voltage generating circuit 127 to the ground voltage terminal 126 can be
cut off by the means for cutting off a current 129, so that a source
current failure during standby can be detected in the data processing unit
3. Consequently, a simple data processing system which allows high-speed
data processing can be constituted as well as an effective inspection can
be executed with respect to a source current during standby.
To attain the above object, a third semiconductor memory according to the
present invention comprises, as shown in FIGS. 5(a) and 5(b): a memory
array 122 and data processing unit 3 disposed on a single semiconductor
chip 1; a first source voltage terminal (first source voltage pad) 125a
disposed on the above semiconductor chip 1 so as to supply a source
voltage to the above memory array 122; a second source voltage terminal
(second source voltage pad) 125b disposed on the above semiconductor chip
1 so as to supply the source voltage to the above data processing unit 3;
and a memory array supply voltage generating circuit (reference voltage
generating circuit) 127 disposed on the above semiconductor chip 1 so as
to receive the source voltage from the above first source voltage terminal
125a and generate a memory array supply voltage to be supplied to the
above memory array 122.
In the above structure, there are provided: the first source voltage
terminal 125a for supplying the source voltage to the memory array 122 and
memory array supply voltage generating circuit 127; and the second source
voltage terminal 125b for supplying the source voltage to the data
processing unit 3. As a result, a current flows from the first source
voltage terminal 125a into the memory array supply voltage generating
circuit 127 and does not affect a current flowing from the second source
voltage terminal 125b into the data processing unit 3. In the case of
inspecting a source current during standby, therefore, the measurement of
the source current flowing through the memory array 122 on standby can be
performed independently of the measurement of the source current flowing
through the data processing unit 3 on standby, so that it is also possible
to detect a source current failure in the data processing unit 3 on
standby. Moreover, since the control signal for controlling the means for
cutting off a current (switching element), which was required in the above
second semiconductor memory), is not required, control over the chip can
be simplified. Consequently, a simple data processing system which allows
high-speed data processing can be constituted as well as an effective
inspection can be executed with respect to a source current during standby
.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a layout diagram showing an example of a DRAM according to a
first embodiment of the present invention;
FIG. 2 shows another layout diagram showing another example of the DRAM in
which the components are placed differently;
FIG. 3(a) is a block diagram showing an example of a circuit for supplying
a specified voltage to a memory array and data processing unit in the DRAM
of the first embodiment;
FIG. 3(b) is a block diagram showing the structure of a voltage converting
circuit in the circuit of FIG. 3(a);
FIG. 4 is a circuit diagram showing the structure of a reference voltage
generating circuit in the voltage converting circuit of FIG. 3(b);
FIG. 5(a) is a block diagram showing another example of the circuit for
supplying a specified voltage to the memory array and data processing unit
in the DRAM of the first embodiment;
FIG. 5(b) is a block diagram showing the structure of the voltage
converting circuit in the circuit of FIG. 5(a);
FIG. 6 is a circuit diagram showing the structure of a data transmission
circuit in the DRAM of the first embodiment;
FIGS. 7(a) to (g) are timing charts showing the operation of the data
transmission circuit according to the first embodiment;
FIG. 8 is a wiring diagram showing an example of a ground line in the DRAM
of the first embodiment;
FIG. 9 is a wiring diagram showing another example of the ground line in
the DRAM of the first embodiment;
FIG. 10 is a circuit diagram showing the structure of a source voltage
reducing circuit;
FIG. 11 is a circuit diagram showing the structure of the driver circuit
6a.;
FIGS. 12(a) to 12(h) are timing charts showing the operation of the data
transmission circuit according to a second embodiment;
FIG. 13(a) is a circuit diagram showing a circuit to be subjected to a
simulation in the data transmission circuit of a conventional DRAM;
FIG. 13(b) is a circuit diagram showing a circuit to be subjected to a
simulation in the data transmission circuit according to the first
embodiment;
FIG. 13(c) is a circuit diagram showing a circuit to be subjected to a
simulation in the data transmission circuit according to the second
embodiment;
FIGS. 14(a) to (d) are timing charts showing conditions for a simulation in
the circuits of FIGS. 13(a) to 13(c);
FIG. 15 is a view showing the results of a simulation on the power
consumption of the circuits of FIGS. 13(a) to 13(c);
FIG. 16 is a view showing the results of a simulation on the power
consumption of the circuits of FIGS. 13(a) to 13(c);
FIG. 17 is a circuit diagram showing the structure of an amplifying circuit
for use in the data transmission circuit of the DRAM according to the
third embodiment; and
FIG. 18 is a circuit diagram showing the structure of a receiver circuit in
a conventional data transmission circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
Below, a first embodiment of the present invention will be described with
reference to the drawings.
FIG. 1 is a view showing a DRAM according to the first embodiment, in which
eight memory units 2 and a data processing unit 3 are provided on a
semiconductor chip 1. The data processing unit 3 is disposed in the
central portion of the semiconductor chip 1, while the eight memory units
2 are disposed in the marginal portion of the semiconductor chip 1 so as
to surround the data processing unit 3. In the intermediate portion
between the central portion and marginal portion of the semiconductor chip
1 are disposed a plurality of input pads 4 for accepting an external
signal. The intermediate portion also serves as a wired region in which
wires for interconnecting the memory units 2, data processing unit 3, and
input pads 4 (the drawing thereof is omitted with some exceptional parts).
In the DRAM in which the memory units 2, data processing unit 3, and input
pads 4 are disposed on the semiconductor chip 1, the operation between the
memory units 2 and data processing unit 3 is free from an undesired speed
reduction resulting from the access of the data processing unit 3 to a
specified memory unit 2, since the distances between the individual memory
units 2 and the data processing unit 3 on the semiconductor chip 1 are the
same. The operation between the memory units 2 or data processing unit 3
and the outside of the semiconductor chip 1 is also free from a speed
reduction, since the input pads 4 are positioned precisely at the
midpoints between the memory units 2 and data processing unit 3 and hence
it is possible to reduce the length of a wire connecting the input pad 4
to the memory unit 2 and the length of a wire connecting the input pad 4
to the data processing unit 3. Moreover, since the wired region can be
reduced, an increase in chip area and the input capacitance of a signal
line terminal viewed from the outside of the semiconductor chip 1 can also
be reduced advantageously.
Each of the memory units 2 comprises: a memory core 5 including a memory
array, decoder circuit, control circuit, and the like; an I/O block 6; and
a voltage conversion circuit 7 for generating an internal source voltage
to be used inside the memory unit 2. The I/O block 6 has a data transfer
element 6c for executing bilateral data transfer between the memory unit 2
and data processing unit 3 via a data bus 10. The data transfer element 6c
consists of: a driver circuit 6a for sending data to the data bus 10 so
that the data is transferred to the data processing unit 3; and a receiver
circuit 6b for receiving from the data bus 10 the data sent from the data
processing unit 3.
The data processing unit 3 comprises: a data processing block 8 for
performing intrinsic data processing; and an I/O block 9 having a data
transfer element 9c which consists of a driver circuit 9a and a receiver
circuit 9b, similarly to the memory unit 2.
In the present embodiment, although data transfer is performed only between
the data processing unit 3 and each of the memory units 2, it is possible
to exchange data between the memory units 2. It is also possible to
constitute the pad 4 so that it not only accepts an external signal but
also outputs a signal generated inside the DRAM to the outside.
FIG. 2 is a view showing another example of the layout of the components of
the DRAM. A description of the same components as shown in FIG. 1 is
omitted here by providing the same reference numerals. As shown in FIG. 2,
it is possible to provide the memory unit 2 and data processing unit 3 on
the same semiconductor chip 1 so that the memory unit 2 is disposed on one
portion of the semiconductor chip 1 (on the right of FIG. 2), while the
data processing unit 3 is disposed on the other portion thereof (on the
left of FIG. 2), with a plurality of input pads 4 aligned in the central
portion of the semiconductor chip 1 lying between the portion in which the
memory unit 2 is disposed and the portion in which the data processing
unit 3 is disposed. In the case where a plurality of memory units 2 are
used, they are aligned on one portion (e.g., on the right of FIG. 2) of
the semiconductor chip 1.
FIG. 3(a) exclusively shows one memory unit 2, the data processing unit 3,
and a circuit for supplying a specified voltage to these component from
the outside, which are provided in the DRAM of the present embodiment
shown in FIG. 1.
In FIG. 3(a), a memory array 122 constituting the memory core of the memory
unit 2 and the data processing unit 3 are provided on the same
semiconductor chip 1. On the semiconductor chip 1 are also provided: the
voltage conversion circuit 7; a source voltage pad 125 for supplying a
source voltage VDD to the memory array 122 and data processing unit 3; and
a ground voltage pad 126 for supplying a ground voltage VSS to the memory
array 122 and data processing unit 3. The voltage conversion circuit 7
receives the source voltage VDD from the source voltage pad 125 and the
ground voltage VSS from the ground voltage pad 126 and generates, e.g., a
reference voltage or a 1/2 source voltage.
FIG. 3(b) is a block diagram showing the structure of the voltage
conversion circuit 7. As shown in FIG. 3(b), the voltage conversion
circuit 7 consists of: a reference voltage generating circuit 127 serving
as a memory array supply voltage generating circuit; a driving circuit
128; and a switching element 129 serving as a means for cutting off a
current which is brought into the non-conducting state by activating a
test control signal TCS. As shown in FIG. 4, the simplest embodiment of
the reference voltage generating circuit 127 is composed of a resistance
130. FIG. 4 shows a circuit in an ordinary state in which the switching
element 129 is conducting. In this case, a current is allowed to flow from
the source voltage pad 125 through the resistance 130 to the ground
voltage pad 126, thereby dividing the source voltage VDD and generating a
voltage VDD/2 at an output node 131.
In a DRAM in which the memory array and data processing unit are mounted
together, a current flowing from the source voltage pad 125 through the
reference voltage generating circuit 127 to the ground voltage pad 126 in
inspecting a source current during standby is larger than a source current
flowing through the data processing unit 3 on standby by two to three
orders of magnitude. Consequently, a source current failure in the data
processing unit 3 on standby is disadvantageously hidden by the source
current flowing through the memory array 122 on standby.
In the present embodiment, however, the switching elements 129 are
interposed between the source voltage pad 125 and the reference voltage
generating circuit 127 of the voltage conversion circuit 7 and between the
ground voltage pad 126 and the reference voltage generating circuit 127 of
the voltage conversion circuit 7, so as to overcome the above
disadvantage.
In the case of inspecting the source current flowing through the memory
array 122 on standby, the test control signal TCS is inactivated so as to
measure the current with the switching elements 129 in the conducting
state.
In the case of inspecting the source current flowing through the data
processing unit 3 on standby, on the other hand, the test control signal
TCS is activated so as to measure the current with the switching elements
129 in the non-conducting state. As a result, since the current is not
allowed to flow from the source voltage pad 125 to the ground voltage pad
126, a source current failure in the data processing unit 3 on standby can
be detected.
Although the switching elements 129 are provided between the source voltage
pad 125 and the reference voltage generating circuit 127 of the voltage
conversion circuit 7 and between the ground voltage pad 126 and the
reference voltage generating circuit 127 of the voltage conversion circuit
7, a similar effect can be obtained if either of the switching elements
129 is solely provided.
FIG. 5(a) shows another example of the circuit for supplying a specified
voltage to the memory array 122 of the memory unit 2 and to the data
processing unit 3.
In FIG. 5(a), the memory array 122 constituting the memory core of the
memory unit 2 and the data processing unit 3 are provided on the same
semiconductor chip 1. On the semiconductor chip 1 are also provided: the
voltage conversion circuit 7a; a first source voltage pad 125a for
supplying the source voltage VDD to the memory array 122; a first ground
voltage pad 126a for supplying the ground voltage VSS to the memory array
122; a second source voltage pad 125b for supplying the source voltage VDD
to the data processing unit 3; and a second ground voltage pad 126b for
supplying the ground voltage VSS to the data processing unit 3. The
voltage conversion circuit 7a receives the source voltage VDD and the
ground voltage VSS from the first source voltage pad 125a and from the
first ground voltage pad 126a, respectively, and generates, e.g., the
reference voltage and 1/2 source voltage.
FIG. 5(b) is a block diagram showing the structure of the voltage
conversion circuit 7a. As shown in FIG. 5(b), the voltage conversion
circuit 7a consists of: the reference voltage generating circuit 127
serving as the memory array supply voltage generating circuit; and the
driving circuit 128. The reference voltage generating circuit 127 used
here is the same as the reference voltage generating circuit shown in FIG.
4.
In the present embodiment, the first source voltage pad 125a connected to
the memory array 122 and to the voltage conversion circuit 7a is
physically separated from the second source voltage pad 125b connected to
the data processing unit 3, while the first ground voltage | | |
