Semiconductor memory device - Patent Review 5652723

Claims

What is claimed is:

1. A semiconductor memory device comprising:

a DRAM array including a plurality of dynamic type memory cells arranged in a matrix of rows and columns;

an SRAM array including a plurality of static type memory cells arranged in a matrix of rows and columns, each row of said SRAM array divided into n groups of said static type memory cells with n greater than or equal to 2, said SRAM array including a plurality of sets of n word lines each connected to memory cells of a different group, each set of n word lines arranged corresponding to each row of said SRAM array, static type memory cells on a row being arranged in a line, and each set of n word lines arranged in parallel with a corresponding row of said static type memory cells; and

data transfer means provided between said DRAM array and SRAM array for transferring data between a selected memory cell of said DRAM array and a selected memory cell of said SRAM array.

2. A semiconductor memory device according to claim 1, wherein

said SRAM array further includes a plurality of pairs of bit lines each pair arranged in each column of said static type memory cells, a plurality of equalize/precharge means provided for each said pair of bit lines and responsive to a precharge/equalize signal for precharging and equalizing a potential of an associated pair of bit lines, and a plurality of clamping means provided for each said bit line and responsive to a clamping signal for clamping a potential of an associated bit line.

3. A semiconductor memory device according to claim 2, wherein said clamping means are adapted to be inhibited from clamping when said data transfer means is activated.

4. A semiconductor memory device according to claim 1, wherein said data transfer means includes a plurality of transfer gate means each provided for n adjacent codes of said SRAM array,

said transfer gate means simultaneously operating for data transfer between said SRAM array and said DRAM array.

5. A semiconductor memory device according to claim 4, wherein said DRAM array includes a plurality of data transmission lines, one for each said transfer gate means, for transferring data between selected memory cells of DRAM array and said transfer gate means, and wherein each said transfer gate means includes selection means for selecting one of associated n columns of the SRAM array in response to a group designating signal, and means for transferring data between a column selected by said selection means and an associated data transmission line.

6. A semiconductor memory device according to claim 2, wherein said DRAM array includes a plurality of data transmission lines, one for each transfer gate means, for transferring data between the transfer gate means and selected memory cells of DRAM array, and wherein each said transfer gate means includes first means coupled to receive and amplify potentials on associated n pairs of bit lines of SRAM array, second means for latching an output of said first means, third means responsive to a first control signal for transferring data latched in said second means to an associated data transmission line, fourth means coupled to receive and amplify a potential on the associated data transmission line, and fifth means in response to a second control signal and a group designating signal for selecting one of associated n pairs of bit lines and transferring an output of said fourth means to thus selected pair of bit lines.

7. A semiconductor memory device according to claim 6, wherein said first means includes logic gate means for carrying out a logical operation on potentials received from associated bit lines.

8. A semiconductor memory device according to claim 1, further comprising:

read data transmission line coupled to said transfer means

driving means provided for each column of the DRAM array and responsive to a read DRAM column selection signal for amplifying and transferring data on a column of the DRAM array selected by said read DRAM column selection signal to said read data transmission line;

write data transmission line provided separately from said read data transmission line and coupled to said transfer means for receiving data therefrom;

write-in means responsive to a write DRAM column selection signal for transferring data on said write data transmission line onto a column of the DRAM array; and

sense amp means provided separately from said driving means and for sensing,

amplifying and latching a potential on associated columns.

9. A semiconductor memory device according to claim 8, wherein said transfer means includes:

current supply means for supplying a current flow to said read data transmission line;

gate means responsive to a first transfer signal for transferring data on said read data transmission line onto a selected column of the SRAM array; and

write transfer means responsive to a second transfer signal for transferring data on the selected column of the SRAM array to said write data transmission line.

10. A semiconductor memory device according to claim 9, wherein

each of said column of the DRAM matrix includes a pair of bit lines and said read data transmission line includes a pair of signal lines, and said current supply means includes means for providing the same amount of current flow to the pair of signal line of said read data transmission line.

11. A semiconductor memory device according to claim 10, wherein

said driving means includes a plurality of differential means provided for each column of the DRAM array and responsive to the DRAM column selection signal for amplifying a potential difference between an associated pair of bit lines;

said differential means and said current supply means constituting a current mirror type amplifier in combination.

12. A semiconductor memory device according to claim 8, wherein said driving means is adapted to be made active at an earlier timing than activation of said sense amp means.

13. A semiconductor memory device according to claim 8, further including:

first selection means responsive to a first address applied to a first address input, for generating a SRAM cell selecting signal;

second selection means responsive to a second address applied to a second address input provided separately from said first address input, for generating a DRAM row selection signal for selecting a row of the DRAM array; and

third selection means responsive to a third address applied to said first address input simultaneously with said second address, for generating said read DRAM column selection signal and said write DRAM column selection signal.

14. A semiconductor memory device according to claim 1, further comprising:

burst means responsive to a burst mode signal for successively generating a burst address; and

selection means responsive to said burst address for generating a SRAM cell selection signal for selecting a memory cell of said SRAM array.

15. A semiconductor memory device according to claim 14, wherein said burst means includes

address generating means responsive to said burst mode signal and a received address for generating the burst addresses starting at said received address successively,

control means responsive to said burst mode signal and the number of burst addresses generated from said address generating means for defining a period of burst mode operation; and

multiplexing means responsive to said control means for selectively transferring one of a burst address and an internal address corresponding to an external address to said selection means.

16. A semiconductor memory device according to claim 15, wherein said address generating means is adapted to generate a burst signal in response to a clock signal, and said control means includes defining means for counting the clock signal to inhibit the multiplexing means from selecting a burst address signal from said address generating means when the count reaches a predetermined value.

17. A semiconductor memory device according to claim 16, wherein said control means includes storage means for storing an information on the number of data accessed in the burst mode, and said defining means includes means for inhibiting said multiplexing means from selecting the burst address when the count coincides with the number indicated by said information.

18. A semiconductor memory device according to claim 1, further including:

clock generating means responsive to an external clock signal for generating an internal clock signal; and

sleep means responsive to a sleep mode signal for inhibiting the clock generating means from generating the internal clock,

said internal clock providing timing of taking an external signal into said memory device.

19. A semiconductor memory device according to claim 18, wherein

said sleep means includes means receiving an external signal applied asynchronously with said external clock signal as said sleep mode signal and responsive thereto for generating a sleep mode indicating signal to deactivate said clock generating means.

20. A semiconductor memory device according to claim 18, further comprising:

detecting means for detecting inhibition of generation of the internal clock;

request means in response to the detection of inhibited clock generation for generating a refresh request signal at predetermined intervals; and

refresh address means in response to the refresh request signal for generating a refresh address for refreshing a memory cell of the DRAM array.

21. A semiconductor memory device according to claim 20, wherein said refresh address means includes gate means responsive to an external refresh designating signal and said refresh request signal for generating a refresh mode indicating signal, and refresh address generating means responsive to said refresh mode indicating signal for generating said refresh address.

22. A semiconductor memory device according to claim 1, further comprising:

refresh address generating means for generating a refresh address for refreshing a memory cell of the DRAM array,

auto-refresh means responsive to an external refresh mode signal for activating said refresh address generating means;

refresh mode setting means for generating a mode signal setting a refresh mode of said memory device to either an auto-refreshing mode or a self-refreshing mode;

self-refresh means responsive to said mode signal indicating the self-refreshing mode for activating said refresh address generating means at prescribed intervals; and

input/output switching means responsive to said mode signal for setting a pin terminal either to an input terminal for receiving said external refresh mode signal or to an output terminal for supplying a busy signal indicating that the self-refresh mode operation is carried out.

23. A semiconductor memory device according to claim 22, wherein

said self refresh means includes request means responsive to said mode signal indicting the self-refresh mode for generating a refresh request signal at the predetermined intervals, and activating means responsive to said refresh request signal for activating said refresh address generating means, and wherein said input/output switching means includes means responsive to said mode signal indicating the self-refreshing for transferring said refresh request signal as said busy signal to said pin terminal.

24. A semiconductor memory device according to claim 1, further comprising:

row address control means responsive to a DRAM array access indicating signal and a clock signal for generating a row address latch signal at a first leading edge of said clock signal;

column address control means responsive to the clock signal and said row address latch signal for generating a column address latch signal at one of transition edges of the clock signal subsequent to said first leading edge;

first latch means responsive to said row address latch signal for latching an external address to generate internal row address signal; and

second latch means responsive to said column address latch signal for latching an external address to generate an internal column address.

25. A semiconductor memory device according to claim 24, wherein

said column address control means includes means responsive to a trailing edge of the clock signal following said first leading edge to generate said column address latch signal.

26. A semiconductor memory device according to claim 24, wherein said column address control means includes means for generating a setting signal for setting a timing of latching an external address by said second latch means, and control means responsive to said setting signal and said row address latch signal to generate said column address latch signal at one of successive leading edges of the clock signal following the first leading edge.

27. A semiconductor memory device according to claim 24, further including resetting means responsive to said row address latch signal for resetting said row address control means after elapse of a predetermined time period since generation of said row address latch signal.

28. A semiconductor memory device according to claim 1, further comprising:

first address input means receiving a first address through a first address input for generating a first internal address;

second address input means receiving a second address through a second address input for generating a second interval address;

third address input means receiving a third address input for generating a third internal address;

said second address input provided separately from said third address input and receiving an address simultaneously with said third address input;

first selection means responsive to said first and second internal address for generating a first select signal for selecting a memory of the SRAM array;

second selection means responsive to said second and third internal address for generating a second select signal for selecting a memory cell of said DRAM array; and

decision means responsive to an access indicating signal for deciding which of the first and second selection means receives the second internal address.

29. A semiconductor memory device according to claim 28, wherein said first selection means includes SRAM row selection means responsive to said second internal address for generating a SRAM row select signal for selecting a row of memory cells of the SRAM array, and SRAM column selection means responsive to said first internal address for generating a SRAM column select signal for selecting a column of memory cells of said SRAM array, and said second selection means includes DRAM row selection means responsive to said third internal address for generating a DRAM row select signal for selecting a row of memory cells of the DRAM array, and DRAM column select signal responsive to the second internal address for generating a DRAM column select signal for selecting a column of memory cells of the DRAM array.

30. A semiconductor memory device according to claim 29, wherein said SRAM row selection means includes predecode means responsive to said second internal address for generating a predecoded signal of the second internal address, and decoder means responsive to said predecode signal for generating said SRAM row select signal, and wherein

said decision means is provided between said predecode means and said decoder means.

31. A semiconductor memory device according to claim 29, wherein said decision means is provided between an output of said SRAM row selection means and an input of said DRAM column selection means.

32. A semiconductor memory device according to claim 30, wherein said DRAM column select means receives a part of said second internal address to generate a DRAM column select signal for selecting a plurality of columns of memory cells of the DRAM array, and said SRAM column selection means selects a column among selected plurality of codes of memory cells.

33. A semiconductor memory device according to claim 1, further comprising:

SRAM clamping means provided for each said column of said SRAM array and for clamping a potential of an associated column of said SRAM array; and

control means for activating said data transfer means to transfer data from said DRAM array to said SRAM array while disabling said clamping means to inhibit the clamping operation thereof, in response to an instruction for data transfer from said DRAM array to SRAM array.

34. A semiconductor memory device according to claim 1, further including:

a data transfer bus for coupling a selected memory cell in said DRAM array to said data transfer means;

clamping means for claming a potential of said data transfer bus; and

control means responsive to an instruction of data transfer from said SRAM array to DRAM array, for enabling said data transfer means for data transfer from said SRAM array to said DRAM array while disabling and clamping means to inhibit the clamping operation thereof.

35. A semiconductor memory device according to claim 4, wherein said DRAM array includes a plurality of data transmission lines, one for each transfer gate means, for transferring data between the transfer gate means and selected memory cells of DRAM array, and wherein each said transfer gate means includes first means coupled to receive and amplify potentials on associated n pairs of bit lines of SRAM array, second means for latching an output of said first means, third means responsive to a first control signal for transferring data latched in said second means to an associated data transmission line, fourth means coupled to receive and amplify a potential on the associated data transmission line, and fifth means in response to a second control signal and a group designating signal for selecting one of associated n pairs of bit lines and transferring an output of said fourth means to the selected pair of bit lines.

36. A semiconductor memory device, comprising:

a first memory cell array including a plurality of memory cells arranged in a matrix of rows and columns;

a second memory cell array including a plurality of memory cells arranged in a matrix of rows and columns;

a first row address input terminal for receiving a first row address for designating a row of said first memory cell array;

a first column address input terminal provided separate from said first row address input terminal for receiving a first column address for designating a column of said first memory cell array;

a second row address input terminal for receiving a second row address for designating a row of said second memory cell array;

a second column address input terminal provided separate from said second row address input terminal for receiving a second column address for designating a column of said second memory cell array; wherein

a part of said first column address input terminal is commonly used with said second row address input terminal and said second column address input terminal.

37. A semiconductor memory device, comprising:

a DRAM array including a plurality of dynamic memory cells arranged in rows and columns;

an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns, static memory cells on a row being arranged in a line, each row divided into n groups of codes, said SRAM array including a plurality of sets of word lines provided corresponding to the rows of said SRAM array, a different word line in each set being connected to said static memory cells of a different group, each of the sets of the n word lines being arranged corresponding to each row of said SRAM array and in parallel with a corresponding row of said SRAM array; and

data transfer means provided between said DRAM array and said SRAM array for transferring data between a selected memory cell of said DRAM array and a selected memory cell of said SRAM array.

38. A semiconductor memory device, comprising:

a DRAM array including a plurality of dynamic memory cells arranged in rows and columns;

an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns, each row divided into n groups of static memory cells, said SRAM array including a plurality of sets of immediately adjacent n word lines each connected to static memory cells of a different group, each set of word lines arranged corresponding to each row of said SRAM array and in parallel with a corresponding row of SRAM array, and static memory cells on a row arranged in a line; and

data transfer means provided between said DRAM array and said SRAM array for transferring data between a selected memory cell of said DRAM array and a selected memory cell of said SRAM array.