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Description  |
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FIELD OF THE INVENTION
This invention relates to memory device architectures designed to provide high density data storage with high speed read and write access cycles. This invention relates more specifically to memory data read circuitry for burst access memory
devices.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory devices (DRAMs) are among the highest volume and most complex integrated circuits manufactured today. Except for their high volume production, the state of the art manufacturing requirements of these devices would
cause them to be exorbitantly priced. Yet, due to efficiencies associated with high volume production, the price per bit of these memory devices is continually declining. The low cost of memory has fueled the growth and development of the personal
computer. As personal computers have become more advanced, they in turn have required faster and more dense memory devices, but with the same low cost of the standard DRAM. Fast page mode DRAMs are the most popular standard DRAM today. In fast page
mode operation, a row address strobe (/RAS) is used to latch a row address portion of a multiplexed DRAM address. Multiple occurrences of the column address strobe (/CAS) are then used to latch multiple column addresses to access data within the
selected row. On the falling edge of /CAS an address is latched, and the DRAM outputs are enabled. When /CAS transitions high the DRAM outputs are placed in a high impedance state (tri-state). With advances in the production of integrated circuits,
the internal circuitry of the DRAM operates faster than ever. This high speed circuitry has allowed for faster page mode cycle times. A problem exists in the reading of a DRAM when the device is operated with minimum fast page mode cycle times. /CAS
may be low for as little as 15 nanoseconds, and the data access time from /CAS to valid output data (tCAC) may be up to 15 nanoseconds; therefore, in a worst case scenario there is no time to latch the output data external to the memory device. For
devices that operate faster than the specifications require, the data may still only be valid for a few nanoseconds. On a heavily loaded microprocessor memory bus, trying to latch an asynchronous signal that is valid for only a few nanoseconds is very
difficult. Even providing a new address every 35 nanoseconds requires large address drivers which create significant amounts of electrical noise within the system. To increase the data throughput of a memory system, it has been common practice to place
multiple devices on a common bus. For example, two fast page mode DRAMs may be connected to common address and data buses. One DRAM stores data for odd addresses, and the other for even addresses. The /CAS signal for the odd addresses is mined off
(high) when the /CAS signal for the even addresses is mined on (low). This interleaved memory system provides data access at twice the rate of either device alone. If the first /CAS is low for 20 nanoseconds and then high for 20 nanoseconds while the
second /CAS goes low, data can be accessed every 20 nanoseconds or 50 megahertz. If the access time from /CAS to data valid is fifteen nanoseconds, the data will be valid for only five nanoseconds at the end of each 20 nanosecond period when both
devices are operating in fast page mode. As cycle times are shortened, the data valid period goes to zero.
There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM
architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not
tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low transition occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data
will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with
respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by the various DRAM manufacturers.
Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM) for example has an additional pin for receiving a
system clock signal. Since the system clock is connected to each SDRAM device in a memory system, it is highly loaded, and it is always toggling circuitry in every SDRAM. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin.
Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM.
The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM
devices which in turn result in higher device manufacturing costs.
In order for existing computer systems to use an improved device having a nonstandard pinout, those systems must be extensively modified. Additionally, existing computer system memory architectures are designed such that control and address
signals may not be able to switch at the frequencies required to operate the new memory device at high speed due to large capacitive loads on the signal lines. The Single In-Line Memory Module (SIMM) provides an example of what has become an industry
standard form of packaging memory in a computer system. On a SIMM, all address lines connect to all DRAMs. Further, the row address strobe (/RAS) and the write enable (/WE) are often connected to each DRAM on the SIMM. These lines inherently have high
capacitive loads as a result of the number of device inputs driven by them. SIMM devices also typically ground the output enable (/OE) pin making /OE a less attractive candidate for providing extended functionality to the memory devices.
There is a great degree of resistance to any proposed deviations from the standard SIMM design due to the vast number of computers which use SIMMs. Industry's resistance to radical deviations from the standard, and the inability of current
systems to accommodate the new memory devices will delay their widespread acceptance. Therefore only limited quantities of devices with radically different architectures will be manufactured initially. This limited manufacture prevents the reduction in
cost which typically can be accomplished through the manufacturing improvements and efficiencies associated with a high volume product.
SUMMARY OF THE INVENTION
An integrated circuit memory device with a standard DRAM pinout is designed for high speed data access and for compatibility with existing memory systems. A high speed burst mode of operation is provided where multiple sequential accesses occur
following a single column address, and data is input and output relative to the /CAS control signal. In the burst mode of operation the address is incremented internal to the device eliminating the need for external address lines to switch at high
frequencies. Read /Write commands are issued once per burst access eliminating the need to toggle the Read /Write control line at high speeds. Only one control line per memory chip (/CAS) must toggle at the operating frequency in order to clock the
internal address counter and the data input/output latches. The load on each /CAS is typically less than the load on the other control signals (/RAS, /WE and /OE) since each /CAS typically controls only a byte width of the data bus. A data output
buffer has a two stage pipeline mode of operation which allows for further speed increases by latching read data in an intermediate data latch, and allowing internal read signals to precharge prior to latching the data in an output latch and driving the
data from the part. Internal circuitry of the memory device is largely compatible with existing Extended Data Out (EDO) DRAMs. This similarity allows the two part types to be manufactured on one die with a limited amount of additional circuitry. The
ability to switch between a standard non-burst mode and a high speed burst mode allows the device to be used to replace standard devices, and eliminates the need to switch to more complex high speed memory devices. Internal address generation with a
pipelined data output provides for faster data access times than is possible with either fast page mode or EDO DRAMs. This high speed operation eliminates the need to interleave memory devices in order to attain a high data throughput. In contrast to
the 50 megahertz interleaved memory system described above, the output data from this device will be valid for approximately 15 nanoseconds significantly easing the design of circuitry required to latch the data from the memory. Operating frequencies
significantly higher than 50 megahertz are possible with this architecture due to internal address generation, pipelined read circuitry, an extended valid data output period, and a single lightly loaded control signal operating at the operating frequency
or one half of the operating frequency. The device is compatible with existing memory module pinouts including Single In-Line Memory Module (SIMM), Multi-Chip Module (MCM) and Dual In-Line Memory Module (DIMM) designs. This combination of features
allows for significant system performance improvements with a minimum of design alterations.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention as well as objects and advantages will be best understood by reference to the appended claims, detailed description of particular embodiments and accompanying drawings where:
FIG. 1 is an electrical schematic diagram of a memory device in accordance with one embodiment of the invention;
FIG. 2 is a timing diagram for a method of accessing the device of FIG. 1;
FIG. 3 is an electrical schematic diagram of an output buffer circuit in accordance with the teachings of the present invention;
FIG. 4 is a schematic diagram of a specific embodiment of the output buffer circuit of FIG. 3;
FIG. 5 is a timing diagram of the operation of the circuit of FIG. 4; and
FIG. 6 is a schematic diagram of a microprocessor system in accordance with the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a schematic representation of a sixteen megabit device designed in accordance with the present invention. The device is organized as a 2 Meg.times.8 burst EDO DRAM having an eight bit data input/output path 10 providing data storage
for 2,097,152 bytes of information in the memory array 12. The device of FIG. 1 has an industry standard pinout for eight bit wide EDO DRAMs. An active-low row address strobe (/RAS) signal 14 is used to latch a first portion of a multiplexed memory
address, from address inputs A0 through A10 16, in latch 18. For the purposes of this specification, the term input may be, but is not limited to, an input signal or a point in a circuit for receiving an input signal. The latched row address 20 is
decoded in row decoder 22. The decoded row address is used to select a row of the memory array 12. A column address strobe (/CAS) signal 24 is used to latch a second portion of a memory address from address inputs 16 into column address counter 26.
The latched column address 28 is decoded in column address decoder 30. The decoded column address is used to select a column of the memory array 12.
In a burst read cycle, data within the memory array located at the row and column address selected by the row and column address decoders is read out of the memory array and sent along data path 32 to output latches 34. Data 10 driven from the
burst EDO DRAM may be latched external to the device in synchronization with /CAS after a predetermined number of /CAS cycle delays (latency). For a two cycle latency design, a first /CAS falling edge is used to latch an initial address for a burst
access. The first burst data from the memory is latched in an intermediate latch shortly after it becomes valid on internal data lines. The data from the intermediate data latch is then latched in the output latch and driven from the memory after the
second /CAS failing edge, and remains valid through the third /CAS falling edge. Latching the data in an intermediate latch allows for access cycles to begin immediately after each /CAS low transition. Once the memory device begins to output data in a
burst read cycle, the output drivers 34 will continue to drive the data lines without tri-stating the data outputs during /CAS high intervals dependent on the state of the output enable and write enable (/OE and /WE) control lines, thus allowing
additional time for the system to latch the output data. Once a row and a column address are selected, additional transitions of the /CAS signal are used to advance the column address within the column address counter in a predetermined sequence. The
time at which data will be valid at the outputs of the burst EDO DRAM is dependent only on the timing of the /CAS signal provided that /OE is maintained low, and /WE remains high. The output data signal levels may be driven in accordance with standard
CMOS, TTL, LVTTL, GTL, or HSTL output level specifications.
The address may be advanced linearly, or in an interleaved fashion for maximum compatibility with the overall system requirements. The column address may be advanced with each /CAS transition, each pulse, or multiple of /CAS pulses in the event
that more than one data word is read from the array with each column address. When the address is advanced with each transition of the /CAS signal, data is also latched in the intermediate latch, latched in the output latch and driven from the part
after each /CAS transition. In this case, the device latency is referenced to each edge of the /CAS signal. This allows for a burst access cycle where the highest switching control line (/CAS) toggles only once (high to low or low to high) for each
memory cycle. This is in contrast to standard DRAMs which require /CAS to go low and then high for each cycle, and synchronous DRAMs which require a full clock cycle (high and low transitions) for each memory cycle. For maximum compatibility with
existing EDO DRAM devices, the invention will be further described in reference to a device designed to latch and advance a column address on falling edges of the /CAS signal.
It may be desirable to latch and increment the column address after the first /CAS falling edge in order to apply both the latched and incremented addresses to the array at the earliest opportunity in an access cycle. For example, a device may
be designed to access two data words per cycle (prefetch architecture). The memory array for a prefetch architecture device may be split into odd and even array halves. The column address least significant bit is then used to select between odd and
even halves while the other column address bits select a column within each of the array halves. In an interleaved access mode with column address 1, data from columns 0 and 1 would be read and the data from column 1 would be output followed by the data
from column 0 in accordance with standard interleaved addressing as described in SDRAM specifications. In a linear access mode column address 1 would be applied to the odd array half, and incremented to address 2 for accessing the even array half to
fulfill the two word access. One method of implementing this type of device architecture is to provide a column address incrementing circuit between the column address counter and the even array half. The incrementing circuit would increment the column
address only if the initial column address in a burst access cycle is odd, and the address mode is linear. Otherwise the incrementing circuit would pass the column address unaltered. For a design using a prefetch of two data accesses per cycle, the
column address would be advanced once for every two active edges of the /CAS signal. Read data is latched in the intermediate latch, and a multiplexer is placed between multiple intermediate latches and an output latch to provide data to the output
latch in the proper sequence. Prefetch architectures where more than two data words are accessed are also possible.
In the burst access memory device, each new column address from the column address counter is decoded and is used to access additional data within the memory array without the requirement of additional column addresses being specified on the
address inputs 16. This burst sequence of data will continue for each /CAS falling edge until a predetermined number of data accesses equal to the burst length has occurred. A /CAS falling edge received after the last burst address has been generated
will latch another column address from the address inputs 16 and a new burst sequence will begin. Read data is latched in the output latch and driven from the device with each falling edge of /CAS after the first /CAS latency.
For a burst write cycle, data 10 is latched in input data latches 34. Data targeted at the first address specified by the row and column addresses is latched with the /CAS signal when the first column address is latched (write cycle data latency
is zero). Other write cycle data latency values are possible; however, for today's memory systems, zero is preferred. Additional input data words for storage at incremented column address locations are latched by /CAS on successive /CAS pulses. Input
data from the input latches 34 is passed along data path 32 to the memory array where it is stored at the location selected by the row and column address decoders. As in the burst read cycle previously described, a predetermined number of burst access
writes will occur without the requirement of additional column addresses being provided on the address lines 16. After the predetermined number of burst writes has occured, a subsequent /CAS pulse will latch a new beginning column address, and another
burst read or write access will begin.
The memory device of FIG. 1 may include the option of switching between burst EDO and standard EDO modes of operation. In this case, the write enable signal /WE 36 may be used at the row address latch time (/RAS falling, /CAS high) to determine
whether memory accesses for that row will be burst or page mode cycles. If /WE is low when /RAS falls, burst access cycles are selected. If /WE is high at /RAS falling, standard extended data out (EDO) page mode cycles are selected. Both the burst and
EDO page mode cycles allow for increased memory device operating frequencies by not requiting the data output drivers 34 to place the data lines 10 in a high impedance state between data read cycles while /RAS is low. DRAM control circuitry 38, in
addition to performing standard DRAM control functions, controls the I/O circuitry 34 and the column address counter/latch 26 in accordance with the mode selected by /WE when /RAS falls. For EDO page mode cycles, the intermediate data latch is bypassed
in the output buffer circuitry and data is latched directly in the output latch. In a burst mode only DRAM, or in a device designed with an alternate method of switching between burst and non-burst access cycles, the state of /WE when /RAS fails may be
used to switch between other possible modes of operation such as interleaved versus linear addressing modes.
The write enable signal is used in burst access cycles to select read or write burst accesses when the initial column address for a burst cycle is latched by /CAS. /WE low at the column address latch time selects a burst write access. /WE high
at the column address latch time selects a burst read access. The level of the /WE signal must remain high for read and low for write burst accesses throughout the burst access. A low to high transition within a burst write access will terminate the
burst access, preventing further writes from occurring. A high to low transition on /WE within a burst read access will likewise terminate the burst read access and will place the data output 10 in a high impedance state. Transitions of the /WE signal
may be locked out during critical timing periods within an access cycle in order to reduce the possibility of triggering a false write cycle. After the critical timing period the state of /WE will determine whether a burst access continues, is
initiated, or is terminated. Termination of a burst access resets the burst length counter and places the DRAM in a state to receive another burst access command. Both /RAS and /CAS going high during a burst access will also terminate the burst access
cycle placing the data drivers in a high impedance output state, and resetting the burst length counter. Read data may remain valid at the device outputs if /RAS alone goes high while /CAS is active for compatibility with hidden refresh cycles,
otherwise /RAS high alone may be used to terminate a burst access. A minimum write enable pulse width is only required when it is desired to terminate a burst read and then begin another burst read, or terminate a burst write prior to performing another
burst write with a minimum delay between burst accesses. In the case of burst reads, /WE will transition from high to low to terminate a first burst read, and then /WE will transition back high prior to the next falling edge of /CAS in order to specify
a new burst read cycle. For burst writes, /WE would transition high to terminate a current burst write access, then back low prior to the next falling edge of /CAS to initiate another burst write access.
A basic implementation of the device of FIG. 1 may include a fixed burst length of 4, a fixed /CAS latency of 2 and a fixed interleaved sequence of burst addresses. This basic implementation requires very little additional circuitry to the
standard EDO page mode DRAM, and may be mass produced to provide the functions of both the standard EDO page mode and burst EDO DRAMs. This device also allows for the output enable pin (/OE) to be grounded for compatibility with many SIMM module
designs. When not disabled (tied to ground), /OE is an asynchronous control which will prevent data from being driven from the part in a read cycle if it is inactive (high) prior to /CAS falling and remains inactive beyond CAS rising. If these setup
and hold conditions are not met, then the read data may be driven for a portion of the read cycle. It is possible to synchronize the /OE signal with /CAS, however this would typically increase the /CAS to data valid delay time and doesn't allow for the
read data to be disabled prior to /RAS high without an additional /CAS low pulse which would otherwise be unnecessary. In a preferred embodiment, if /OE transitions high at any time during a read cycle the outputs will remain in a high impedance state
until the next falling edge of /CAS despite further transitions of the /OE signal.
Programmability of the burst length, /CAS latency and address sequences may be accomplished through the use of a mode register 40 which latches the state of one or more of the address input signals 16 or data signals 10 upon receipt of a
write-/CAS-before-/RAS (WCBR) programming cycle. In such a device, outputs 44 from the mode register control the required circuits on the DRAM. Burst length options of 2, 4, 8 and full page as well as /CAS latencies of 1, 2 and 3 may be provided. For
a latency of 1, the intermediate data latch is bypassed. For a latency of 3, an additional pipeline stage may be added. It may be desirable to place this additional pipeline stage in the address path, or in the read data path between the memory array
and the first intermediate data latch. Other burst length and latency options may be provided as the operating speeds of the device increase, and computer architectures evolve. The device of FIG. 1 includes programmability of the address sequence by
latching the state of the least significant address bit during a WCBR cycle. The burst length and /CAS latency for this particular embodiment are fixed. Other possible alterations in the feature sets of this DRAM include having a fixed burst mode only,
selecting between standard fast page mode (non-EDO) and burst mode, and using the output enable pin (/OE) 42 in combination with /RAS to select between modes of operation. Also, a WCBR refresh cycle could be used to select the mode of operation rather
than a control signal in combination with /RAS. A more complex memory device may provide additional modes of operation such as switching between fast page mode, EDO page mode, static column mode and burst operation through the use of various
combinations of /WE and /OE at /RAS falling time. One mode from a similar set of modes may be selected through the use of a WCBR cycle using multiple address or data lines to encode the desired mode. Alternately, a device with multiple modes of
operation may have wire bond locations, or programmable fuses which may be used to program the mode of operation of the device.
A preferred embodiment of a sixteen bit wide burst EDO mode DRAM designed in accordance with the teachings of this invention has two column address strobe input pins /CASH and /CASL. For read cycles only one /CAS signal needs to toggle. The
second /CAS may remain high or toggle with the other /CAS. During burst read cycles, all sixteen data bits will be driven out of part during a read cycle even if one /CAS remains inactive. In a typical system application, a microprocessor reads all
data bits on a data bus in each read cycle, but may only write certain bytes of data in a write cycle. Allowing one of the /CAS control signals to remain static during read cycles helps to reduce overall power consumption and noise within the system.
For burst write access cycles, each of the /CAS signals (CASH and /CASL) acts as a write enable for an eight bit width of the data. The two /CAS's are combined in an AND function to provide a single internal /CAS which will go low when the first
external /CAS falls, and returns high after the last external /CAS goes high. All sixteen data inputs are latched when the first of the /CAS signals transitions low. If only one /CAS signal transitions low, then the eight bits of data associated with
the /CAS that remained high are not stored in the memory.
The present invention has been described with reference to several preferred embodiments. Just as fast page mode DRAMs and EDO DRAMs are available in numerous configurations including x1, x4, x8 and x16 data widths, and 1 Megabit, 4 Megabit, 16
Megabit and 64 Megabit densities; the memory device of the present invention may take the form of many different memory organizations. It is believed that one who is skilled in the art of integrated circuit memory design can, with the aide of this
specification design a variety of memory devices which do not depart from the spirit of this invention. It is therefore believed that detailed descriptions of the various memory device organizations applicable to this invention are not necessary.
It should be noted that the pinout for | | |
