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Analog signal sampling circuit constructed with field-effect transistors
 
   
Document Number
US Patent 5654709
Issued Date
August 5, 1997
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Abstract
The present invention is intended to realize an analog signal sampling circuit constructed with field-effect transistors wherein errors caused by parasitic capacitance or gate conductance in a switch device is reduced. The sampling circuit of the invention comprises an inverting amplifier, a capacitor, a first switch for selecting a reference voltage Vref or a target signal Vin for input to the capacitor, and a second switch for opening or closing the connection between the input and output of the inverting amplifier, and produces an output in proportion to the difference between the target signal Vin and reference voltage Vref held in the capacitor, the sampling circuit being characterized by the inclusion of a voltage converting circuit whereby the operating voltage of the clock signal applied to the gate of the field-effect transistor forming the second switch is converted to a voltage related to the self-bias level of the inverting amplifier.
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Analog signal sampling circuit constructed with field-effect transistors - US Patent 5654709 Drawing
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Number of Claims:
15
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Owner
Fujitsu Limited (Kawasaki,JP)
Published
August 5, 1997
Application Number
08/252,094
Filed
May 31, 1994
US Classification
341/122  
Int'l Classification
H03M   1/34   (20060101)  
Assistant Examiner
Attorney/Law Firm
Priority Data
Aug 30, 1993 [JP] 5-214483
USPTO Field of Search
341/122  
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