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BRIEF DESCRIPTION OF THE INVENTION
This invention relates to the testing of electrical devices and, more
particularly, to the testing of nonpackaged integrated circuit dice.
BACKGROUND OF THE INVENTION
An integrated circuit die is subject to a series of tests to ensure that it
can operate within the desired parameters. A die which passes these tests
is referred to as a known good die (KGD). Dice are manufactured in lots on
wafers. Each die is initially probe tested while still on the wafer. Wafer
level testing is usually limited to testing for continuity and resistance
and sometimes for capacitance and/or inductance. The die typically cannot
be statically or dynamically tested under environmental conditions while
still on the wafer. Difficulties with access and thermal expansion have
presented problems in providing power, ground and signals into and out of
a die in the middle of a wafer. For example, testing of a die under power
while still on the wafer can cause thermal damage to the other dice on the
wafer. As a result, most dice are not further tested prior to sorting.
Preferably, a die sliced from the wafer which has passed the probe test is
thereafter subject to environmental functional and climatic burn-in
testing to make certain that it operates properly under conditions which
approximate the worst that it can expect to experience during use.
The burn-in tests involve pre-exposing the dice to anticipated functional
and climatic environmental conditions so as to sort out infant mortality
and marginal responsive chips. The scope and exposure can include testing
for any or all of temperature, time or voltage. Temperature testing can
include testing the chip at low (down to -65 degrees Centigrade), ambient
(approximately 20 degrees Centigrade) and/or high (up to 175 degrees
Centigrade) temperatures. Testing for time can include on-off testing
and/or duration testing, for example 24, 48 or 168 hours. Voltage testing
can include zero or continuity testing, static testing for power, ground
and/or signal levels, dynamic testing for partial or full range
performance and testing at greater than specification levels for
accelerated stress. In this regard, typical die may be subjected to shock
forces, biasing, continuity checks, voltage signal cycling, power surges
and high-current thermal shock during burn-in testing.
Currently, most dice are mounted to a package to permit electrical access
to the individual die. Although the package can have many different
designs, a first level package such as a lead frame package having one of
the several standard or conventional lead or pin configurations adopted by
the semiconductor industry is typically used. As a result, most test,
burn-in, transferring and handling equipment is designed to accommodate
only die packages having input and output leads or pins arranged in one of
these standard configurations. This standardization not only reduces
compatibility problems between packages and circuit boards, but also
between packages and test, burn-in, handling and transferring equipment. A
die mounted in a nonstandard die package or support structure typically
requires costly specialized machinery for testing, burn-in, transferring
and/or handling.
Standard single chip packages include the dual inline package (DIP), the
pin grid array package (PGA), the quad flat package (QFP), leaded chip
carrier, low lead count metal can package, small outline integrated
circuit package (SOIC), ball grid array package (BGA) and metal pin grid
array package (MQUAD). The dual inline and pin grid array packages are
through hole packages having pins or leads for mounting in a socket or
hole in the second level package; the quad flat package is a surface
mounted package having leads or pads meant for surface mounting to the
second level package.
Mounting a die within a package typically involves attaching the die within
a socket formed in the package by die bonding with a suitable medium such
as epoxy or filled polymer. The interconnect or wire bond pads of the die
are electrically connected to the package leads with electrical
interconnects permanently attached to the wire bond pads such as by wire
bonding, lead bonding or soldering. A lid is usually mounted, often by
soldering, over the socket once the die has been attached therein. Once
burn-in has been completed, the lid is desoldered to permit access to the
die. If the die does not perform properly under the burn-in tests, the die
and package are usually discarded. Although methods exist for salvaging
packages for reuse, these methods have not usually proven cost effective.
Apparatus or fixtures have been provided for performing burn-in testing on
discrete nonpackaged dice. Some of these fixtures are designed to make
electrical connections With the integrated circuit of the dice without
forming a permanent connection to the wire bond pads. For example, see the
apparatus disclosed in U.S. Pat. No. 4,899,107. These apparatus and
fixtures, however, have a variety of disadvantageous. For example, the
nonstandard test apparatus disclosed in U.S. Pat. No. 4,899,107 requires
specialized machinery for use therewith and has not proven altogether
satisfactory in operation. In addition, low force nonpermanent connections
to wire bond pads have been found to be difficult by the fact that most
bond pads cannot withstand a large pressure thereon without disfiguring
the bond pad surface so as to impair subsequent wire bonding or without
causing subsurface metallization damage.
Other test fixtures require that deleterious bonds of a permanent nature be
made to the interconnect pads, or have proven too complicated to
manufacture and/or operate. Still other fixtures have been designed for
the burn-in testing of dice and include probes and leads etched from one
or more films or layers of conductive material deposited onto an
elastomeric layer or film mounted to a rigid support plate or other
structure. The probes are pressed against the wire bond pads of the die to
establish electrical contact with the die to permit testing thereof. These
fixtures suffer from difficulties in piercing through the aluminum oxide
layer on aluminum wire bond pads to establish electrical contact therewith
and excessive loads exerted on the wire bond pads. Similar fixtures
suffering from similar disadvantages have probes mounted to a first
structure which is compliantly mounted to a second structure.
Certain integrated circuit dice, such as flip chips, are designed for
direct placement on a circuit board, substrate or other first or second
level package. The interconnect pads on flip chips are aligned on one
surface so as to mate with the bond pads on the substrate or circuit board
when the chip is flipped over and placed face down. The interconnect pads
on the chip or die consist of bond pads provided with drops of solder
known as solder bumps which serve to bond the die and substrate pads
together.
As with other chips having conventional bond pads, it has proven difficult
to make effective electrical contact with a flip chip in an isolated
environment, that is apart from a circuit board. Among other things, this
is due to the fact that the tolerances for solder bumps are not as small
as those for conventional wire bond pads. For these and other reasons,
burn-in tests are typically not performed on flip chips. As can be
appreciated, the inability to economically and effectively burn-in test
flip chips can increase the percentage of defective chips shipped.
OBJECTS AND SUMMARY OF THE INVENTION
In general, it is an object of the present invention to provide a method
for performing burn-in tests on a nonpackaged integrated circuit die which
utilizes, for the most part, conventional and available testers, handlers
and materials.
Another object of the invention is to provide a damage-free method such as
described above for testing an integrated circuit die without forming a
permanent connection with the interconnect pads of the die.
Another object of the invention is to provide a method such as described
above for testing an integrated circuit die having 20 to 1,000 or more
interconnect pads disposed on the surface thereof.
Another object of the invention is to provide a method such as described
above for testing flip chips having interconnect pads which include solder
bumps.
Another object of the invention is to provide a fixture for use with the
method described above which utilizes a package compatible with commercial
test, burn-in and handling equipment for conventional integrated circuit
packages.
Another object of the invention is to provide a fixture of the above
character which utilizes a conventional or industry standard package
assembly having the usual envelope and commercial standard electrical
access. Another object of the invention is to provide a fixture of the
above character in which a controlled low pressure contact is made
independently with each interconnect pad when establishing electrical
contact therewith.
Another object of the invention is to provide a fixture of the above
character in which the pressure exerted-on the interconnect pads is not
deleterious to the integrated circuit die or subsequent interconnection
operations, but leaves a small witness mark on the interconnect pad as
evidence that the die has undergone testing and/or burn-in.
Another object of the invention is to provide a fixture of the above
character in which the pressure exerted on each of the interconnect pads
is substantially equal.
Another object of the invention is to provide a fixture of the above
character in which the electrical contact with the interconnect pads is
maintained should the die expand during thermal testing.
These and other objects are achieved in accordance with the invention by
providing a method for testing an integrated circuit die in a package. The
die has interconnect pads which permit making electrical connections with
the die, and the package has leads which permit making electrical
connections with the package and are in a configuration compatible with
test, burn-in and handling equipment. The method includes the steps of
placing the interconnect pads in direct contact with the leads of the
package without forming a permanent connection to the interconnect pads,
conducting burn-in tests on the die while the interconnect pads are in
direct contact with the leads of the package, electrically testing the
integrated circuit of the die to ascertain whether predetermined
electrical parameters are met and disconnecting the interconnect pads from
the leads of the package. In a preferred approach, the die is placed in
the package and a pressure contact is made with each of the interconnect
pads to permit directly connecting them to the leads of the package.
A fixture is provided for making temporary electrical connections with an
integrated circuit die to permit electrical testing of various parameters
of the circuitry of the integrated circuit. The die has interconnect pads
arranged in a predetermined pattern. The fixture includes a substantially
rigid support member and contact elements carried thereby. The contact
elements are adapted to engage a single die and have a pattern
corresponding to the predetermined pattern of interconnect pads.
Engagement means is provided for bringing the interconnect pads and the
contact elements carried by the support member together into engagement
and registration to make nonpermanent temporary simultaneous electrical
connections therebetween. The engagement means includes a package having
leads which permit making electrical connections with the package and are
in a configuration compatible with test, burn-in and handling equipment
for conventional integrated circuit packages. The fixture further includes
lead means connected to the contact elements carried by the support member
and making electrical contact with the leads of the package.
In the preferred embodiments, a yieldable material at least partially
encapsulates the contact elements and, by doing so, exerts a substantially
equal pressure on the contact elements and thus the interconnect pads and
accommodates irregularities in the elevations of the interconnect pads. In
one embodiment, a plate member having a thermal coefficient-of expansion
which approximates the thermal coefficient of expansion of the die is
carried by the support member. The plate member has first and second
opposite surfaces and is provided with a plurality of bores extending
therethrough. The contact elements are slidably disposed in the bores.
Registration retention means is carried by the support member and the
plate member for retaining the contact elements in registration with the
interconnect pads should the die expand during thermal testing.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an isometric view of the assembly for testing integrated circuit
die of the present invention.
FIG. 2 is an exploded isometric view of the testing assembly of FIG. 1
shown with an integrated circuit die.
FIG. 3 is a cross-sectional view taken along the line 3--3 of FIG. 1.
FIG. 4 is an enlarged cross-sectional view taken along the line 4--4 of
FIG. 3.
FIG. 5 is a cross-sectional view taken along the line 5--5 of FIG. 1.
FIG. 6 is an enlarged isometric view, partially cut away, taken along the
line 6--6 of FIG. 2.
FIG. 7 is a bottom plan view, partially cut away, taken along the line 7--7
of FIG. 2.
FIG. 8 is a cross-sectional view taken along the line 8--8 of FIG. 7 and
rotated 180 degrees.
FIG. 9 is a cross-sectional view taken along the line 9--9 of FIG. 7 and
rotated 180 degrees.
FIG. 10 is an isometric view, partially cut away, of another embodiment of
the assembly for testing integrated circuit die of the present invention.
FIG. 11 is a cross-sectional view taken along the line 11--11 of FIG. 10.
FIG. 12 is a cross-sectional view taken along the line 12--12 of FIG. 10.
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the preferred embodiments of the
invention, which are illustrated in the accompanying figures. Turning now
to the drawings, wherein like components are designated by like reference
numerals throughout the various figures, attention is first directed to
FIGS. 1 through 9 where one embodiment of the apparatus and method of the
present invention for testing non-packaged integrated circuit die is
shown.
A fixture 21 of the present invention is designed for making temporary
electrical connections with an integrated circuit die 22 to permit
electrical testing of various parameters of the circuitry of the
integrated circuit in the die. Die 22 is of a conventional type, being
made from silicon or other semiconductor material and having opposite and
generally planar top and bottom surfaces 23 and 26. Top surface 23 of die
22 has a plurality of interconnect pads or wire bond pads 27 arranged in a
predetermined pattern or array along two opposite sides of the die which
permit making electrical connections with the integrated circuit of die
22. Wire bond pads 27 can vary in elevational height with respect to top
surface 23 from one to 25 microns.
Fixture 21 is provided with a cover or electrical bridge apparatus or
assembly 31 which overlies die 22 and includes a substantially rigid and
flat support member or lid 32 made of any suitable material, such as
ceramic or alloy 42 metal, having a coefficient of expansion generally
matching that of silicon. Lid 32 is generally rectangular when viewed in
plan as in FIG. 2, having generally parallel and planar opposite first or
bottom and second or top surfaces 33 and 34, opposite and parallel first
and second ends 37 and 38 and opposite and parallel first and second sides
41 and 42. Two diagonally disposed bores 43 extend generally
perpendicularly through surfaces 33 and 34 at opposite corners formed by
adjoining side and end 42 and 37 and adjoining side 41 and end 38 and have
elongate registration means or pins 46, each having a generally circular
cross-section, press fit or otherwise snugly and permanently disposed
therein. Registration pins 46 are generally flush with lid top surface 34
and extend from bottom surface 33 as illustrated in FIGS. 2, 3, 5 and 7.
Contact elements or pins 51 made of gold plated stainless steel or any
other suitable material are carried by lid bottom surface 33 and are
adapted to engage wire bond pads 27 for making electrical connections to
the integrated circuit on die 22 (See FIG. 3). Pins 51 are generally
circular in cross-section, having a butt first or top end 52 and tapering
toward a rounded second or bottom end 53 (See FIGS. 8 and 9). Means for
mounting pins 51 to lid 32 includes a suitable polymer 56 such as silicone
which serves as a yieldably elastic flexible adhesive material or jelly
and is disposed evenly across lid bottom surface 33 in several layers. A
pattern interconnect 57 is embedded in polymer 56 and serves as means for
arranging contact pins 51 on lid bottom surface 33 in a pattern
corresponding to the predetermined pattern of wire bond pads 27 on die top
surface 23.
Pattern interconnect 57 is a very thin and flexible sheet made of any
suitable material such as gold-plated copper or alloy 42. The patterned
interconnect is generally elongate and rectangular in shape when viewed in
plan with first and second end portions 57a and 57b and opposite and
generally parallel first or top and second or bottom surfaces 58 and 61
(See FIGS. 7 through 9). A set of thin elongate strip elements or
temporary jumper connections 62 are formed in each of end portions 57a and
57b. Jumper connections 62 are generally longitudinally aligned with
pattern interconnect sides 41 and 42, being spaced-apart across pattern
interconnect 57 in juxtaposition with each other and separated by elongate
electrical disconnect slots 63 extending through top and bottom surfaces
58 and 61. The jumper connections are joined at each end to the remainder
of pattern interconnect 57 by thin connectors 66, and are provided with
sets of first or inner and second or outer bores 67 and 68 extending
therethrough between surfaces 58 and 61. At least one inner bore 67 and
outer bore 68 is provided in each jumper connection 62. Inner bores 67 are
arranged in a pattern which extends generally linearly across pattern
interconnect 57 and corresponds to the predetermined pattern of wire bond
pads 27 on die 22. Outer bores 68, being farther from the center of
pattern interconnect 57 than inner bores 67, are also arranged in a
pattern which extends generally linearly across the pattern interconnect.
Inner bores 67 are designed for receiving contact pins 51 and outer bores
68 are designed for receiving a second set of contact elements or pins 71
which are substantially similar to contact pins 52 and have a butt first
or top end 72 and a rounded second or bottom end 73 (see FIG. 9).
Pattern interconnect 57 is further provided with first and second alignment
bores 76 and 77 extending through surfaces 58 and 61 and diagonally
disposed thereon in a pattern which generally conforms with the pattern of
registration pins 46 on lid 32. First alignment bore 76 is generally
circular in cross-section and second alignment bore 77 is generally oblong
shaped in cross-section, each such bore being configured and dimensioned
to receive a registration pin 46. In addition, pattern interconnect 57 is
provided with a pattern of securement bores 81 extending through top and
bottom surfaces 58 and 61 to assist in retaining the pattern interconnect
in polymer 56. The configuration of pattern interconnect 57, including
slots 63 and bores 67, 68, 76, 77 and 81, is formed by any suitable means
such as chemical etching or stamping.
For assembling cover assembly 31, contact pins 51 and 71 are mounted to
pattern interconnect 57 in respective inner and outer bores 67 and 68 by
any suitable means such as soldering with gold tin solder 83. Pins 51 and
71 are perpendicularly aligned with pattern interconnect surfaces 58 and
61, top ends 52 and 72 extending from top surface 58 and bottom ends 73
extending from bottom surface 61. Bottom ends 53 and 73 of pins 51 and 71
are elevationally aligned with respect to surfaces 58 and 61 within a
surface planarity of 0.0005 inches.
A first or bottom layer of polymer 56 is placed on and disposed across
pattern interconnect bottom surface 61, after which a second layer is
placed in slots 63 and securement bores 81. A third layer of polymer 56 is
placed on and disposed across pattern interconnect top surface 58. First
and second sets of holes 85 and 86 are provided in the bottom layer of
polymer 56. Contact pins 51 and 71 extend through first holes 85, while
second holes 86 provide access to connectors 66. Further holes are
provided for access to first and second alignment bores 76 and 77.
The laminate formed by polymer 56 with pattern interconnect 57 embedded
therein is mounted to lid 32. More specifically, a fourth thin layer or
film of polymer 56, not shown in the drawings, is applied atop the third
layer of polymer 56 and serves to bond pattern interconnect 57 to lid
bottom surface 33 with pattern interconnect top surface 58 facing lid
bottom surface 33. Registration pins 46 are received within alignment
bores 76 and 77 to ensure proper alignment of pattern interconnect 57 and
lid 32, with the oblong configuration of second alignment bore 77
accommodating the variations in placement of registration bores 43 on lid
32 and alignment bores 76 and 77 on pattern interconnect 57 within the
specified tolerances. Prior to mounting pattern interconnect 57 to lid 32,
connectors 66, accessible through second holes 86, are each punched to
sever and singulate temporary jumper connections 62 from the remainder of
the pattern interconnect. Connectors 66 are shown in the drawings,
specifically FIGS. 7 and 9, in their severed condition. As severed from
the remainder of pattern interconnect 57, jumper connections 62 are
carried by polymer 56 and serve as means for electrically connecting
contact pins 51 and 71.
Engagement means or assembly 90 is provided for bringing wire bond pads 27
and contact pins 51 together into accurate engagement and registration to
make nonpermanent temporary simultaneous electrical connections
therebetween. Engagement assembly 90 includes a conventional standardized
commercial chip package, such as dual inline package 91 shown in FIGS. 1
and 2, for receiving an integrated circuit die. Package 91 is formed from
a laminate housing 92 made from a suitable non-conductive material such as
ceramic and includes an integral conductive lead interconnect assembly 93
carried by housing 92 to permit making electrical contact with a die
mounted in the package. Housing 92 is generally in the form of a
parallelepiped, having opposite first or top and second or bottom surfaces
96 and 97 and opposite generally parallel and planar sides 98. Lead
interconnect assembly 93 includes an equal number of generally parallel
pins or lead strips 101 on each housing side 98 which permit making
electrical connections through chip package 91. Leads 101 are aligned in a
pattern so as to be spaced apart along sides 98 at substantially equal
intervals and extend downwardly therefrom in a direction substantially
perpendicular to housing bottom surface 97.
Housing 92 further includes a recess or socket 102 provided in the center
of top surface 96. A layer of vapor deposited gold 103, included within
lead interconnect assembly 93, has a surface which forms lower surface 106
of well or socket 102 and the floor of chip package 91. An integral
platform 107 is formed in housing 92 at each end of socket 102 below top
surface 96, each platform 107 having a plurality of contact elements or
bond pads 108 linearly spaced apart therealong. Each bond pad 108 is
electrically connected to a lead 91 by a conventional interconnect, not
shown in the drawings, vapor deposited onto a layer of ceramic and buried
within laminate ceramic housing 92. Bond pads 108 are each formed from a
strip of gold vapor deposited onto platform 107 of ceramic housing 92 and,
together with the related interconnects, comprise part of lead
interconnect assembly 93.
Engagement assembly 90 has a mounting assembly 116 for temporarily and
nonpermanently mounting die 22 within socket 102 as illustrated in FIGS. 3
through 5. Mounting assembly 116 comprises a button 117 made of gold
plated copper or any other suitable material and having a base portion
117a ultrasonically bonded to well lower surface or package floor 106.
Button 117 is further secured to package floor 106 by epoxy 118, and is
provided with a plurality of bores 121 spaced circumferentially around the
bottom thereof for increasing the surface area of button 117 and gold
layer 103 interconnected by the epoxy. Two bores 121 are shown in
cross-section in FIG. 4. Button 117 further includes a dome portion 117b
provided with a centrally disposed bore 122 extending longitudinally
therethrough.
A support structure or spring platform 126 for supporting die 22 on package
91 and made from a suitable material such as alloy 42 metal is also
included within mounting assembly 116. Yieldable elastic platform 126 is
generally rectangular when viewed in plan and is formed from a generally
planar base 127 with an elevated pad 128 at each end thereof. Pads 123
have top surfaces 131 which are generally coplanar. Base 127 has a dimple
132 formed in the center thereof for alignably positioning and mounting
platform 126 to button 117. A suitable quick-drying cyanoacrylate polymer
or anaerobic cement 133 such as "Loctite" is disposed between dimple 132,
which extends upwardly from base 127, and button 117. Cement 133 serves as
an initial means for attaching platform 126 to button 117 with pads 128
being generally parallel with package floor 106. Dimple 132 is provided
with a bore 137 therethrough, and a locking pin 138 made of any suitable
material such as brass extends through dimple and dome bores 137 and 122
for further securing spring platform 126 to button 117. Locking pin 138 is
retained in position by epoxy 141 disposed within button dome portion 117b
and epoxy 142 disposed on dimple 132.
Die 22 is mounted on platform 126 with die bottom surface 26 being
supported at each end by a platform pad 128. A suitable adhesive such as a
thin tacky layer 143 of any suitable liquid or polymer such as silicone,
water or vacuum oil, illustrated in FIG. 3, is placed on pad top surfaces
131 and temporarily grips die bottom surface 28 to restrict lateral
movement between die 22 and platform 126 until wire bond pads 27 are
engaged by bottom ends 53 of contact pins 51. As illustrated in FIG. 6,
platform pads 128 are each provided with bores 126 extending therethrough
and spaced thereacross to further limit such lateral movement and permit
tacky layer 143 of liquid or polymer to pass therethrough when cover
assembly 31 is mounted to chip package 91.
A frame 151 made of a suitable material such as alloy 42 metal is mounted
to housing top surface 96 and is included in the means for positioning and
aligning cover assembly 31 on chip package 91 (See FIG. 2). Frame 151 is
generally rectangular when viewed in plan, having opposite and generally
parallel first or top and second or bottom surfaces 152 and 153 and
provided with a central rectangular opening 156 therethrough. The frame is
provided with three threaded bores 157 extending through surfaces 152 and
153 which are adapted for engagement by handling and positioning
equipment, not shown in the drawings, to facilitate proper mounting and
positioning of frame 151 on chip package 91. Housing top surface 96 is
provided with a layer 158 of vapor deposited gold around the perimeter of
socket 102 and frame bottom surface 153 is attached to gold layer 158 by
any suitable means such as gold tin solder 161. Frame 151 is mounted and
attached to chip package 91 so that frame opening 156 is generally aligned
about and not overlapping socket 102, and frame top surface 152 is
generally parallel to package floor 106.
Frame 151 is further provided with two countersinks 162 extending through
bottom surface 153 and two corresponding registration bores 163 extending
through top surface 152 and opening into countersinks 162 (See FIGS. 1 and
5). Among other things, countersinks 162 provide a suitable area into
which excess solder 161 will be restricted in registration bores 163
during attachment of frame 151 to chip package 91. Registration bores 163
are aligned on frame 151 in a precise pattern corresponding to the pattern
of registration pins 46 on lid bottom surface 33, and registration pins
and bores 46 and 163 are included within the means for aligning lid 32
with frame 151 and chip package 91.
Engagement assembly 90 also includes means for leveling and elevationally
positioning lid 32 with respect to frame 151 and chip package 91. In this
regard, lid 32 is provided with three countersinks 166 extending through
top surface 34 and three corresponding threaded bores 167 extending
through bottom surface 33 and o | | |
