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Claims  |
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I claim:
1. A semiconductor device capable of receiving external power comprising:
a semiconductor circuit having a plurality of circuit cells addressable by
electrically conductive row and column lines, and having a power altering
circuit for receiving the external power and providing an altered power
signal to the semiconductor circuit, the altered power signal capable of
being provided by an electrically conductive bus to the plurality of
circuit cells through the plurality of row lines or the plurality of
column lines;
a die having the semiconductor circuit and a plurality of input terminals
formed thereon, a first input terminal being electrically coupled to the
electrically conductive bus, a first set of input terminals being coupled
to and providing power signals to the semiconductor circuit, a second set
of input terminals being coupled to and providing address signals to
access circuit cells in the semiconductor circuit through the row and
column lines, and a third set of input terminals being coupled to and
providing input signals to and output signals from the semiconductor
circuit;
a plurality of electrically conductive leads each having an externally
accessible end and a free end, the free ends of first, second and third
sets of leads being electrically coupled to at least some of the input
terminals in the first, second and third sets of input terminals,
respectively, and at least one of the plurality of leads being a
superfluous lead capable of being unused during operation of the
semiconductor circuit;
an electrical conductor coupled between the first input terminal and the
free end of the superfluous lead, the superfluous lead capable of
providing supplementary external power as the altered power signal during
testing of the semiconductor circuit to the plurality of circuit cells
through the electrical conductor, the first input terminal and the
plurality of row or column lines; and
an encapsulating material that encapsulates the semiconductor circuit, the
die, the free ends of the leads and the electrical conductor as a packaged
chip.
2. The semiconductor device of claim 1, further comprising a test mode
circuit formed on the die that receives predetermined signals from at
least some of the input terminals in one of the second and third sets of
input terminals to initiate a test mode for the semiconductor device and
allow the plurality of row lines to receive the altered power signal
through the electrical conductor.
3. The semiconductor device of claim 1 wherein the encapsulating material
forms the packaged chip as an automatically manipulatable packaged chip.
4. The semiconductor device of claim 1 wherein the power altering circuit
is a voltage boosting circuit that boosts the external power to provide a
boosted voltage to the plurality of row lines.
5. The semiconductor device of claim 1 wherein the each of leads is
assigned to receive one the power, address, input and output signals, and
wherein the superfluous lead is redundantly assigned to receive the power
signal.
6. The semiconductor device of claim 1 wherein the each of leads is
assigned to receive one of the power, address, input and output signals,
and wherein the superfluous lead has an unused assignment so as to be
unconnected to the semiconductor circuit in the absence of the electrical
conductor.
7. The semiconductor device of claim 1 wherein alternate row lines in the
plurality of row lines are capable of simultaneously receiving the altered
power signal through the electrical conductor and of providing the altered
power signal to approximately half of the plurality of circuit cells in a
checkerboard pattern.
8. The semiconductor device of claim 1, further comprising a test mode
circuit formed on the die that receives enable signals from the at least
some of the input terminals in one of the second and third sets of input
terminals to initiate a test mode for the semiconductor device and allows
alternate row lines in the plurality of row lines to receive the altered
power through the electrical conductor to thereby stress test the circuit
cells for short circuit failures therebetween.
9. The semiconductor device of claim 1, further comprising at least one
diode coupled between the first input terminal and the semiconductor
circuit.
10. A semiconductor memory device capable of receiving external power
comprising:
a semiconductor memory circuit having an array of memory cells addressable
by electrically conductive row and column lines, and having a voltage
boosting circuit for providing boosted voltage from a supply voltage
provided to the semiconductor memory circuit, the boosted voltage capable
of being provided to the array of memory cells through the plurality of
row lines;
a die having the semiconductor memory circuit and a plurality of pads
formed thereon, a first pad being electrically coupled to the voltage
boosting circuit, a first set of pads being coupled to and providing power
signals to the semiconductor memory circuit, a second set of pads being
coupled to and providing address signals to access memory cells in the
semiconductor memory circuit through the row and column lines, and a third
set of pads being coupled to and providing input signals to and output
signals from the semiconductor memory circuit;
a plurality of electrically conductive leads each having a pin end assigned
to receive one of the power, address, input and output signals and a free
end, the free ends of first, second and third sets of leads being
electrically coupled to at least some of the pads in the first, second and
third sets of pads, respectively, and at least one of the leads being a
selected lead capable of being unused during standard operation of the
array of memory cells;
an electrical conductor coupled between the first pad and the free end of
the superfluous lead, the selected lead capable of providing supplementary
external power as the boosted voltage to the array of memory cells through
the electrical conductor, the first pad and at least some of the plurality
of row and column lines during stress testing of the semiconductor memory
circuit; and
an encapsulating material that encapsulates the semiconductor memory
circuit, the die, the free ends of the leads and the electrical conductor
as a packaged chip.
11. The semiconductor memory device of claim 10 wherein the selected lead
is redundantly assigned to receive the power signal.
12. The semiconductor memory device of claim 10 wherein the selected lead
has an unused assignment so as to be unconnected to the semiconductor
memory circuit in the absence oft he electrical conductor.
13. The semiconductor memory device of claim 10 wherein alternate row lines
in the plurality of row lines are capable of simultaneously receiving the
altered power signal through the electrical conductor and of providing the
altered power signal to approximately half of the array of memory cells in
a checkerboard pattern.
14. The semiconductor memory device, of claim 10, further comprising a test
mode circuit formed on the die that receives enable signals from the at
least some of the pads in one of the second and third sets of pads to
initiate a test mode for the semiconductor memory device and allows
alternate row lines in the plurality of row lines to receive the boosted
voltage through the electrical conductor to thereby stress test memory
cells for short circuit failures therebetween.
15. The semiconductor memory device of claim 10, further comprising at
least one diode coupled between the first pad and the semiconductor memory
circuit.
16. A semiconductor memory device testing apparatus comprising:
a semiconductor memory circuit having a plurality of memory cells
addressable by electrically conductive row and column lines, and having a
voltage boosting circuit for providing boosted voltage from a supply
voltage provided to the semiconductor memory circuit, the boosted voltage
capable of being provided to the plurality of memory cells through the
plurality of row lines;
a die having the semiconductor memory circuit and a plurality of pads
formed thereon, a first pad being electrically coupled to the voltage
boosting circuit, a first set of pads being coupled to and providing power
signals to the semiconductor memory circuit, a second set of pads being
coupled to and providing address signals to access memory cells in the
semiconductor memory circuit through the row and column lines, and a third
set of pads being coupled to and providing input signals to and output
signals from the semiconductor memory circuit;
a plurality of electrically conductive leads each having an externally
accessible end assigned to receive one of the power, address, input and
output signals and a free end, the free ends of first, second and third
sets of leads being electrically coupled to at least some of the pads in
the first, second and third sets of pads, respectively, at least one lead
being a redundant or unused lead as specified under a semiconductor
industry standard for the semiconductor memory device;
an electrical conductor coupled between the first pad and the free end of
the superfluous lead, the at least one lead capable of providing
supplementary external power as the boosted voltage to the plurality of
memory cells through the electrical conductor, the first pad and at least
one of the plurality of row and column lines during testing of the
semiconductor memory circuit;
an encapsulating material that encapsulates the semiconductor memory
circuit, the die, the free ends of the leads and the electrical conductor
as a packaged chip;
a testing circuit for applying the power, address and input signals to the
packaged chip under direction of a test routine and analyzing the output
signals therefrom;
an external power source for supplying the supply voltage to the at least
one lead; and
a socket for releasably holding the packaged chip and electrically coupling
the first, second and third sets of leads to the testing circuit and the
at least one lead to the external power source during testing of the
packaged chip.
17. A method of forming a semiconductor device comprising the steps of:
providing a die;
forming a semiconductor memory circuit on the die, the semiconductor memory
circuit including an array of memory cells accessible by a plurality of
row and column lines;
forming a voltage pump circuit electrically coupled to the plurality of
memory cells, through the plurality of row lines, to provide a boosted
voltage thereto;
forming a plurality of pads on the die, a first pad being electrically
coupled to the voltage pump circuit, a first set of pads being coupled to
and providing power signals to the semiconductor memory circuit, a second
set of pads being coupled to and providing address signals to access
memory cells in the semiconductor memory circuit through the row and
column lines, and a third set of pads being coupled to and providing input
signals to and output signals from the semiconductor memory circuit;
providing a plurality of electrically conductive leads including a
superfluous lead capable of being unused during standard testing of the
semiconductor device, each lead having an external end for external
electrical coupling;
electrically connecting free ends of first, second and third sets of leads
to at least some of the pads in the first, second and third sets of pads,
respectively;
electrically connecting a free end of the superfluous lead to the first pad
to thereby allow supplementary external power to be provided as the
boosted voltage to the plurality of memory cells through the plurality of
row lines during testing of the semiconductor device; and,
encapsulating the die, the semiconductor memory circuit, the voltage pump
circuit, and the free ends of the leads as an externally testable packaged
device.
18. The method of claim 17, further comprising the step of forming a
protection diode coupled between the first pad and the voltage pump
circuit.
19. The method of claim 17, further comprising the step of forming a test
mode circuit on the die that receives signals from the at least some of
the pads in one of the second and third sets of pads to initiate a test
mode for the semiconductor memory device and allows alternate row lines in
the plurality of row lines to receive the supplementary external power to
thereby stress test memory cells for short circuit failures between memory
cells.
20. The method of claim 17 wherein the steps of forming a voltage pump
circuit and forming a semiconductor memory circuit form alternate row
lines in the plurality of row lines that are capable of simultaneously
receiving the altered power signal through the electrical conductor and of
providing the altered power signal to approximately half of the plurality
of memory cells in a checkerboard pattern. |
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Claims |
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Description |
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TECHNICAL FIELD
The present invention relates to apparatus and methods for testing
semiconductor electrical devices, particularly memory devices.
BACKGROUND OF THE INVENTION
Various types of defects and failures can occur during the manufacture of
semiconductor devices. A "failure" occurs when a semiconductor device
fails to meet its specifications. A "defect" occurs when a semiconductor
device has an improper circuit structure that currently presents a failure
of the device, or has the potential to fail during the expected lifetime
of the device. For example, due to a manufacturing error, an insulator or
dielectric between a pair of memory cells can be thinned or include
polysilicon particles which could currently provide a short therebetween,
or could break down over a period of time ("a cell-to-cell defect"). After
this period of time, typically during prolonged use of the device, the
polysilicon particle provides a conductive path between the cells so that
a "high" voltage written to one cell forces a "low" voltage on an adjacent
cell to rise to a high value, resulting in a failure.
Therefore, a polysilicon particle that presently shorts two memory cells
together is a defect resulting in a failure of the semiconductor device. A
polysilicon particle that has not yet formed a short between the two
memory cells, however, is a defect that has not yet evidenced itself as a
failure. As a result, the semiconductor device can be operated for a brief
time under standard operating conditions and voltages before the defect
manifests itself as a failure.
Testing is performed on semiconductor devices to locate defects and
failures in such devices. As circuit density on semiconductor devices
increases, the number of defects and failures can increase. Semiconductor
manufacturers, therefore, have an increasing need to detect for defects
and failures in semiconductor devices as circuit density on these devices
increases.
Thus, for quality control and to improve yields of acceptably operable
semiconductor devices, semiconductor devices are tested, often before a
die containing the semiconductor device is packaged into a chip. A series
of probes on a test station electrically contact pads on each die in a
wafer to thereby access portions of the individual semiconductor devices
on the die. For example, in a semiconductor memory device, the probes
contact address and data input/output pads to access selected memory cells
in the memory device. Typical dynamic random access memory devices
("DRAM") include one or more arrays of memory cells that are each arranged
in rows and columns. Each array of memory cells includes word or row lines
that select memory cells along a selected row, and bit, digit or column
lines (or pairs of lines) that select individual memory cells along a row
to read data from, or write data to, the cells in the selected row.
During testing, predetermined data or voltage values are typically written
to selected row addresses, or row and column addresses, that correspond to
certain memory cells, and then the voltage values are read from those
memory cells to determine if the read data matches the data written to
those addresses. If the read data does not match the written data, then
the memory cells at the selected addresses likely contain defects and the
semiconductor devices fail the test.
A person testing the several dies on the wafer can then examine a
particular die itself, by means of a microscope, to determine if failures
occurred from masking defects, during the deposition of certain layers,
and so forth. During the initial development of a semiconductor device,
and while the device is in die form, changes to masks can be made to
compensate for most detected failures. However, once a semiconductor
device is in production and packaged as a chip, redundant circuitry on the
semiconductor device can be employed to compensate for only certain
detected failures. Redundant circuitry on the semiconductor device cannot
compensate for many detected failures, and therefore, such failed devices
must generally be discarded.
Semiconductor manufacturers, to increase output of acceptable semiconductor
devices, strive to perform rapid testing of the semiconductor devices to
expose defects in the devices before shipping them to a vendor or user. A
semiconductor device can be most thoroughly tested when the device is
still in die form on the semiconductor wafer. Semiconductor wafers,
however, are often difficult to manipulate, and typically require a test
bed or other apparatus to releasably secure the wafer while the probes are
adjusted to contact the pads on each die on the wafer. As a result,
testing of semiconductor devices in die form is time consuming. Therefore,
semiconductor manufacturers desire to test a given semiconductor device
after it has been packaged as a semiconductor chip, because the chip can
be automatically inserted into a test socket for testing using pick and
place machinery. Automated testing circuitry can then apply predetermined
voltages and signals to the chip, write test patterns thereto, and analyze
the results therefrom to detect for failures in the chip.
Often, the number of pads on a die is greater than the number of pins on
the packaged semiconductor chip. Therefore, as noted above, certain tests
performed while the semiconductor device is in die form cannot be
performed on the device after it has been packaged. As a result, package
chips necessarily undergo less rigorous testing than unpackaged dies.
Packaged chips therefore can include manufacturing defects that are not
yet failures and thus are undetectable by the limited number of tests
capable of being performed on the packaged chips.
For example, to test for the above-identified cell-to-cell defect, a test
circuit writes a pattern of higher, than average voltage values (as
logical "1" values) to memory cells coupled to or "along" several row
lines, while writing low voltage values (as logical "0" values) to memory
cells along the adjacent row lines. The test circuit then determines
whether the memory cells along the adjacent row lines maintain a logical
"0" value. If not, then the logical "1" value written to a first memory
cell has shorted to an adjacent memory cell, causing the low voltage or
logical "0" value to rise to become a high voltage or logical "1" value.
The time required for the high voltage value in the first memory cell to
raise the voltage in the adjacent memory cell will vary depending upon the
severity of the defect between the cells. As a result, a high voltage
value over a continuous period of time must be applied to the memory cells
along the first row lines to force the failure to the memory cells along
the adjacent row lines. External test circuitry typically must apply such
a continuous, high voltage value to the semiconductor memory device while
the device is still in its die form.
Some semiconductor memory devices include an on-chip voltage pump that
provides a boosted voltage, greater than the supply voltage Vcc, that can
provide the continuous, high voltage value to memory cells along several
row lines. However, typical 16 megabit DRAM circuits contain 4096 row
lines. As a result, to test only memory cells along half of the row lines
over the period required to force a cell-to-cell defect, when the voltage
pump can activate only several row lines at a time, requires a prolonged
test cycle for each packaged chip. Consequently, cell-to-cell defects
cannot be efficiently tested in packaged chips. As a result, cell-to-cell
defects can typically only be tested efficiently when the semiconductor
memory device is in die form. Probes access the voltage pump circuit and
apply supplemental power to the device being tested to thereby
simultaneously provide the high voltage value to multiple row lines over
the continuous test period. Such a cell-to-cell stress test, however,
suffers from the above-described difficulties in testing semiconductor
memory circuits when in die form. Therefore, any time saved by conducting
the cell-to-cell stress test while the semiconductor device is in die form
is offset by the time consuming process of manipulating and testing
semiconductor wafers.
SUMMARY OF THE INVENTION
The present invention allows packaged semiconductor chips, such as DRAMs
and other semiconductor memory devices, to undergo certain tests when in
packaged form, where such tests previously had been available only to
unpackaged devices (i.e., semiconductor devices in die form). The present
invention electrically couples a superfluous pin or lead on the packaged
chip to a voltage pump pad Vccp on the die. As a result, power from an
external supply can be applied to the die, while in packaged chip form, to
thereby efficiently perform certain tests on the semiconductor device. For
example, a voltage pump circuit on the die normally has the capacity to
provide a high voltage Vccp to activate only a few row lines
simultaneously. By coupling the external power supply to supplement the
voltage pump capacity, through one of two redundant Vcc pins in the
packaged part, multiple row lines can be simultaneously activated.
Alternatively, an unused or non-connected pin can be so coupled. As a
result, the present invention allows one of the most common defects in
DRAMs, cell-to-cell defects, to be rapidly tested in a packaged chip.
Since packaged chips can be tested in parallel, using automated equipment,
as opposed to testing in die form, the present invention provides a
tremendous time saving step during the testing of semiconductor devices.
In a broad sense, the present invention embodies a semiconductor device
capable of receiving external power. The semiconductor device includes a
semiconductor circuit having a plurality of circuit cells addressable by
electrically conductive row and column lines. The semiconductor circuit
also has a power altering circuit for receiving external power and
providing an altered power signal to the semiconductor circuit. The
altered power signal is capable of being provided to the plurality of
circuit cells through the plurality of row lines or the plurality of
column lines.
A die having the semiconductor circuit and a plurality of input terminals
formed thereon has a first input terminal that is electrically coupled to
the power altering circuit. A first set of input terminals is coupled to
and provides power signals to the semiconductor circuit. A second set of
input terminals is coupled to and provides address signals to access
circuit cells in the semiconductor circuit through the row and column
lines. A third set of input terminals is couple to and provides input
signals to and output signals from the semiconductor circuit.
A plurality of electrically conductive leads each have a pin end and a free
end. The free ends of first, second and third sets of leads are
electrically connected to at least some of the input terminals in the
first, second and third sets of input terminals, respectively. At least
one of the plurality of leads is a superfluous lead. An electrical
conductor is coupled between the first input terminal and the free end of
the superfluous lead. This superfluous lead is capable of providing
supplementary external power as the altered power signal to the plurality
of circuit cells through the electrical conductor, the first input
terminal and the plurality of row or column lines. An encapsulated
material encapsulates the semiconductor circuit, the die, the free ends of
leads and the electrical conductor as a packaged chip.
The present invention also embodies a method of forming a semiconductor
device comprising the steps of: (i) providing a die; (ii) forming a
semiconductor memory circuit on the die, the semiconductor memory circuit
including an array of memory cells accessible by a plurality of row and
column lines; (iii) forming a voltage pump circuit electrically coupled to
the plurality of memory cells, through the plurality of row lines, to
provide a boosted voltage thereto; (iv) forming a plurality of pads on the
die, a first pad being electrically coupled to the power altering circuit,
a first set of pads being coupled to and providing power signals to the
semiconductor memory circuit, a second set of pads being coupled to and
providing address signals to access memory cells in the semiconductor
memory circuit through the row and column lines, and a third set of pads
beings coupled to and providing input signals to and output signals from
the semiconductor memory circuit; (v) providing a plurality of
electrically conductive leads including a superfluous lead, each lead
having a pin end for external electrical coupling; (vi) electrically
connecting free ends of first, second and third sets of leads to at least
some of the pads in the first, second and third sets of pads,
respectively; (vii) electrically connecting a free end of the superfluous
lead to the first pad to thereby allow supplementary external power to be
provided as the boosted voltage to the plurality of memory cells through
the plurality of row lines; and, (viii) encapsulating the die, the
semiconductor memory circuit, the voltage pump circuit, and the free ends
of the leads as an eternally testable packaged device.
The present invention furthermore embodies a method of testing a packaged
semiconductor device having a semiconductor memory circuit, a voltage
boosting circuit and a plurality of pads formed on a die. The memory
circuit has an array of memory cells addressable by electrically
conductive row and column lines. The voltage boosting circuit provides a
boosted voltage signal to the memory circuit. A first set of pads is
coupled and provides power signals to the semiconductor memory circuit, a
second set of pads is coupled to and provides address signals to access
memory cells in the semiconductor memory circuit through the row and
column lines, and a third set of pads is coupled to and provides input
signals to and output signals from the semiconductor memory circuit. The
semiconductor device also has a plurality of electrically conductive leads
each having a pin end and a free end. The free ends of first, second and
third sets of leads are electrically connected to at least some of the
pads in the first, second and third sets of pads, respectively. The method
includes the steps of: (I) providing the packaged semiconductor memory
device, the memory device having at least one superfluous lead having a
free end coupled to the first pad; (ii) applying a predetermined voltage
to at least one of the leads in the first set of leads; (iii) applying a
predetermined combination of signals to the leads in the first or second
sets of leads; (iv) providing external supplementary power to the
superfluous lead as the boosted voltage signal; (v) simultaneously
applying the boosted voltage signal for a predetermined period of time to
a selected number of row lines and thereby writing a high voltage value to
a preselected pattern of memory cells in the array of memory cells; (vi)
analyzing values stored in the non-selected memory cells; and (vii)
determining that the memory device is defective if the high voltage value
written to the selected number of memory cells approximately equals a
value on a non-selected memory cell.
The present invention solves problems inherent in the prior art of
semiconductor testing by allowing certain tests to be performed on
packaged semiconductor chips that are available to unpackaged dies, but
previously unavailable to packaged chips. As a result, the present
invention can rapidly test semiconductor devices for cell-to-cell defects
by supplying an external voltage to supplement the voltage pump capacity
in a packaged part to simultaneously allow multiple row lines in a memory
device to be tested for cell-to-cell short circuiting between memory
cells. Other features and advantages of the present invention will become
apparent from studying the following detailed description of the presently
preferred embodiment, together with the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a packaged semiconductor memory device under
the present invention.
FIG. 2 is a schematic diagram of two memory cells from the semiconductor
memory device of FIG. 1, which shows a defect short circuiting the two
cells.
FIG. 3 is a scanning electron microscope photograph of several memory cells
from the semiconductor memory device of FIG. 1 showing a polysilicon
defect between two memory cells.
FIG. 4 is a greatly enlarged plan view of memory cells for the
semiconductor memory circuit of FIG. 1 showing the physical layout of the
memory cells.
FIG. 5 is a partial isometric, partial block diagram of a testing station
for testing the packaged semiconductor memory device of FIG. 1.
FIG. 6 is a flowchart diagram of the steps performed by the testing station
of FIG. 5.
FIG. 7 is a block diagram of an alternative embodiment of the package
semiconductor memory device of FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, a block diagram of a 16 megabit DRAM packaged chip 100
is shown as having a substrate or die 102 encapsulated by a protective
material 104 such as epoxy or plastic. Twenty-four electrically conductive
leads 106 have a pin end extending from the package chip 100, and a free
end (shown in dashed lines) encapsulated within the protective material
104. Several pads 110 are formed on, and at the periphery of, the die 102.
The pads 110 are electrically coupled to a semiconductor circuit such as a
memory circuit 112 formed on the die 102 and form input terminals for the
circuit. As explained more fully below, several of the pads 110 are
electrically coupled to the free ends of the leads 106 by means of
electrically conductive members such as bond wires 114. As a result, the
pin ends of the leads 106 in the packaged chip 100 provide an external
electrical path through the bond wire 114 to the die 102.
Each of the twenty-four leads 106 in the package chip 100 typically has an
industry specified standard assignment based on the type of semiconductor
circuit formed on the die 102. An acronym for the assignment of each pin
in the exemplary 16 megabit packaged chip 100 is shown next to the pin end
of the leads 106, and are as follows: positive voltage supply pins Vcc,
data input/output pins DQ1-DQ4, address pins A0-A10, write enable pin WE,
row address select pin RAS, column address select pin CAS, output enable
pin OE, negative or ground voltage supply pins Vss, and a non-connected
pin NC. While the general type of signals applied to each pin are
established by industry standards, the particular voltages and timing of
the signals applied to each pin often vary between packaged chips 100, and
between manufacturers of similar semiconductor circuits.
Several pads 110 shown in FIG. 1 have acronyms that are identical to the
pin assignment acronyms for the twenty-four leads 106. The free end of
each lead 106 is electrically coupled to its appropriate pad 110 by means
of bond wires 114. For example, the lead 106 associated with the A10 pin
is coupled to the A10 pad 110 b | | |
