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Claims  |
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What is claimed is:
1. A method for generating a desired filter coefficient of a digital
filter, wherein each filter coefficient has a corresponding coefficient
address in an address space defined by a number of taps of the digital
filter, the method using a memory in which a plurality of coefficient
values, less than the number of taps of the digital filter, are stored,
wherein each pair of adjacent coefficient values stored in the memory
define boundaries of a region including a plurality of addresses in the
address space, and wherein at least one region has a number of addresses
different from other regions, the method comprising the steps of:
receiving a coefficient address in the address space and corresponding to
the desired filter coefficient;
determining the region including the coefficient address;
selecting a stored coefficient value from the memory defining one boundary
of the determined region;
generating a difference value indicating a difference between the selected
coefficient value and an adjacent coefficient value stored in the memory
and defining another boundary of the determined region;
generating a fractional value indicating a distance between the coefficient
address and a coefficient address corresponding to the selected
coefficient value; and
generating the desired filter coefficient as a function of the selected
coefficient value, the difference value and the fractional value.
2. The process of claim 1, wherein the process further uses a difference
memory containing difference values corresponding to each coefficient
value in the memory, and wherein the step of generating the difference
value comprises the step of:
selecting the difference value from the difference memory corresponding to
the selected coefficient value.
3. The process of claim 1, wherein the step of selecting a coefficient
value from the memory comprises the steps of:
mapping a number of the most significant bits of the coefficient address to
provide a reduced coefficient address and a shift control output;
shifting a number of the least significant bits of the coefficient address
to provide a shifted output; and
accessing the memory using the reduced coefficient address and most
significant bits of the shifted output to obtain the selected coefficient
value.
4. The process of claim 3, wherein the step of selecting the difference
value includes the step of accessing the difference memory using most
significant bits of the shifted output.
5. The process of claim 3, wherein the fractional value is least
significant bits of the shifted output.
6. The process of claim 1, wherein the step of generating the difference
value comprises steps of:
selecting the adjacent coefficient value from the memory; and
computing a difference between the adjacent coefficient value and the
selected coefficient value.
7. The process of claim 6, wherein the step of selecting a coefficient
value from the memory comprises the steps of:
mapping a number of the most significant bits of the coefficient address to
provide a reduced coefficient address and a shift control output;
shifting a number of the least significant bits of the coefficient address
to provide a shifted output; and
accessing the memory using the reduced coefficient address and most
significant bits of the shifted output to obtain the selected coefficient
value.
8. The process of claim 7, wherein the fractional value is least
significant bits of the shifted output.
9. The process of claim 1, wherein the step of selecting a coefficient
value from the memory comprises the steps of:
mapping a number of the most significant bits of the coefficient address to
provide a reduced coefficient address and a shift control output;
shifting a number of the least significant bits of the coefficient address
to provide a shifted output; and
accessing the memory using the reduced coefficient address and most
significant bits of the shifted output to obtain the selected coefficient
value.
10. The process of claim 9, wherein the fractional value is least
significant bits of the shifted output.
11. A circuit for generating a desired filter coefficient of a digital
filter, wherein each filter coefficient has a corresponding coefficient
address in an address space defined by a number of taps of the digital
filter, the circuit using a memory in which a plurality of coefficient
values, less than the number of taps of the digital filter, are stored,
wherein each pair of adjacent coefficient values stored in the memory
define boundaries of a region including a plurality of addresses in the
address space, and wherein at least one region has a number of addresses
different from other regions, the circuit comprising:
means for receiving a coefficient address in the address space and
corresponding to the desired filter coefficient;
means for determining the region including the coefficient address;
means for selecting a stored coefficient value from the memory according to
the determined region;
means for generating a difference value indicating a difference between the
elected coefficient value and an adjacent coefficient value stored in the
memory and defining another boundary of the determined region;
means for generating a fractional value indicating a distance between the
coefficient address and a coefficient address corresponding to the
selected coefficient value; and
means for computing the desired filter coefficient as a function of the
selected coefficient value, the difference value and the fractional value.
12. The circuit of claim 11, wherein the means for generating the
difference value includes:
a difference memory containing difference values corresponding to each
coefficient value in the memory; and
means for selecting the difference value from the difference memory
corresponding to the selected coefficient value.
13. The circuit of claim 12, wherein the means for selecting a coefficient
value from the memory comprises:
means for mapping a number of the most significant bits of the coefficient
address to provide a reduced coefficient address and a shift control
output;
means for shifting a number of the least significant bits of the
coefficient address to provide a shifted output; and
means for accessing the memory using the reduced coefficient address and
most significant bits of the shifted output to obtain the selected
coefficient value.
14. The circuit of claim 13, wherein the means for selecting the difference
value includes means for accessing the difference memory using most
significant bits of the shifted output.
15. The circuit of claim 13, wherein the fractional value is least
significant bits of the shifted output.
16. The circuit of claim 11, wherein the means for generating the
difference value includes:
means for selecting the adjacent coefficient value from the memory; and
means for computing a difference between the adjacent coefficient value and
the selected coefficient value.
17. The circuit of claim 16, wherein the means for selecting a coefficient
value from the memory comprises:
means for mapping a number of the most significant bits of the coefficient
address to provide a reduced coefficient address and a shift control
output;
means for shifting a number of the least significant bits of the
coefficient address to provide a shifted output; and
means for accessing the memory using the reduced coefficient address and
most significant bits of the shifted output to obtain the selected
coefficient value.
18. The circuit of claim 17, wherein the fractional value is least
significant bits of the shifted output.
19. The circuit of claim 11, wherein the means for selecting a coefficient
value from the memory comprises:
means for mapping a number of the most significant bits of the coefficient
address to provide a reduced coefficient address and a shift control
output;
means for shifting a number of the least significant bits of the
coefficient address to provide a shifted output; and
means for accessing the memory using the reduced coefficient address and
most significant bits of the shifted output to obtain the selected
coefficient value.
20. A circuit for generating a desired filter coefficient of a digital
filter, wherein each filter coefficient has a corresponding coefficient
address in an address space defined by a number of taps of the digital
filter, wherein the address space is divided into a plurality of regions,
wherein each region includes a plurality of addresses in the address
space, and wherein at least one region has a number of addresses different
from other regions, the circuit comprising:
a mapping circuit having an input for receiving a coefficient address in
the address space for the desired filter coefficient and an output
providing an indication of a region which includes the received
coefficient address;
a memory circuit including a memory in which a plurality of coefficient
values, less than the number of taps of the digital filter, are stored,
and wherein each pair of adjacent coefficient values stored in the memory
define boundaries of one of the regions in the address space such that at
least one region has a number of addresses different from other regions,
and wherein the memory circuit has an input connected to receive the
output of the mapping circuit and a first output providing from the memory
a first coefficient value defining one boundary of the region indicated by
the output of the mapping circuit a second output providing a difference
value indicating a difference between the first coefficient value and a
second adjacent coefficient value in the memory defining another boundary
of the region and a third output providing a fractional value indicating a
distance between the received coefficient address and a coefficient
address corresponding to the first coefficient value; and
an arithmetic unit having inputs connected to the first, second and third
outputs of the mapping circuit to receive the coefficient value, the
difference value and the fractional value and an output providing the
desired filter coefficient as a function of the coefficient value, the
difference value and the fractional value. |
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Claims |
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Description |
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FIELD OF THE INVENTION
The invention is related to circuits for converting data samples received
at a first sample rate into corresponding data samples provided at a
second rate. More particularly, the invention is a sample rate converter
capable of converting a sequence of digital data samples presented at an
input sample rate into a different sequence of digital data provided at an
output sample rate which is not a rational multiple or submultiple of the
input sample rate.
BACKGROUND OF THE INVENTION
It is becoming common for audio recording studios to digitize signals
produced by analog sources, such as microphones. In these studios, audio
recording, production, editing and processing is performed completely in
the digital domain. For this reason, most modern digital audio equipment
comes equipped to receive digital input signals and to provide digital
output signals; analog-to-digital converters and digital-to-analog
converters are often optional. There is, however, no established standard
for digital sampling rates for all types of information. The need for
simple digital interfacing between different equipment has thus become
very important.
The most common solution to the digital interface problem is to use a
phase-locked loop to recover the sample rate of input data, and to use the
resulting high frequency clock as an internal system clock. One problem
that often arises is that an internal system clock must be fixed at a
frequency that is not related to the frequency of the input serial data.
An example of this problem occurs in digital videotape recorders, where
the internal system clock must be related to a standard video frequency,
and must be able to lock up with a master video synchronizing generator
whose frequency is not related to the frequency of serial input data, such
as digital audio data. Therefore, such digital videotape recorders, and
similar devices, need a sample rate converter to convert input audio
signals sample at some unknown rate (though typically 44.1 kHz) to
corresponding digital samples at a local, fixed sample rate.
There are two classes of sample rate converters: synchronous and
asynchronous. In synchronous sample rate converters, an input sample rate
is related to an output sample rate by a ratio of integers (3:2, for
example), i.e., a rational number. While such a device is sometimes
useful, the output rate is still related to the input rate. Equipment
which uses this data still must lock to it.
Asynchronous sample rate converters, on the other hand, are designed to
receive a stream of input data samples and produce output data samples
when requested by the system (i.e., not necessarily at a fixed rate
rationally related to the input rate). It is therefore capable of
converting between any two sample rates, and the ratio of these rates may
be irrational. Thus, the main purpose of an asynchronous digital sample
rate converter is to decouple the sampling rate of the input and output
data streams from the clock frequencies used in the processing or storage
of these data streams. Further, an asynchronous converter may correctly
follow the slow variations of the input and output sample rates. This type
of sample rate converter is in the most commercial demand today.
A simple analog method to change from one sample rate to another is shown
in FIG. 1. It uses a digital-to-analog (D/A) converter 50 followed by a
brick wall filter 52 to convert the signal back to the analog domain. This
analog signal from filter 52 is applied to an analog-to-digital (A/D)
converter 54 which runs at a different sample rate. (See FIG. 1) This
analog approach is complex and presents signal degradation problems, due
to harmonic distortion and noise caused by the A/D and D/A converters.
Thus, sample rate converters are more commonly implemented using digital
interpolation filters.
The operation of a digital interpolation filter, in both the time and
frequency domains, will now be described in connection with FIGS. 2A-2C.
In FIG. 2A digital data samples 40 are shown as a sample data signal
x(N*T), sampled at a rate Fs=1/T. The Fourier transform of x(N*T) is X(w),
which has periodic images 38 centered around all multiples of the sampling
rate, as according to sampling theory.
A desired interpolation ratio (R) is chosen and, between each sample 40 of
the original signal x(N*T), (R-1) zero-valued samples 42 are inserted at
constant intervals, as shown in FIG. 2B. This operation does not alter the
frequency-domain description of the signal, except that the signal is
considered to be sampled at a rate of Fs.sub.13 new=R*Fs.
The signal which included the zero-valued samples is applied to a digital
low-pass filter, with a cutoff frequency of one-half the input sample
rate, as shown in FIG. 2c. The output of this filter is the desired
interpolated signal, with images 44 around the higher sampling rate of
Fs.sub.-- new.
Referring now to FIG. 3, a purely digital sample rate converter includes a
digital interpolation filter 60 placed between input and output samplers
62 and 64, as shown in FIG. 3. The filter 60 includes a zero-stuff circuit
68 and a lowpass filter 70. A zero-order hold 66 is used at the output of
the interpolation filter 60, otherwise sample times would never line up
and the output would be zero.
The purpose of the digital interpolation filter 60 between the two input
and output samplers 62 and 64 in FIG. 3 is to produce a stream of output
samples on a much finer time grid than the original input samples. When
these interpolated values are fed into the zero-order hold 66, then
asynchronously re-sampled by the output sampler 64, the output values
represent the "nearest" (in time) values produced by the interpolation
filter. There is always some error in the output samples due to the fact
that the output sampler 64 does not operate to request a sample at a time
that exactly corresponds to a point on the fine time grid of the
interpolated outputs. This error is inversely related to the interpolation
ratio (R).
FIG. 4 shows a purely conceptual hardware implementation of a digital
interpolation filter, referred to because of its conceptual simplicity,
but which requires too much hardware to be implemented in a practical
manner. The input signal is sampled by sampler 80. A number of zero-valued
samples are inserted at constant intervals (defined by the interpolation
ratio and the input sample rate) between each sample by a zero-value
sample insertion circuit 82, and applied to an FIR interpolation filters
84 which is shown as a classic convolution machine employing a shift
register 86 in which the value stored in each tap 88 is multiplied using
multiplier 92 by a corresponding coefficient value (C.sub.0, C.sub.1, . .
. , C.sub.n). These products are summed by adder 94 to form an output. The
asynchronous output re-sampling switch 96 grabs the "nearest" interpolated
output when it closes. The fact that the interpolated output is held in a
register 98 for the duration of one cycle of the interpolation clock is
what provides a zero-order-hold function.
With such a circuit, if the interpolation ratio is about 2.sup.16 (i.e.,
65536) and the input sampling rate is 50 KHz, the shift register must
operate at a rate of 3.27 GHz. Providing a clock signal at such a rate is
highly impractical. Moreover, assuming that the shift register needs to be
operated at a rate of 3.27 GHz and that a new interpolated output is
produced on every cycle, the estimated length of a reasonably good 20 kHz
low-pass filter, (operating at a sampling rate of 3.27 GHz, having less
than 0.01 dB of ripple and attenuating by more than 110 dB any frequencies
above 24 kHz), is about U.S. Pat. No. 4,194,304 taps. This number
represents both the length of the shift register and the number of filter
coefficients which must be stored.
To develop a practical implementation of a digital sample rate converter
using a digital interpolation filter requires reducing this conceptual
hardware model described above into a practical hardware implementation.
That is, the number of taps and coefficients and the operating clock
frequency must be reduced. While others have found solutions to these
problems, these solutions are problematic and/or limited. Most are not
suitable for implementation in an integrated circuit.
For example, one problem experienced by all currently known systems is that
the input and output sample rates are expected to be fixed. Thus, these
systems are inflexible to changes in the input and output sampling rates.
Further, when these rates are changed, so that the filter changes from an
interpolation filter to a decimation filter, or vice-versa, these systems
require different hardware configurations. For an example, see U.S. Pat.
Nos. 4,604,720 and 4,584,659, issued to Eduard Stikvoort and assigned to
U.S. Philips Corporation. Changes in input or output sampling rates thus
require user interaction to modify the sample rate converter, or even a
different circuit., which is generally undesirable.
Solutions to the reduction of the conceptual hardware model of FIG. 4 are
based on the fact that the number of non-zero data values that exist at
any one time in the shift register 86 is equal to the number of taps
divided by the interpolation ratio R. For the example given above, the
number of non-zero values is 64. Thus, there is no reason to compute every
interpolated output at the 3.27 GHz rate when only roughly one out of
65,536 outputs is used. Further, since filter convolution only needs to be
performed when an output sample is required, occurring at the output
sample rate, the required multiply/accumulate rate is the product of the
output sample rate and the number of non-zero input data values in the
shift register at any one time.
This method implies that the exact arrival time of an output sample request
is measured, and that this information is used to determine where the
non-zero data values are in the conceptual shift register. Once the
locations of these values are determined, the correct subset of filter
coefficients can also be determined. These coefficients and data values
are multiplied and summed together to obtain the desired result. Thus, the
zero value data need not be stored in the shift register at all. As long
as the correct data values are maintained in the shift register, and the
correct coefficient subset to use is determined, the correct output for a
given output sample request can be determined. Thus, the process can be
considered as a time-varying FIR filter. Depending on the relative phases
of the input sample clock and the output sample clock, a particular set of
64 coefficients out of the total coefficient space would be chosen to
compute any requested output.
The problem with this method is that the arrival of an output sample
request needs to be accurately measured in order to determine the position
of the non-zero data values in the shift register with no error, thus
implying that a high frequency clock is available, for example, running at
3.27 GHz, which was to be avoided in the first place. The only solution to
this problem is to effectively average many more coarse measurements in a
way that the DC error is guaranteed to go to zero over the long term.
Another problem with reducing the conceptual model involves reducing the
set of filter coefficients that must be stored. Some solutions have been
proposed to this problem, such as in U.S. Pat. No. 4,825,398, issued to
Andreas Koch, et al., and assigned to Willi Studer, AG. Although the
linear interpolation method shown may reduce a set of four million stored
filter coefficients to about 16,000, that amount of storage is still
problematic for an integrated circuit implementation of a digital sample
rate converter. Higher order (e.g. quadratic) interpolation may enable
further reduction of this set, but increases computational complexity.
Other systems involve using a number of fixed prefilters in combination
with a smaller variable filter. One problem with these circuits is that
they require the use of a high-frequency clock signal which is related to
the input rate. Thus, a phase-locked loop must be used, requiring analog
components, which is undesirable for a purely digital integrated circuit
implementation.
A number of U.S. patents have been cited in this section for background
purposes. The disclosures of these patents (U.S. Pat. Nos. 4,584,659,
4,604,720 and 4,825,398) are hereby expressly incorporated by reference.
SUMMARY OF THE INVENTION
A digital sample rate converter in accordance with the present invention
includes a random access memory for storing input data values and a read
only memory for storing a reduced set of interpolation filter
coefficients. Input data is written to the random access memory at the
input sample rate. Output samples are provided from a multiply/accumulate
engine which, given a stream of input data and filter coefficients
produces an output sample upon receipt of an output sample request. The
initial address for reading input data from the random access memory and
the address for reading the initial filter coefficient from the read only
memory are provided by an auto-centering scheme. This scheme is a
first-order closed-loop system with a digital integrator fed by an
approximation of the input to output sample rate ratio. This
auto-centering scheme may include a feed-forward low-pass filter to cancel
steady state error, and an interpolated write address to reduce noise.
A circuit determining the output to input sample rate ratio can also be
provided to scale coefficient addresses and resulting output samples to
allow for the case when the output sample rate is less than the input
sample rate. This circuit includes a form of digital hysteresis to
eliminate noise.
The ROM coefficients are reduced by relying on the symmetry of the impulse
response of the interpolation filter and by utilizing a variable
step-size, forward and backward, linear interpolation.
The foregoing and other aspects, advantages, features and details of the
present invention will be more fully understood in view of the detailed
description which follows.
BRIEF DESCRIPTION OF THE DRAWING
In the drawing,
FIG. 1 is a block diagram of an analog method for sample rate conversion;
FIGS. 2A through 2C are graphs illustrating the concept of digital
interpolation;
FIG. 3 is a block diagram describing how digital sample rate conversion is
performed;
FIG. 4 is a conceptual block diagram of a theoretical digital sample rate
converter;
FIG. 5 is a block diagram of a sample rate converter in accordance with the
present invention;
FIG. 6 is a conceptual diagram illustrating read and write addresses of
input data in a random access memory;
FIG. 7 is a conceptual diagram illustrating how the location of the first
data value in the shift register changes with respect to time;
FIG. 8 is a block diagram of a preferred embodiment of the invention
illustrating a ramp generating circuit;
FIG. 9 is a block diagram of a circuit for interpolating the write
addresses;
FIG. 10 is a block diagram of a preferred embodiment of the ramp generating
circuit;
FIG. 11 is a block diagram of a circuit for generating the ratio of the
output frequency to the input frequency;
FIG. 12 is a block diagram illustrating a multiplier-free low-pass filter;
FIG. 13 is a block diagram of the preferred embodiment of the invention,
enabling both interpolation and decimation;
FIG. 14 is a block diagram illustrating how a 4 million tap digital
interpolation filter was designed;
FIGS. 15A and 15B describe the address folding operation for reducing the
number of stored filter coefficients;
FIGS. 16A and 16B illustrate linear interpolation of filter coefficients;
FIG. 17 is a block diagram of a circuit used in variable step size linear
interpolation of filter coefficients;
FIGS. 18A and 18B describe variable step size linear interpolation;
FIG. 19 is a block diagram of illustrating the preferred method of the
invention for reducing the number of stored filter coefficients;
FIGS. 20A and 20B describe in more detail the read address generating
circuit;
FIGS. 21A and 21B describe in more detail the coefficient address
generating circuit;
FIG. 22 is a block diagram of a preferred embodiment of a two-channel
multiply accumulator engine;
FIG. 23 is a state diagram for a state machine controller for controlling
the multiply/accumulate engine;
FIGS. 24A and 24B describe an integer arithmetic logic unit for use in a
preferred embodiment of the invention;
FIGS. 25A and 25B are flow charts describing multiply and divide operations
implemented by the integer ALU of FIG. 24;
FIG. 26 is the complete block diagram of the preferred embodiment of the
sample rate converter of the present invention; and
FIGS. 27A and 27B is a block diagram of a preferred embodiment of the
circuit of FIG. 9.
DETAILED DESCRIPTION
A detailed description of a preferred embodiment of the invention will now
be provided. This embodiment has been developed for implementation as an
integrated circuit for use with digital audio equipment, and has been
optimized accordingly. It should be understood by those skilled in the art
that modifications may be made to optimize the sample rate converter for
different applications. The interpolation ratio, the set of stored filter
coefficients, the size of a RAM for storing input data, the interpolation
filter design, and the gain of auto-centering scheme, are factors among
others which can be optimized for a given application.
As described above, in order to design a sample rate converter, appropriate
digital interpolation filter coefficients are determined. In the preferred
embodiment, we have selected an interpolation ratio of 2.sup.16 (i.e.,
65,536). A conceptual description of such a filter, and the implementation
problems to be solved, were provided above in connection with the
description of FIG. 4.
The interpolation ratio is selected on the basis of an error criterion
selected for the output. For the preferred embodiment a sample rate
converter with 16-bit accuracy was desired, thus the difference between
any two adjacent interpolated values should be less than one
least-significant-bit (1sb) at the 16-bit level.
The interpolation ratio required to achieve 16-bit accuracy is determined
on the basis of the input signal that causes the worst-case
sample-to-sample difference in the interpolated output. Since the
interpolation filter ideally cuts off at 20 kHz (the brick wall filter
cut-off frequency), the maximum slew rate of a 20 kHz sine wave may be
assumed to be the worst case signal. If maximum output levels of .+-.1 are
assumed, then a 20 kHz sine wave has a peak slew rate of:
S.R.=2*PI*1*20 kHz=125,600 v/sec.
A time grid of interpolated output signals is desired, such that when
multiplied by the slew rate above results in an error of less than
2/(2.sup.16), which is one 16-bit 1sb of the .+-.1 range assumed above.
This time grid is easily found to be 240 ps. If the input sample rate is
assumed to be about 50 kHz, the corresponding interpolation ratio R is
83,333.
Actually, a ratio of 83,333 is quite conservative for several reasons.
First, the RMS error over a 20 kHz sine-wave is more meaningful than the
peak error and results in a requirement for an interpolation ratio that is
about 3 dB lower than the peak error-based analysis would suggest.
Moreover, the error introduced by the misalignment of the output sampler
with the interpolation time grid was assumed to be maximum at each output
sampling time, when it is actually a statistical distribution that will
tend to lower the RMS error. For these reasons, for this embodiment an
interpolation value of 2.sup.16 (65,536) was used to achieve 16-bit
accuracy. Accuracy at lower frequencies and/or levels is significantly
higher due to the sin(x)/x nature of the zero-order hold (ZOH) frequency
response.
Given the desired interpolation ratio, a problem solved by the present
invention is the determination of the correct set of filter coefficients,
to be multiplied with input data, based on the relationship of input data
to locations in a conceptual shift register. The solution to this problem,
in the preferred embodiment, also solves the problem of making the system
respond adequately to step changes in sample rates.
FIG. 5 is a block diagram of an embodiment of the invention. In place of a
shift register, a random access memory (RAM) 100 is used to store incoming
data samples. The RAM 100 is addressed for writing data by a write counter
102 which is incremented according to the input sample rate. RAM 100 is
also addressed for reading data by a RAM address generator 110 which
generates read addresses.
Input data received via line 99 is written to sequential locations in the
RAM 100, according to the write address in write counter 102. When the
limit of the write addresses (due to the memory size) is reached, writing
continues at the first location in the RAM.
In response to an output sample request (not shown), a RAM address
generator 110 and a coefficient address generator 112 are controlled to
access sequentially a subset of the input data values in the RAM 100. The
accessed data values are multiplied (by multiplier 106) by corresponding
filter coefficients stored in a read only memory (ROM) 104, and
accumulated (by accumulator 108) to provide an output. The RAM address
generator 110, given an initial input data location in the RAM 100,
accesses sequential addresses to obtain the input data. The coefficient
address generator 112, given the location of the first filter coefficient
and an increment value, which is typically the interpolation ratio,
generates the locations of coefficients corresponding to the accessed
input data values. The increment value changes and the first coefficient
address is scaled for a decimation filter (when the output sample rate is
less than the input sample rate), as will be explained in more detail
below.
The coefficient addresses generated by generator 112 indicate locations
corresponding to the conceptual shift register model of the filter (FIG.
4). However, not all of the corresponding coefficient values are actually
stored. An interpolation is performed on a reduced set of coefficients,
using the input coefficient addresses. This interpolation procedure is
discussed in more detail below in connection with FIGS. 14 through 19.
The address of the first data value in the RAM 100 (the read start
address), and the first coefficient in the ROM 104 are generated by a ramp
generating circuit 114 which generates a ramp signal using a digital
integrator 116 fed with a signal approximating the ratio of the input
sample rate to the output sample rate. The digital integrator 116 provides
new values according to the output sample rate. Thus, its average slope is
proportional to the input sample rate. The output is split: a lower-order
set of bits (fractional part) is transmitted to line 113 to provide the
first filter coefficient address; an upper-order set of bits (integer
part) is transmitted to line 115 to provide the address of the initial
input data value (the read start address) in the RAM 100.
A reason for using an integrator to generate both the read start address to
RAM address generator 110 and the first coefficient address for the
coefficient address generator 112, and a circuit implementing this
feature, will now be described in connection with FIGS. 6-13.
Since data cannot be easily shifted into or within a RAM, with new data
inserted at RAM address 0, the read and write addresses are considered as
pointers in a circular (modulo) RAM. FIG. 6 shows a conceptual diagram.
Each time an input sample request occurs, the write address pointer 101 is
incremented (rotating in direction A) and the input data is written to the
location indicated by the new write address pointer value. When the end of
memory is reached (i.e., when pointer 101 reaches "LENGTH OF RAM"), the
write address pointer wraps to zero.
As with a shift register, there is no need to store all the zero-valued
samples (resulting from the zero-stuffing operation) in RAM, as they
contribute nothing to the accumulated sum. The RAM length must be large
enough so that all past non-zero values needed for the filter fit in the
RAM without wrap-around. Preferably, some overhead is provided to absorb
step changes in sample rates. The selection of the overhead size will be
described in more detail below.
In the shift register model of the filter, each coefficient multiplied the
value of one location in the shift register array. In a RAM-based
architecture, the data segment 103 (FIG. 6) to be multiplied by a
coefficient array is constantly rotating around the circular RAM in
direction B. Therefore, a rotating read pointer 105 gives the address of
the first data value to be multiplied by the first coefficient of the
filter. This value does not have to be the most recently written input
value. Some delay is desirable to make the RAM an elastic store buffer, to
allow the converter to respond to step changes in input or output sample
rates.
If an infinitely accurate number representing the ratio of the input sample
rate to the output sample rate were available computation of the read
start address would be simple. As discussed above, an integrator fed this
ratio and sample at the output sampling rate has an average slope equal to
the input sample rate. This slope is the same as the slope of the write
address. However, if the ratio is incorrect, the average slope of the read
start address from the integrator 116 is different from the average slope
of the write address. Thus the offset of the read start address from the
write address changes, and they may eventually cross, resulting in errors.
The error between the average slopes of the read and write addresses can
be used to correct the ratio estimate and thus to correct the output of
the digital integrator. Therefore, the read start address is determined
from an estimate of that ratio which has no error when averaged over a
long term. This estimate is determined using an auto-centering circuit
described below in connection with the description of FIGS. 8-13.
The location of the first non-zero data value in the shift register of the
conceptual model, and thus the first coefficient address, also changes in
a manner similar to the read start address for the RAM. FIG. 7 is a timing
diagram of the location in the conceptual shift register of the first
non-zero data value with respect to time. Arrows 117 along the time axis
show when an output sample clock edge occurs. Since new data enters the
conceptual shift register periodically, according to the selected
interpolation ratio (R), the location of the first non-zero data value
linearly increases to (R)-1 and then goes to zero when new data enters.
Therefore, given an input sample rate (Fs.sub.-- in) and an output sample
rate (Fs.sub.-- out), the following equation may be used to compute
recursively a new coefficient offset number from the last, or "old",
offset number:
New offset=(old offset+(R)*Fs.sub.-- in/Fs.sub.-- out)mod (R).
To gain some intuitive insight into this equation, if the input and output
sample rates are exactly the same, the same coefficient offset number is
produced for each output clock, as (R) is added to the old offset and the
result is taken modulo (R). Referring to the shift register model of FIG.
4, if the input and output sample rates are identical, the location of the
first non-zero data value in the shift register remains the same for each
closing of the output sampling. If, however, the input sampling rate is
slightly greater than the output sampling rate, the location of the first
non-zero data in the shift register drifts slowly to the right for
subsequent closings of the output sampling switch, until this location
"wraps" back through zero. Conversely, if the input sampling rate is
slightly lower than the output sampling rate, the location of the first
non-zero data value in the shift register slowly drifts to the left until
it wraps.
Because the first coefficient address ramps from zero to the interpolation
ratio R, with a frequency of the input sample rate, and because the read
start address increments according to the input sample rate, the first
coefficient address is simply the fractional part of the read start
address. Thus, a lower-order set of bits (a fractional part) of a ramp
signal (which ramps from zero to the length of the RAM 100, less one, and
which increments according to the input sample rate) indicates the first
coefficient address while an upper-order set of bits (an integer part)
indicates the read start address. The number of bits of the fractional
part is typically the number of bits used to represent the value of the
interpolation ratio R, less one, as a binary number. The number of bits of
the integer part is the number of bits which are needed to access all
addresses of the RAM 100.
A preferred embodiment for a ramp generating circuit 114 will now be
described in connection with FIG. 8. This embodiment is a first-order
closed-loop system which determines, from user-supplied clocks, a digital
estimate of the ratio of the input sample rate to the output sample rate,
where the ratio is unknown. This estimated ratio is fed to an integrator
to provide the desired ramp signal for the read start address and the
first coefficient address. It also maintains the average difference
between read and write addresses at a desired offset. The effective cutoff
frequency of this first-order loop is preferably 4 to 15 Hz.
The integrator 116 provides the desired ramp signal. Since the digital
integrator 116 receives an input proportional to the ratio of the input
sample rate to the output sample rate, and is sampled at the output sample
rate, the "average slope" of the integrator output is equal to the input
sample rate. Therefore, the integrator 116 output can be subtracted from
the write address to obtain a difference whose average value should be
constant over time if the ratio applied to integrator 116 agrees with the
actual input and output sample rates. Therefore, the output of integrator
116 is fed back to subtractor 118 which subtracts it from the current
write address latched by latch 111 at the output sample rate from write
address counter 102.
This output of subtractor 118 is applied through a small loop gain 124 (K)
to adder 126 which adds a "one" so that the nominal slope of the output of
integrator 116 is equal to the nominal slope of the write address when the
input and output sample rates are equal. For a fast settling time (e.g.
200 ms when the output sample rate is 50 kHz), a gain of 1/512 may be
used. For a relatively slower settling time (e.g. 800 ms when the output
sample rate is 50 kHz), a gain o | | |
