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Claims  |
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What is claimed is:
1. A semiconductor memory device including a memory array having a
plurality of memory cells arranged in a matrix of rows and columns,
comprising:
first signal generating means responsive to deactivation of a row address
strobe signal instructing a start of selection of a row in said memory
array to generate a signal resetting an operation related to selection of
the row in said memory cell array;
delay means for delaying the deactivation of said row address strobe signal
by a predetermined time; and
second signal generating means responsive to deactivation of the delayed
row address strobe signal from said delay means and deactivation of a
column address strobe signal instructing a start of selection of a column
in said memory array to generate an output allowance signal for setting an
output buffer outputting data of a selected memory cell to a data output
terminal to an output high impedance state.
2. The semiconductor memory device according to claim 1, wherein said
second signal generating means includes
a first pulse generator enabled by activation of the delayed row address
strobe signal, for generating a timing signal in response to each
deactivation of said column address strobe signal,
a second pulse generator enabled in response to the activation of said
delayed row address strobe signal and set in response to the timing signal
for generating an active signal and reset in response to deactivation of
said column address strobe signal and the delayed row address strobe
signal for deactivating said active signal, and
signal generator enabled in response to said active signal for being set in
response to said column address strobe signal being active for activating
said output allowance signal and being reset in response to said active
signal being deactivated and the deactivation of said column address
strobe signal for deactivating said output allowance signal to bring said
output buffer into the output high impedance state.
3. The semiconductor memory device according to claim 1, wherein said
second signal generating means includes means responsive to an operation
mode instructing signal being at a first level, said delayed row address
strobe signal and said column address strobe signal for maintaining said
output buffer in an operable state transferring data to said output
terminal until the deactivation of both the delayed row address strobe
signal and said column address strobe signal, and means responsive to said
operation mode instructing signal being at a second level and said column
address strobe signal for bringing said output buffer into the output high
impedance state upon each deactivation of said column address strobe
signal during the activation of said delayed row address strobe signal.
4. The semiconductor memory device according to claim 1, further
comprising:
memory selection means responsive to said row and column address strobe
signal for selecting a predetermined number of memory cells in said memory
array in accordance with an address signal, and
read means responsive to said column address strobe signal and said address
signal for selecting a memory cell among said predetermined number of
memory cells and transferring data of the selected memory cell to said
output buffer.
5. The semiconductor memory device according to claim 4, wherein said read
means includes amplifier means provided for each of the predetermined
number of memory cells and activated in response to said address signal
for amplifying data of a corresponding one of said predetermined number of
memory cells for transmission to said output buffer.
6. The semiconductor memory device according to claim 5, wherein said
memory selection means includes counter means responsive to said column
address strobe signal for performing a counting operation with the address
signal as an initial address and supplying a count to said amplifier
means, so that said amplifier means for the predetermined number of memory
cells are sequentially activated in accordance with the count.
7. The semiconductor memory device according to claim 4, wherein said read
means includes means a first and second read bus lines coupled to said
output buffer for transferring data to said output buffer,
amplifier means coupled to receive data of the selected memory cell, for
amplifying the data to produce complementary data, and
gate means coupled between said amplifier means and said first and second
read bus lines, for transferring the complementary data onto said first
and second bus lines in a first operation mode and inhibiting transfer of
one of the complementary data onto one of the first and second read bus
lines while allowing the transfer of the other of the complementary data
onto the other of the first and second read bus lines in a second
operation mode.
8. The semiconductor memory device according to claim 7, wherein said
output buffer includes means coupled to said first and second read bus
lines for producing complementary data in accordance with the
complementary data on said first and second read bus lines in said first
operation mode and for producing complementary data in accordance with the
data on said one of said first and second read bus lines in said second
operation mode.
9. A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells arranged in a matrix
of rows and columns;
column selecting means being activated in response to activation of a
column address strobe signal to select simultaneously a plurality of
columns in said memory cell array in accordance with a column address
signal;
a plurality of read amplifier means provided corresponding to said
plurality of columns for amplifying and transmitting data of said memory
cells in the corresponding columns to an output buffer;
control means responsive to said column address signal and said column
address strobe signal to activate a read amplifier means specified by said
column address signal; and
said output buffer including means externally outputting data amplified by
said read amplifier means.
10. The semiconductor memory device according to claim 9, wherein said
control means includes,
transition detecting means coupled to receive said column address signal
for detecting a transition of said column address signal to generate an
address transition signal,
enable means responsive to a deactivation of said column address strobe
signal for generating an amplifier enable signal in a first operation mode
and responsive to said address transition signal for generating said
amplifier enable signal in a second operation mode, and
activation means coupled to receive said column address signal and said
amplifier enable signal and responsive thereto for activating the read
amplifier means specified by said column address signal.
11. The semiconductor memory device according to claim 10, wherein said
control means further comprises,
first counter means responsive to said column address strobe signal for
generating alternatively a first timing signal and a second timing signal,
buffer means responsive to said first timing signal for taking in an
external column address signal,
second counter means responsive to said column address strobe signal for
performing a counting operation with an output of said buffer means as an
initial count,
first gate means coupled to said second counter means for transferring a
count of said second counter means to the output of said buffer means,
second gate means coupled to said buffer means for passing an output signal
received from said buffer means in response to said column address strobe
signal in a first operation mode and for passing said output signal when
received in a second operation mode, and
latching means for latching an output signal of said second gate means to
generate said column address signal.
12. The semiconductor memory device according to claim 11, wherein said
first counter means includes,
a counter for performing a counting operation in response to said column
address strobe signal,
third gate means enabled in response to an initial count from said counter
for generating said first timing signal in response to activation of said
column address strobe signal in the first operation mode, and
fourth gate means enabled in response to a count other than said initial
count from said counter for generating said second timing signal in
response to the activation of said column address strobe signal in said
first operation mode.
13. The semiconductor memory device according to claim 12, further
comprising
precharge means coupled to receive the count of said counter and said
column address strobe signal and a column address transition detecting
signal for precharging inputs of said plurality of read amplifier means in
response to said initial count and activation of said column address
strobe signal in said first operation mode and for precharging the inputs
of said plurality of read amplifier means in response to said column
address transition detecting signal in the second operation mode.
14. The semiconductor memory device according to claim 12, wherein said
first counter means further includes means for invalidating the count from
said counter so that said second timing signal is inhibited from being
generated and said first timing signal is generated in response to the
activation of said column address strobe signal in the second operation
mode.
15. The semiconductor memory device according to claim 9, further
comprising
another control means responsive to a row address strobe signal and said
column address strobe signal for generating an output allowance signal
being active while said row and column address strobe signals are active
in a first operation mode and for generating said output allowance signal
being active in response to said column address strobe signal in a second
operation mode, and wherein
said output buffer includes an output stage enabled in response to said
output allowance signal for outputting externally the data received from
the specified read amplifier means.
16. The semiconductor memory device according to claim 15, wherein said
another control means further includes means for generating a transfer
instruction signal being active in response to said column address strobe
signal in the first operation mode and for constantly activating said
transfer instructing signal in the second operation mode, and said output
buffer further includes means responsive to said transfer instruction
signal being active for transferring data from the specified read
amplifier means to said output state.
17. The semiconductor memory device according to claim 9, wherein each of
said read amplifier means includes means for producing complementary data
onto a first read line and a second read line in accordance with data of a
selected memory cell in a second operation mode and for producing data
corresponding to the data of the selected memory cell onto the first read
line while inhibiting data transfer onto the second read line in a first
operation mode.
18. The semiconductor memory device according to claim 9, wherein each of
the read amplifier means includes means responsive to a multibit test mode
instruction signal for invalidating the column address signal specifying a
read amplifier means, so that said plurality of read amplifier means are
all brought to a selected state to supply data onto a common read bus.
19. A semiconductor memory device having a plurality of memory cells
arranged in a matrix of rows and columns comprising:
first and second read data lines paired together for transmitting data of a
memory cell selected in said memory cell array;
an output buffer coupled to said first and second read data lines for
buffering and externally outputting a received data signal;
operation mode designating signal generating means for generating a signal
designating one of a first operation mode for setting said output buffer
to an output high impedance state in response to deactivation of a column
address strobe signal instructing at least start of column selection and a
second operation mode for maintaining an activation of said output buffer
when said column address strobe signal is inactive;
read amplifier means for amplifying the data of said selected memory cell
into complementary data for transmission onto said first and second read
data lines;
inhibiting means responsive to a signal designating said second operation
mode from said operation mode designating signal generating means to
inhibit transmission of the data signal onto said second read data line
from said read amplifier means; and
an output buffer including means responsive to a signal designating said
first operation mode from said operation mode designating signal
generating means to produce read data in accordance with the data signals
on said first and second data lines, and responsive to a signal
designating said second operation mode from said operation mode
designating signal generating means to produce the read data in accordance
with only the data signal on said first data line, said output buffer
operable to transmit the produced read data onto a data output terminal. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and
particularly to a dynamic semiconductor memory device which operates fast
with a low current consumption. More particularly, the present invention
relates to a semiconductor memory device which has internal circuitry
compatible with semiconductor memory devices in former generations and can
operate fast with a low current consumption.
2. Description of the Background Art
As one of semiconductor memory devices capable of performing fast
operation, there has been known a semiconductor memory device having a
nibble mode, as disclosed, e.g., in "1981 IEEE International Solid-State
Circuits Conference Proceeding", pp. 84-85.
FIG. 50 is a timing chart representing an operation in a nibble mode of a
semiconductor memory device. More specifically, FIG. 50 is a timing chart
representing an operation in data reading in the nibble mode. Operation in
the nibble mode will be described below with reference to FIG. 50.
At time t1, a row address strobe signal ZRAS is set to the low level of the
active state. In response to this transition of row address strobe signal
ZRAS, an address signal Add currently applied is taken in as an X-address
(row address) signal. Memory cells in the row specified by this X-address
are selected. For simplicity, it is assumed that memory cells in one row
are selected and data are read bit by bit. The character "Z" prefixed to
reference characters indicating signals denotes that the signal is active
when it is at the low level.
A clock signal CLOCK is a system clock determining operation timings of a
processing system including the semiconductor memory device. A memory
controller changes the states of the control signals for the semiconductor
memory device according to clock signal CLOCK.
In the state that row address strobe signal ZRAS is maintained at the
active state of the low level, a column address strobe signal ZCAS is
activated to attain the low level at time t2. Thereby, address signal Add
currently applied is taken in as a Y-address signal (column address
signal), and memory cells in four columns (4 bits) among the memory cells
in the selected one row are simultaneously selected. Among the selected
memory cells of 4 bits, data D1 of the memory cell specified by the
Y-address is read in this clock cycle. Thereafter, column address strobe
signal ZCAS is changed from the high level to the low level at times t4,
t6 and t8, whereby remaining data D2, D3 and D4 are successively read from
a data output terminal DQ.
In this nibble mode, data which are read in parallel from memory cells of 4
bits in accordance with the address are externally read out after
parallel/serial conversion in accordance with column address strobe
signals ZCAS. It is therefore not necessary to toggle row address strobe
signal ZRAS for reading data from memory cells, so that a cycle time tPC
in the data read operation can be reduced. In the nibble mode, it is
necessary for reading data D2-D4 to set column address strobe signal ZCAS
to the H-level (high level) and then set the same to the L-level (low
level). However, even in the case where the output enable signal ZOE is
already set to the active state of the low level designating data reading,
data output terminal DQ is set to the high impedance state (Hi-Z) when
column address strobe signal ZCAS is raised to the H-level. In order to
increase a period for outputting valid data, therefore, it is necessary to
increase a time period for which column address strobe signal ZCAS is at
the low level, which increases cycle time tPC and thus prevents fast
reading of data.
In view of the above, a semiconductor memory device having a nibble mode in
which a data valid period for outputting valid data is increased is
proposed, for example, in Japanese Patent Laying-Open No. 59-1100945
(1984). This operation mode is called an EDO (Extended Data Output) mode
or a hyperpage mode.
FIG. 51 is a timing chart representing a hyperpage mode operation. The
hyperpage mode operation will be described below with reference to FIG.
51. FIG. 51 represents the data read operation in which output enable
signal ZOE is set to the low level of the active state.
In this hyperpage mode, similarly to the nibble mode, row address strobe
signal ZRAS and column address strobe signal ZCAS are set to the low level
at times t1 and t2 for taking the X-address and Y-address signals,
respectively, and memory cells of 4 bits are simultaneously selected. Data
of the simultaneously selected memory cells of 4 bits are successively
read in accordance with toggling of column address strobe signal ZCAS. In
this hyperpage mode, however, data output terminal DQ does not attain the
high impedance state even when column address strobe signal ZCAS is
deactivated to attain the high level, so that data which are read in the
current cycle are continuously output. Data output terminal DQ is set to
the high impedance state when both signals ZRAS and ZCAS are deactivated
to attain the high level.
Therefore, this hyperpage mode can implements such an advantage that the
data valid time can be increased even if cycle time tPC is reduced.
Accordingly, if the data valid time in this hyperpage mode is to be equal
to that in the nibble mode, cycle time tPC can be reduced, and thus data
can be read out more rapidly.
As a semiconductor memory device having the cycle time in the data output
operation reduced, there has been disclosed a semiconductor memory device
with a pipeline burst mode (burst EDO mode) shown, e.g., in "NIKKEI BYTE",
April 1995, p. 142.
FIG. 52 is a timing chart representing an operation during data reading of
a semiconductor memory device with the pipeline burst mode. More
specifically, FIG. 52 is a timing chart representing data reading
operation. Referring to FIG. 52, the data read operation in the pipeline
burst mode will now be described below.
At time t1, row address strobe signal ZRAS is set to the low level to take
in an X-address signal X1, and then column address strobe signal ZCAS is
set to the low level to take in a Y-address signal Y1 at time t2. Thereby,
memory cells of 4 bits are selected per data output terminal DQ. In
subsequent ZCAS cycles, i.e., at and after time t3, data of memory cells
of 4 bits are successively output one at each time column address strobe
signal ZCAS is set to the low level. More specifically, data D1, D2, D3
and D4 are output to data output terminal DQ upon lowering of column
address strobe signal ZCAS at times t3, t4, t5 and t6, respectively.
In this pipeline burst mode, data of the memory cell, which is selected by
the column address input at time t2, can be output in the subsequent ZCAS
cycle, i.e., in the cycle during which column address strobe signal ZCAS
attains the low level at time t3. Therefore, cycle time tPC in the data
read operation can be shorter than a time tA after specifying of a column
address to reading of data. Accordingly, data can be output during the
cycle period of clock signal CLOCK, and thus data can be read fast. In
this pipeline burst mode, when another column address is input while data
is being output, memory cell data at four addresses are selected in
accordance with this column address. Thus, data can be continuously read
by successively inputting column addresses for memory cells at the same
row address. Therefore, a large quantity of data can be transferred fast
to a CPU (Central Processing Unit) which is an external processing unit.
Also in this pipeline burst mode, data output terminal DQ is set to the
high impedance state when data reading is completed in response to setting
of both signals ZRAS and ZCAS to the high level.
The semiconductor memory device provided with the fast operation mode
described above is generally used as a main storage unit of a
microprocessor. This semiconductor memory device is generally controlled
by a controller (DRAM controller) which produces the row address signal,
column address signal, row address strobe signal ZRAS, column address
strobe signal ZCAS, output enable signal ZOE and write enable signal ZWE
in accordance with instructions issued from the microprocessor. The
microprocessor and the controller operate in synchronization with clock
signal CLOCK. Therefore, the controller generates the row address signal,
column address signal and signals ZRAS, ZCAS, ZOE and ZWE in
synchronization with clock signal CLOCK.
In order to select memory cells at a row other than that specified by row
address X1 after data are read from four memory cells designated by the
row address (X-address) supplied at time t1 and the column address
(Y-address) Y1 supplied at time t2, it is necessary to maintain row
address strobe signal ZRAS at the high level for a predetermined period
(tRP: RAS precharge time) for initializing internal circuits such as an
internal read circuit in the semiconductor memory device. In order to
select another row, it is necessary to inactivate the selected word line
and select another word line. For this purpose, an internal node of the
semiconductor memory device must be temporarily precharged to a
predetermined potential, so that an RAS precharge time tRP is required for
surely performing this precharging (this semiconductor memory device is a
dynamic semiconductor memory device which operates in accordance with row
address strobe signal ZRAS and column address strobe signal ZCAS).
In FIG. 52, RAS precharge time tRP has a time period (between times t7 and
t8) equal to double the cycle period of clock signal CLOCK. In this case,
therefore, time tRC required for reading data of four memory cells
specified by a different row address is equal to a time period from time
t8 to time t1 and hence equal to 9 cycles of clock signal CLOCK.
It is assumed that, in order to reduce this time tRC (RAS cycle time), row
address strobe signal ZRAS is set to the high level simultaneously with
falling of column address strobe signal ZCAS at time t6 as shown in FIG.
53. The semiconductor memory device is supplied with signals ZRAS and ZCAS
from an external controller. In the controller, circuitry issuing row
address strobe signal ZRAS is different from that issuing column address
strobe signal ZCAS, and a slight time difference occurs between timings of
change of these signals. Delay in signal propagation between the
controller and the semiconductor memory device is caused. In a structure
where the semiconductor memory device is mounted on a printed circuit
board, the signal propagation delay between the controller and the
semiconductor memory device is fixedly determined depending on
characteristics of signal lines on the printed circuit board. In the
semiconductor memory device, if a delay, tdr, of row address strobe signal
ZRAS with respect to clock signal CLOCK is smaller than a delay, tdc, of
column address strobe signal ZCAS with respect to clock signal CLOCK, both
signals ZRAS and ZCAS are at the high level for a certain period. In this
case, read circuitry of the semiconductor memory device is initialized,
and the data output terminal is set to the high impedance state, so that
fourth data D4 cannot be output.
In order to read all data of the four memory cells, the controller sets
column address strobe signal ZCAS to the low level at time t6, and will
set row address strobe signal ZRAS to the high level after a predetermined
time equal to a margin for transition of column address strobe signal ZCAS
elapses. Since the controller is synchronized with clock signal CLOCK, row
address strobe signal ZRAS attains the high level at time t7 as shown in
FIG. 52. This causes a problem that the pipeline burst mode cannot reduce
time tRC.
FIG. 54 schematically shows a structure of a data read portion related to a
data output terminal of 1 bit. In FIG. 54, the read portion includes read
amplifiers RAP0-RAP3 which amplify data M0-M3 of 4 bits of simultaneously
selected memory cells in response to preamplifier enable signal PAE,
respectively, an I/O decoder DEC which generates a control signal for
sequentially selecting the memory cell data of 4 bits in accordance with
Y-address signal CA and column address strobe signal ZCAS, a selector STR
which selects the data amplified by read amplifiers RAP0-RAP3 in
accordance with the select signal sent from I/O decoder DEC, and an output
circuit OBF which buffers the data selected by selector STR and
transmitting the same to data Output terminal DQ.
In the structure for performing the operation in the pipeline burst mode,
read amplifiers RAP0-RAP3 contains registers for storing the amplified
data. Read amplifiers RAP0-RAP3 are provided corresponding to memory cell
data M0-M3 of 4 bits, and are simultaneously activated to amplify memory
cell data M0-M3 upon activation of preamplifier enable signal PAE,
respectively. Since four read amplifiers RAP0-RAP3 simultaneously operate,
a large amount of current Ic flows when read amplifiers RAP0-RAP3 are
operating, as shown in FIG. 55, so that a voltage on a power supply line
Vcc lowers due to a peak value of the large consumed current Ic, resulting
in power supply noises and malfunction of circuits (high/low of data
signal is erroneously determined due to lowered level of the power supply
voltage.)
Also, output circuit OBF shown as a block in FIG. 54 suffers from such a
disadvantage that a trade-off relationship exists between fast reading and
average power consumption as will be discussed below in detail.
FIG. 56 shows specific structures of the read amplifier and output circuit
shown in FIG. 54. The selector is not shown in FIG. 56. Read amplifier RAP
includes differential amplifiers 1900 and 1901 which differentially
amplify data appearing on internal data lines I/O and ZI/O complementary
with each other in response to preamplifier enable signal PAE. Data
transmission lines I/O and ZI/O transmit complementary memory cell data
(M). Complementary output signals sent from differential amplifiers 1900
and 1901 are transmitted to output circuit OBR via read data bus lines
RBUS and ZRBUS, respectively. Parasitic capacitances 1902 and 1903 exist
in read data bus lines RBUS and ZRBUS, respectively.
Output buffer circuit OBF includes a 2-input NAND gate 1904 receiving
output buffer activating signal OEM and a signal on read data line RBUS,
an inverter 1906 inverting the output signal of NAND gate 1904, an
n-channel MOS transistor (insulating gate type field effect transistor)
1908 which is turned on to supply a current from a power supply node Vc to
data output terminal DQ when the output signal of inverter 1906 is at the
high level, an NAND gate 1905 receiving the signal on read data bus line
ZRBUS and output buffer activating signal OEM, an inverter 1907 inverting
the output signal of NAND gate 1905, and an n-channel MOS transistor 1909
which is turned on to discharge data output terminal DQ to ground
potential Vss level when the output signal of inverter 1907 is at the high
level. The operation of the read amplifier and output circuit shown in
FIG. 56 will be described below with reference to a waveform diagram of
FIG. 57.
When preamplifier enable signal PAE is at the low level and thus inactive,
differential amplifiers 1900 and 1901 are also inactive, and both read
data bus lines RBUS and ZRBUS are at the low level. In this state, both
the output signals of NAND gates 1904 and 1905 are at the high level, and
both MOS transistors 1908 and 1909 are turned off by inverters 1906 and
1907. Thus, data output terminal DQ is in the high impedance state.
Upon reading data signals, preamplifier enable signal PAE is maintained at
the active state of the high level for a predetermined period.
Differential amplifiers 1900 and 1901 are activated, and signal potentials
on internal data transmission lines I/O and ZI/O are amplified, so that
potentials on read data bus lines RBUS and ZRBUS change. Differential
amplifiers 1900 and 1901 perform amplification complementarily (a positive
input of differential amplifier 1900 is connected to internal data line
I/O and a positive input of differential amplifier 1901 is connected to
internal data line ZI/O). Therefore, complementary data signals are
transmitted onto read data bus lines RBUS and ZRBUS. In the state that the
potential on read data bus line RBUS is at the high level, when output
buffer activating signal OEM attains the high level, MOS transistor 1908
is made on via NAND gates 1904 and 1906. In this state, the output signal
of NAND gate 1905 is at the high level, and MOS transistor 1909 maintains
the off state. Thereby, data output terminal DQ is charged via MOS
transistor 1908, and thus data signal at the high level is output.
In the state that preamplifier enable signal PAE is active, when a data
signal at the high level is transmitted onto read data bus line ZRBUS, MOS
transistor 1909 is turned on, and MOS transistor 1908 is turned off. In
this case, data output terminal DQ is discharged via MOS transistor 1909,
so that data at the low level is output.
In the structure of the output circuit shown in FIG. 56, both read data bus
lines RBUS and ZRBUS maintain the low level until the data signal is
transmitted onto them. Therefore, even if output buffer activating signal
OEM is activated before activation of preamplifier enable signal PAE as
indicated by broken line in FIG. 57, the output terminal DQ maintains the
high impedance state until the data signal is transmitted onto read data
bus lines RBUS and ZRBUS. When the data signal is transmitted onto read
data bus lines RBUS and ZRBUS, data is output to data output terminal DQ
via output circuit OBF.
In the structure shown in FIG. 56, therefore, output buffer activating
signal OEM can be activated at an earlier timing, so that data can be read
out fast. In the structure shown in FIG. 56, however, parasitic
capacitance 1902 of read data bus line RBUS must be charged when data at
the high level is to be output, and parasitic capacitance 1903 of read
data bus line ZRBUS must be charged when data at the low level is to be
output. Thus, either of parasitic capacitances 1902 and 1903 is charged
each time when data is to be read out, which results in an increase of an
average power consumption (charge/discharge current of parasitic
capacitance per cycle time).
FIG. 58 shows a structure of another data read portion. In FIG. 58, read
amplifier RAP is formed of one differential amplifier 2100. Differential
amplifier 2100 is responsive to preamplifier enable signal PAE to amplify
differentially signals on internal data transmission lines I/O and ZI/O.
Output circuit OBF produces read data in accordance with the data signal on
one read data line RBUS transmitted from differential amplifier 2100.
Output circuit OBF includes an inverter 2102 which inverts a signal
potential on read data bus line RBUS, an NAND gate 2105 receiving the
signal on read data bus line RBUS and output buffer activating signal OEM,
an inverter 2103 receiving the output signal of NAND gate 2105, an
n-channel MOS transistor 2107 for outputting a signal at the high level to
data output terminal DQ in accordance with the output signal of inverter
2103, an NAND gate 2106 which receives the output signal of inverter 2102
and output buffer activating signal OEM, an inverter 2104 which receives
the output signal of NAND gate 2106, and an n-channel MOS transistor 2108
for discharging data output terminal DQ to transmit the signal at the low
level to data output terminal DQ in accordance with the output signal of
inverter 2104.
MOS transistors 2107 and 2108 are turned on when the output signals of
inverters 2103 and 2104 are at the high level, respectively. A parasitic
capacitance 2102 exists in read data bus line RBUS. Now, operation of the
read portion shown in FIG. 58 will be described below with reference to an
operation waveform diagram of FIG. 59. For the sake of illustration, the
following description will be given on the operation of successively
reading memory cell data bit by bit.
A memory cell is selected in response to activation of column address
strobe signal ZCAS, and the selected memory cell data is transmitted onto
internal data transmission lines I/O and ZI/O. When preamplifier enable
signal PAE is at the inactive state of the low level, read data line RBUS
is at the low level. When output buffer activating signal OEM is at the
low level, both NAND gates 2105 and 2106 output the signals at the high
level, so that both MOS transistors 2107 and 2108 are off, and data output
terminal DQ is in the high impedance state.
When preamplifier enable signal PAE attains the high level, differential
amplifier 2100 is activated. It is now assumed that the output signal of
differential amplifier 2100 is at the low level. When the potential on
read data line RBUS is at the low level, the output signal of NAND gate
2106 attains the low level in response to activation of output buffer
activating signal OEM to the high level. Thereby, MOS transistor 2108 is
turned on to discharge data output terminal DQ to the ground potential
level, and data at the low level is read to data output terminal DQ. In
this case, as can be seen from waveforms indicated at I and II in FIG. 59,
read data is transmitted to data output terminal DQ in accordance with
activation of output buffer activating signal OEM.
When differential amplifier 2100 outputs data at the high level onto read
data bus line RBUS in response to activation of preamplifier activating
signal PAE, the following two states selectively occur depending on a
relationship between the change of the potential on read data bus line
RBUS and the activation timing of output buffer activating signal OEM.
When output buffer activating signal OEM is activated after rising of the
potential on read data bus line RBUS shown at I in FIG. 59, read data at
the high level is transmitted to data output terminal DQ in accordance
with activation of output buffer activating signal OEM. On the other hand,
when output buffer activating signal OEM is activated to attain the high
level before change of the potential on read data bus line RBUS as shown
at II in FIG. 59, MOS transistor 2108 is turned on in accordance with
activation of output buffer activating signal OEM, so that data at the low
level is once output, because the potential on read data bus line RBUS is
at the low level at the time of activation of output buffer activating
signal OEM. When the potential on read data bus line RBUS subsequently
changes to the potential corresponding to the selected memory cell data,
MOS transistor 2108 is turned off and MOS transistor 2107 is turned on, so
that data at the high level is output to data output terminal DQ.
In the structure shown in FIG. 58, charging of parasitic capacitance 2101
is required only when data at the high level is to be read, so that the
average current consumption can be made small. However, false data is once
output when data at the high level is read as shown at II in FIG. 59, so
that output buffer activating signal OEM cannot be activated at an earlier
timing, and thus fast reading is impossible.
However, the structure of output circuit shown in FIG. 58 can offer the
following advantage. In such a case that transition to the high level
(transition to the inactive state) of column address strobe signal ZCAS
does not cause the output high impedance state, data read in the last
cycle is continuously output when row address strobe signal ZRAS maintains
the low level, so that data can be read correctly regardless of the timing
relationship between output buffer activating signal OEM and the potential
on read data bus line RBUS as shown at III in FIG. 59.
Generally in semiconductor memory device of a large storage capacity,
memory cells of a plurality of bits are simultaneously tested for rapidly
determining existence of a defective memory cell. In this test operation,
data of the same logic are written into a plurality of memory cells which
are simultaneously selected, and then the data are read from the
simultaneously selected memory cells to determine
coincidence/non-coincidence of the read data, and to determine whether the
memory cells of a plurality of bits are acceptable or not.
FIG. 60 shows a testing structure for one data I/O terminal of a 16-Mbit
DRAM. In the test, one memory block MB is selected, and memory cells M0-M3
of 4 bits are selected in the selected memory block MB. In the test, data
of the same logic are written into memory cells M0-M3 of 4 bits. When the
data are read, a coincidence detector EXR which is activated in response
to a test instruction signal TE determines coincidence/non-coincidence of
logics of the data read from memory cells M0-M3 of 4 bits. When data of
memory cells M0-M3 of 4 bits coincide with each other, it is determined
that memory cells M0-M3 of 4 bits are acceptable. Since the memory cells
of 4 bits are simultaneously tested for one data I/O terminal, the test
can be executed fast.
Selector STR uses 2-bit address CA<1:0> of a column address for selecting a
memory cell of 1 bit from memory cells M0-M3 of 4 bits. A DRAM operable in
a pipeline burst mode can be easily accomplished by employing a structure
which can sequentially select the memory cells to be selected
simultaneously in the above test mode. In a 16-Mbit DRAM with the pipeline
burst mode, therefore, a counter CNTR receives column address bits CA<1:0>
and column address strobe signal ZCAS, and generates a select signal to
selector STR, as shown in FIG. 61.
However, in currently available 64-Mbit DRAMs, a parallel test mode
generally employs 32-bit compression (simultaneous testing of memory cells
of 32 bits). For example, in a 64-Mbit DRAM having a 4-bit word structure,
test is simultaneously effected on memory cells of 8 bits per data I/O pin
terminal. In this case, the degenerated address is standardized as shown
in FIG. 62. In FIG. 62, if the refresh cycle is 8K-refresh (i.e., if
logical word lines are 8K in number), the degenerated addresses are column
address bits CA10, CA9 and CA8 in the case of the 4-bit word structure,
and the degenerated addresses are column address bits CA9 and CA8 in the
case of the 8-bit word structure. If the refresh cycle is 4K-refresh
(i.e., if logical word lines are 4K in number), the degenerated addresses
are column address bits CA11, CA10 and CA9 in the case of the 4-bit word
structure, and the degenerated addresses are column address bits CA10 and
CA9 in the case of the 8-bit word structure.
Here, the "logical word lines" are word lines to be simultaneously
selected, and correspond to rows specified by row address signals.
The degenerated addresses of the 64-Mbit DRAM are address bits to be
simultaneously selected during the test mode of operation.
FIG. 63 schematically shows a structure of a portion corresponding to data
output terminal DQ of one bit in x4-bit structure. Memory block MB is
divided into two, i.e., upper and lower regions depending on column
address bit CA8. In the upper and lower regions of memory block MB, memory
cells M0a-M3a of 4 bits and memory cells M0b-M3b of 4 bits are selected
during the test mode of operation. In the normal operation, memory cells
of 4 bits in only one of these regions are selected in accordance with
column address bit CA8. Selectors STRa and STRb, which select
corresponding memory cells of 4 bits to pass the selected cell data in
accordance with column address bits CA<8> and ZCA<8> are provided
corresponding to the upper and lower regions of memory block MB. Data of
memory cells of 4 bits transmitted from one of selectors STRa and STRb is
sent to a selector STRc. Selector STRc selects a memory cell of 1 bit to
transmit the data toward data output terminal DQ in accordance with 2 bits
CA<10:9> of column address.
In the test operation, data of memory cells M0a-M3a and M0b-M3b are sent to
coincidence detecting circuit EXR, which detects
coincidence/non-coincidence of their logics. In this case, therefore,
column address bits CA<10:8> are used for selecting the memory cell of 1
bit from simultaneously selected memory cells M0a-M3a and M0b-M3b, and
8-bit data is compressed into 1-bit data, so that the degenerated address
is column address bits CA10, CA9 and CA8 in the test operation.
When the pipeline burst mode is to be implemented in the semiconductor
memory device having the above structure, the counter is constructed such
that a signal for selecting a memory cell of 1 bit is applied to selector
STRc in accordance with column address bits CA<10:9>. According to this
structure, a semiconductor memory device potentially operable in the fast
page mode and pipeline burst mode is formed on the same semiconductor
chip, and the structure operating in only one of these modes can be easily
completed by a mode selection circuit.
In this case, the counter address applied from the counter to selector STRc
is column address bits CA<10:9>. Meanwhile, in the case of 16-Mbit DRAM,
the counter address is CA<1:0> as shown in FIG. 61. Therefore, the counter
address for the 64-Mbit DRAM is different from that for 16-Mbit DRAM, so
that there is no pin compatibility therebetween, and thus 64-Mbit DRAM
cannot be used instead of 16-Mbit DRAM.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device
which has address pins compatible with semiconductor memory device in
another generation and can perform fast operation with a low current
consumption.
Another object of the invention is provide a semiconductor memory device
which can perform fast operation with a low current consumption and can
efficiently achieve operation modes of different data output nodes based
on the column address strobe signal.
A semiconductor memory device according to one aspect of the invention
includes a first signal generating circuit responsive to deactivation of a
row address strobe signal instructing a start of row selection for
generating a signal resetting an operation related to selection of a row
in a memory cell array; a delay circuit for delaying the deactivation of
the row address strobe signal by a predetermined time; and a second signal
generating circuit responsive to deactivation of the delayed row address
strobe signal sent from the delay circuit and deactivation of a column
address strobe signal instructing a start of selection of a column in the
memory cell array for generating a signal setting an output buffer
outputting data of the selected memory cell to a data output terminal to
an output high impedance state.
A semiconductor memory device according to a second aspect includes a
column selecting circuit for simultaneously selecting a plurality of
columns in a memory cell array in accordance with a column address signal;
a plurality of read amplifier circuits provided corresponding to the
plurality of selected columns for amplifying and transmitting data of the
memory cells in the corresponding columns to an output buffer; a control
circuit responsive to deactivation of the column address signal and a
column address strobe signal for activating the read amplifier circuits
sequentially in accordance with activation of the column address strobe
signal; and a circuit for externally outputting data amplified by the read
amplifier circuit in synchronization with activation of the column address
strobe signal.
A semiconductor memory device according to a third aspect includes a pair
of first and second read data lines for transmitting complementary data of
a selected memory cell; an output buffer coupled to the first and second
read data lines for buffering received data signals for external
outputting; an operation mode designating signal generating circuit for
generating a signal designating one of a first operation mode for setting
the output buffer to an output high impedance state in response to
deactivation of a column address strobe signal and a second operation mode
for activating the output buffer regardless of an inactive state of the
column address strobe signal; a read amplifier circuit for amplifying the
data of the selected memory cell into complementary data and transmitting
the same onto the first and second read data lines; and an inhibiting
circuit for inhibiting transmission of the data | | |
