Method of producing a single piece package for semiconductor die

What is claimed is:

1. A method for packaging a semiconductor die comprising:

forming a package body with a die mounting location;

forming an interconnect opening through the package body, said opening extending from the die mounting location to a surface of the package body;

forming a pattern of grooves on the surface;

forming an insulating layer in the opening and on the surface;

forming pattern of conductors within the grooves;

mounting the die circuit side down on the die mounting location with a pattern of bond pads on the die accessible through the interconnect opening; and

forming an electrical interconnection between the pattern of bond pads and the pattern of conductors by wire bonding through the interconnect opening.

2. The method as claimed in claim 1 further comprising forming the package body and interconnect opening in a configuration for packaging the die or for packaging a second die having a different pattern of bond pads.

3. The method as claimed in claim 1 further comprising forming a second interconnect opening through the package body and wire bonding through the second interconnect opening to a second pattern of bond pads on the die.

4. The method as claimed in claim 1 further comprising forming a capture groove in the surface and forming a metal bump on the capture groove in electrical communication with a selected conductor.

5. The method as claimed in claim 1 further comprising forming a wire bonding shelf on the surface for wire bonding to the pattern of conductors.

6. The method as claimed in claim 1 wherein the package body comprises silicon.

7. The method as claimed in claim 1 further comprising forming a pattern of bumps on the pattern of conductors, said bumps configured for flip chip mounting the package to a substrate.

8. The method as claimed in claim 1 further comprising aligning the bond pads on the die with the interconnect opening using optical alignment.

9. The method as claimed in claim 1 further comprising aligning the bond pads on the die with the interconnect opening using an alignment fixture.

10. The method as claimed in claim 1 further comprising flip chip mounting the package body to a supporting substrate with the pattern of conductors in electrical contact with a pattern of contact locations on the supporting substrate.

11. The method as claimed in claim 1 further comprising mounting the package body on a supporting substrate in a chip on board configuration with the pattern of conductors wire bonded to a pattern of contact locations on the supporting substrate.

12. The method as claimed in claim 1 wherein forming the package body comprises etching a die cavity and then etching the interconnect opening.

13. The method as claimed in claim 1 wherein forming the pattern of conductors comprises forming a layer of polyimide on the conductors.

14. The method as claimed in claim 1 wherein forming the pattern of conductors comprises a screen printing process.

15. The method as claimed in claim 1 further comprising encapsulating the die on the die mounting location by depositing and curing a material on the die and package body.

16. The method as claimed in claim 1 further comprising depositing and curing a material over the interconnect opening and a wire bonding area.

17. The method as claimed in claim 1 further comprising mounting the package on a supporting substrate in a chip on board configuration with the pattern of conductors wire bonded to a pattern of contact locations on the supporting substrate and then encapsulating the package using a curable material.

18. A method for packaging a semiconductor die comprising:

providing a substrate;

providing the die with a pattern of bond pads having solder bumps formed thereon;

forming a die mounting location on the substrate to form a package body;

forming an opening from the die mounting location to a surface of the package body;

forming a pattern of grooves on the surface of the package body;

forming a pattern of conductors within the grooves;

aligning the bond pads on the die with the opening in the package body;

placing the die circuit side down on the die mounting location; and

electrically connecting the bond pads on the die to the conductors on the package body by reflowing the solder bumps through the opening onto the conductors.

19. The method as claimed in claim 18 further comprising forming an insulating layer on the surface and opening prior to forming the pattern of conductors.

20. The method as claimed in claim 18 further comprising forming the package body and interconnect opening in a configuration for packaging the die or for packaging a second die having a different pattern of bond pads.

21. The method as claimed in claim 18 wherein the substrate comprises silicon.

22. The method as claimed in claim 18 further comprising forming the pattern of conductors by a process selected from the group consisting of metallization, screen printing and sputtering.

23. The method as claimed in claim 18 further comprising forming a pattern of metal bumps on the pattern of conductors for mounting the package in electrical contact with contact locations on a supporting substrate.

24. The method as claimed in claim 18 further comprising encapsulating the die on the die mounting location by depositing and curing a material.

25. The method as claimed in claim 18 further comprising mounting and electrically interconnecting a plurality of dice to the package body.

26. The method as claimed in claim 25 wherein the dice and package body comprise a multi-chip-module.

27. The method as claimed in claim 18 further comprising testing the die following packaging using the package body.

28. A method for packaging semiconductor dice comprising:

providing a silicon wafer;

forming a plurality of packages by etching a plurality of die mounting locations into the wafer, etching a plurality of through openings from a surface of the wafer to the die mounting locations, forming an insulating layer on the surface and sidewalls of the openings, forming a plurality of patterns of conductors on the surface, forming a plurality of grooves on the surface, and forming a plurality of patterns of solder balls within the plurality of grooves in electrical communication with the patterns of conductors;

placing the dice circuit side down on the die mounting locations;

singulating the packages from the wafer; and

electrically connecting bond pads on the dice to the conductors on the packages by wire bonding or solder reflowing through the openings.

29. The method as claimed in claim 28 wherein etching the die mounting locations and openings comprises wet etching with an etchant solution.

30. The method as claimed in claim 28 further comprising forming the packages and openings in a configuration for packaging the dice or for packaging different dice having different patterns of bond pads.

31. The method as claimed in claim 28 wherein forming the conductors comprises a process selected from the group consisting of metallization, screen printing and sputtering.

32. The method as claimed in claim 28 further comprising forming a second pattern of grooves in the surface for and forming the pattern of conductors within the second pattern of grooves.

33. The method as claimed in claim 28 wherein the pattern of grooves is formed such that a groove is proximate to a selected edge of each package.

34. The method as claimed in claim 28 further comprising forming wire bonding shelves in the surface for the conductors.

35. The method as claimed in claim 28 further comprising flip chip mounting at least one package to a supporting substrate.

36. A method for packaging a semiconductor die having a pattern of bond pads comprising:

forming a single piece package body with a die mounting location;

forming an interconnect opening through the package body, said opening extending from the die mounting location to a surface of the package body;

forming a pattern of conductors on the surface;

forming a groove on the surface;

forming metal bumps on the groove in electrical communication with the pattern of conductors;

mounting the die circuit side down on the die mounting location with the pattern of bond pads on the die accessible through the interconnect opening; and

forming an electrical interconnection through the interconnect opening to the pattern of bond pads on the die and the pattern of conductors on the package body.

37. The method as claimed in claim 36 wherein forming the electrical interconnection comprises wire bonding.

38. The method as claimed in claims 36 wherein forming the electrical interconnection comprises reflowing solder bumps formed on the pattern of bond pads.

39. The method as claimed in claim 36 wherein the package body comprises silicon.

40. The method as claimed in claim 36 wherein the package body comprises an electrically insulating glass filled resin.

41. The method as claimed in claim 36 wherein a plurality of dice are mounted to the die mounting location in electrical communication with the pattern of conductors.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and specifically to the packaging of semiconductor dice.

BACKGROUND OF THE INVENTION

Semiconductor dice or chips are typically individually packaged for use in plastic or ceramic packages. This is sometimes referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and full functionality testing of the die.

In general, conventional package designs incorporate several common elements. These common elements include a sealed package enclosure, a die attachment area, bond wires for establishing electrical communication with bond pads on the die, and a lead system for the package. Typically the initial component in the packaging process is a leadframe.

The leadframe supports the die during the packaging process and provides the lead system in the completed package. For example in a conventional process for a plastic package, the dice are initially attached to mounting paddles of the leadframe. During a wire bonding process, the bond pads on the face of each die are electrically connected to the lead fingers of the leadframe by wire bonding. The semiconductor dice are then encapsulated in a molded plastic body and a trim and form operation is used to separate the resultant interconnected packages and to bend the leads of each package into a desired configuration (e.g., DIP, ZIP, SOJ).

Semiconductor dice are also used in unpackaged or bare form to construct multi-chip-modules and multi-chip packages. In this case, bare dice are bonded directly to a supporting substrate such as a printed circuit board. The dice can be flip chip mounted to the substrate or wire bonded in a chip-on-board configuration. The dice in a multi-chip-module are sometimes encapsulated in a curable material using an injection molding, pouring or "glob top" process.

Another type of package is disclosed in U.S. Pat. No. 5,239,198 to Lin et al. Here a multi chip package is fabricated using a substrate formed of a printed circuit board material such as FR4. A pattern of conductors is printed on the substrate and each die is wire bonded to the conductors. A molded package body is then formed over the dice and wire bonds. The multi chip package can be electrically mounted on a printed circuit board using solder balls formed on the pattern of conductors.

One problem with each of these conventional packaging processes is that the packages are relatively complex and therefore difficult to manufacture. The present invention is directed to a method for packaging dice that is simpler and cheaper than a conventional packaging process for dice but which provides protection, heat dissipation and a substantial-lead system for a bare die.

Accordingly, it is an object of the present invention to provide an improved method for packaging bare semiconductor dice.

It is yet another object of the present invention to provide an improved package for a single semiconductor die or multiple semiconductor dice.

It is a further object of the present invention to provide an improved semiconductor package that is low cost, that can accommodate different sizes and types of dice, and that can be formed at the wafer level using semiconductor circuit fabrication techniques.

It is a still further object of the present invention to provides an improved single piece package for semiconductor dice that provides efficient thermal conductivity, low stress, and a good thermal match with a bare die.

Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method for packaging bare semiconductor dice and an improved package for one or multiple semiconductor dice are provided. A package formed in accordance with the invention includes a single piece body having a die mounting location. In addition, the package includes an interconnect opening through the body to the die mounting location. The interconnect opening aligns with bond pads on the die and provides access for electrical interconnection to the die. The package also includes a pattern of conductors formed on an outside surface thereof, which are electrically interconnected to the bond pads on the die. The conductors on the package body terminate in raised solder bumps or wire formed conductors, that provide external mounting and electrical connection points for the package.

In the assembled package, the die is mounted face down on the die mounting location, with the bond pads on the die in alignment with the interconnect opening. Using the interconnect opening for access, the bond pads on the die are interconnected to the pattern of conductors on the package body. A preferred method of electrical interconnection between the die and conductors is wire bonding. However, other interconnect technologies including compressive and non-compressive bonding techniques can also be used. The bonding techniques can include aluminum wedge bonding, TAB bonding or thermal reflow bonding. In addition, the package body can be formed with an interconnect cavity for the electrical interconnection. Furthermore, a curable material can be used to encapsulate the die and the interconnect cavity, or a lid can be used to seal the interconnect cavity.

The package body is preferably formed of silicon but can also be formed of an insulating material such as a resin filled glass fabric (e.g., FR-4). With silicon, a bulk micro machining process of a silicon wafer can be used to form a plurality of package bodies. The dice can then be attached to the silicon bodies which are then singulated from the wafer. The pattern of conductors can be formed using a metallization process (e.g., deposition, patterning, etching) or a screen printing process. The bumps for the conductors can be formed by electrodeposition, screen printing or wire forming processes.

Advantageously the die mounting area and interconnect opening for the package can be made to accommodate different configurations of dice. In addition multiple dice can be mounted in the package to form a multi-chip-module such as an in-line memory module. The assembled package can be flip chip mounted to a supporting substrate such as a printed circuit board (PCB). Alternately, the package can be wire bonded to a supporting substrate in a chip-on-board configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross sectional view of a package formed in accordance with the invention;

FIG. 1A is a schematic cross sectional view of a package formed in accordance with the invention;

FIG. 2 is a schematic perspective view of a package body for the package shown in FIG. 1;

FIG. 2A is a schematic perspective view of an alternate embodiment package body;

FIG. 3A is a schematic cross sectional view of a package formed in accordance with the invention and flip chip mounted to a printed circuit board;

FIG. 3B is a schematic side elevation view of a package formed in accordance with the invention and mounted to a printed circuit board in a chip on board configuration;

FIG. 3C is a schematic side elevation view of a multi-chip-module constructed with packages formed in accordance with the invention;

FIGS. 4A-4E are schematic cross sectional views illustrating a process for forming a package in accordance with the invention;

FIG. 5 is a schematic cross sectional view of a package constructed in accordance with the invention with a lid to protect wire bond areas;

FIG. 5A is a schematic cross sectional view of a package constructed in accordance with the invention with an encapsulant to protect the die and a recess to protect the wire bond areas and conductors;

FIG. 6 is a cross sectional view of a portion of a package constructed in accordance with the invention showing a metallization structure for metal conductors on the package;

FIG. 7 is a schematic perspective view showing a package constructed in accordance with the invention with grooves for metal conductors on the package;

FIG. 8 is a schematic perspective view showing a wafer having etched package bodies constructed in accordance with the invention and semiconductor dice mounted within the package bodies;

FIG. 9 is a schematic cross sectional view of an alternate embodiment package constructed in accordance with the invention with multiple dice;

FIG. 10 is a schematic cross sectional view of an alternate embodiment package constructed in accordance with the invention;

FIG. 11 is a flow diagram of a process for manufacturing packages in accordance with the invention;

FIGS. 12A-12C are schematic cross sectional views illustrating steps in the formation of another alternate embodiment package; and

FIGS. 13A-13B are schematic cross sectional views illustrating a thermal reflow bonding method for interconnecting a die and package in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIGS. 1 and 2, a package 10 constructed in accordance with the invention is shown. The package 10, generally stated includes: a package body 12; a pattern of insulated conductors 14 formed on an outside surface of the package body 12; and a semiconductor die 18 mounted within the package body 12.

The package body 12 is a monolithic structure that can be formed of monocrystalline silicon. By forming the package body 12 of silicon, a coefficient of thermal expansion (CTE) of the package body 12 will closely match the CTE of the semiconductor die 18. A minimum of stress is thus developed between the package body 12 and the die 18 as a result of temperature cycling. In addition, silicon is a good thermal conductor so that the close proximity of the package body 12 to the die 18 provides efficient heat transfer from the die 18.

The package body 12 includes a die mounting location 22 wherein the die 18 is mounted face down (i.e., circuit side down). In the illustrative embodiment the die mounting location 22 is formed as an etched cavity. However, the die mounting location 22 can be formed with tabs or grooves, or can be a flat surface on the package body 12, or can be a pocket enclosed only on two sides. In the illustrative embodiment, the cavity for the die mounting location 22 is sized to be slightly larger than the die. As shown in FIG. 2, the cavity for the die mounting location 22 can be open ended or it can be a pocket enclosed on four sides (not shown) that matches the peripheral configuration of the die 18. The die 18 is mounted face down to the bottom surface of the die mounting location 22. An adhesive layer 23 formed of an epoxy, acrylic, silicone, polyimide or other dielectric material can be used to secure the die 18 to the die mounting location 22. Alternately the adhesive can be omitted, and the die 18 secured to the die mounting location 22 of the package body 12 with the subsequent interconnection method (e.g., wire bonding, aluminum wedge bonding, TAB bonding or thermal reflow bonding).

In the illustrative embodiment, the die 18 includes a row of bond pads 24 (FIG. 1), which are located along the center portion of the die face 25 (FIG. 1) in the manner of a lead over chip (LOC) die. Typically, a die will include many bond pads (e.g., 10-30). The bond pads 24 on the face 25 of the die 18 align with an elongated interconnect opening 20. The interconnect opening 20 is formed in a lower wall 26 (FIG. 1) of the package body 12 and provides access for establishing electrical communication with the die 18. The interconnect opening 20 is thus sized and shaped to provide access to a row of bond pads 24. One continuous interconnect opening 20 can be formed as shown, or multiple interconnect openings which correspond to fewer than all of the bond pads can be formed. In addition, as shown in FIG. 1A, a package 10D can be formed with interconnect openings 20C that align with a die 18A having bond pads 24 formed along the peripheral sides thereof. Other types of die configurations such as area array pads can also be accommodated by the location and shape of the interconnect openings 20.

One advantage of this construction is that a package body 12 formed as shown in FIG. 1, would accommodate different sizes or types of dice having centrally located bond pads 24. This construction permits a universal or generic package body 12 to be used with different configurations of dice as long as the bond pads 24 on the die align with the interconnect opening. In a similar manner the interconnect openings 20C in FIG. 1A could be made generic to accommodate bond pad configurations for different sizes or types of dice.

Prior to the interconnect procedure (e.g., wire bonding), the bond pads 24 on the die 18 must be aligned with the interconnect opening 20. This can be done using optical alignment and a tool such as an aligner bonder used for flip chip bonding. Such an alignment process is disclosed in U.S. patent application Ser. No. 08/338,345, incorporated herein by reference. Alt