A semiconductor device includes a compound semiconductor body having a recess, the recess having a bottom and a hollow, and a refractory metal gate electrode having a lower portion within the hollow. The compound semiconductor body includes a compound semiconductor substrate; a channel layer including a compound semiconductor of a first conductivity type, the channel layer being located on the substrate between the gate electrode and the substrate; first active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor of the first conductivity type located on regions of the substrate sandwiching the recess. Therefore, the controllable region in the channel layer is not adversely affected by a depletion layer produced at the interface between the first active layers and a passivation film, whereby an unwanted reduction in the control speed in the channel layer due to the charging and discharging of carriers in traps at the interface is avoided.
A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.
In the manufacture of a field effect transistor which can improve the breakdown voltage between a gate and a drain and can also prevent a gate lag, an oxide film is formed or wet cleaning is carried out over the semiconductor surface of an inter-source-gate region while a nitride film is formed or dry cleaning is carried out over the semiconductor surface of an inter-gate-drain region, in order that surface traps in the semiconductor surface of the inter-gate-drain region, which is not covered with electrode metal, is greater in number than those in the semiconductor surface of the inter-source-gate region.
The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dummy or sacrificial gate structure. Dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with spacers The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).
A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.
