An arithmetic operation processing unit provided with an external program memory storing a high speed instruction group for executing a specific routine of arithmetic operations which require high speed execution is shown. The arithmetic operation processing unit comprises a start address register for holding a starting address of the specific routine of arithmetic operations and an end address register for holding an end address of the specific routine of arithmetic operations, an FIFO type RAM for storing microcodes obtained by decoding the high speed instruction group. The high speed instruction group stored in the program memory is sequentially read out by a first instruction execution control means from the start address to the end address and decoded into corresponding microcodes when a high speed instruction group decoding instruction is executed. The microcodes thus obtained are then stored in the FIFO type RAM. The microcodes thus stored in the FIFO type RAM are executed one for each clock when a high speed instruction group execution instruction is executed.
An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM1 stored in the external ROM to a high-speed processing region of an internal RAM. When a fetch address AZ1 specified by the MPU indicates a region of the external ROM in which the high-speed processing part PGM1 is stored, the address translation unit translates the fetch address AZ1 to the address AF of a region of the internal RAM corresponding to the high-speed processing part PGM1.
A digital signal processing system which samples an analog voltage, converts the sample to a multi digit base four number, performs a computation with this number, using base four arithmetic, and converts the result back to an analog voltage. This system is comprised of a system an analog to digital converter, an arithmetic logic unit, a digital to analog converter, a system controller, and a memory. The analog to digital converter samples the analog signal and converts the samples into base four numbers. The arithmetic logic performs computations on the samples. The digital to analog converter converts the results of the computations back into analog signals. The system controller controls the operation of the arithmetic logic unit, and the memory stores the command instructions for the system controller. The main advantage of using base four arithmetic instead of binary is much faster through put.
A microprocessor having a microcode unit is provided. Routines comprising DSP functions and instruction emulation routines are stored within a read-only memory within the microcode unit. The routines may be fetched by the microprocessor upon occurrence of a corresponding instruction. For example, DSP functions may be fetched upon occurrence of an instruction defined by the microprocessor to be indicative of a DSP function. The microcode unit provides a library of useful functions. Effectively, the instruction set executed by the microprocessor is increased. A number of methods for defining instructions indicative of a DSP function are contemplated. For example, a subroutine call instruction having a target address within a predefined range of addresses may be defined as indicative of a DSP function. Alternatively, a special subroutine call instruction may be added to the instruction set. Detection of the special subroutine call instruction encoding causes the microprocessor to fetch instructions from the microcode unit. A third alternative is to detect data patterns in data movement instructions and cause instructions to be fetched from the microcode unit upon occurrence of particular data patterns.
