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BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to memory systems in which programmable control parameters are stored in one or more non-volatile data storage units so that each system's parameters can be reprogrammed (by reprogramming each data storage unit) after the
system has been fabricated, and to methods for operating such systems. More specifically, the invention relates to methods for asserting default values of control parameters of memory systems at desired times, regardless of the values of control
parameters stored in non-volatile data storage units of the systems, and to memory systems capable of performing such methods.
2. Background Art
Integrated circuit memory systems have been developed having very large storage capacities. Although attempts have been made to control carefully the fabrication of these systems to increase yield, there invariably are differences in the
characteristics of individual systems, even among systems having the same design. These differences in characteristics are attributable to many factors but are mostly due to processing variations. Thus, memory systems taken from one semiconductor wafer
may differ significantly from those taken from other wafers.
It is usually not possible to characterize a memory system fully until it is completely fabricated. At that point, it is not possible to modify the memory system to take into account the characteristics of the memory. For example, in a flash
memory system it is possible to electrically program, read, and erase the flash cells. The logic state of each cell is set by either programming or erasing the cell, with programming and erasing functioning to alter the threshold voltage of the cell.
When the cell is read, the threshold voltage of the cell is determined in order to establish the logic state of the cell. However, the characteristics of the flash cell, such as the exact manner in which the flash cell responds to programming pulses or
erase pulses, are not easily ascertained. The threshold voltage of the cell of one memory system may change one amount after a single programming pulse is applied and a cell of another supposedly identical memory system may change a different amount
after the same programming pulse is applied to it.
In order to accommodate these variations in memory system characteristics, it is typically necessary to design the system assuming worst case conditions. If so, the overall performance of the system will almost necessarily be reduced.
Many processor systems which operate with an associated memory require a particular memory configuration to operate properly. For example, some systems require a word length of eight bits and others require sixteen bits. Some conventional
memory systems permit the end user to control word size to some degree. However, this somewhat increases the complexity imposed on the end user since the end user must provide the necessary signals to the memory for controlling word length.
As another example, most processor systems look to a certain portion of a memory for boot data at power on. Such boot data is necessary for the processor to function, and the processor is implemented to expect the boot data to be at specific
memory address. Some processors expect the boot data to be at the memory low addresses (bottom boot) and other processors expect the boot data to be at the memory high addresses (top boot).
In order to provide capabilities for different types of processor systems, it is possible to produce a different memory system for each application. However, it is always desirable to limit the number of different memory types which must be
manufactured.
It would be desirable to have a memory system which can be fully characterized after fabrication and wherein operating parameters can then be permanently adjusted (or stably adjusted, until modified) to provide a memory system that is optimized
to take into account the system's particular characteristics. It would also be desirable to provide capability for modifying the configuration (i.e., the operating parameters) of a memory system after fabrication so as to reduce the number of different
types of memories which must be fabricated. Memory systems having these features are described in U.S. patent application Ser. No. 08/508,864 (filed Jul. 28, 1995), entitled "NON-VOLATILE DATA STORAGE UNIT AND METHOD OF CONTROLLING SAME", and U.S.
patent application Ser. No. 08/508,921, entitled MEMORY SYSTEM HAVING PROGRAMMABLE FLOW CONTROL REGISTER, filed Jul. 28, 1995, the contents of each of which are incorporated herein by reference. Preferred embodiments of the present invention pertain
to such memory systems.
It would also be desirable to design memory systems (including but not limited to integrated memory circuits) to have the capability to store (in a non-volatile manner) parameters relating to circuit operation. For example, sometimes an
integrated memory circuit is designed for use in different operating modes. The circuit can be configured at a fabrication facility to operate permanently in only one mode, depending upon the requirements of a particular user. This can be achieved by
modifying the metallization layer of the integrated circuit so that the desired operating mode is achieved. The latter approach has the advantage that the change in metallization is permanent and will not be affected by loss of operating power.
However, this advantage is offset by many disadvantages, including the disadvantage that further changes in the stored operating parameters cannot be made once the metallization has been completed. This is particularly disadvantageous where the value of
the stored parameters is dependent on the characteristics of the integrated circuit which frequently cannot be ascertained until the metallization has been completed. In addition, once the integrated circuit has been packaged, it is frequently
impossible to ascertain the value of the stored parameter.
The present invention also pertains to memory systems capable of storing operating parameters in a non-volatile memory so that such stored parameters can be altered at any time after the fabrication process (e.g., the integrated memory circuits
described in cited U.S. patent applications Ser. No. 08/508,864 and U.S. patent application Ser. No. 08/508,921). In such systems, once a parameter has been stored the parameter is retained even in the event of a loss of power.
In memory circuits having non-volatile storage units (each for storing at least one control parameter), it would be desirable to selectively assert default values of at least some of the control parameters at desired times (e.g., automatically
upon initialization of a test mode of operation of the circuit in response to a "test mode initialization" signal), regardless of the control parameter data stored in the storage units at such times. The present invention provides such a capability, and
permits initialization of internal control registers (and/or analog voltage levels) of an integrated circuit memory system (or other memory system), so that an external program for controlling operation of the system can start from a known condition.
SUMMARY OF THE INVENTION
In a preferred embodiment, the invention is an integrated memory circuit including an array of memory cells arranged in rows and columns, and a control means for controlling memory operations (e.g., programming, reading, and erasing the cells).
Typically, the cells in each row are coupled to a common word line and the cells in each column are coupled to a common bit line. The circuit also includes at least one data storage unit programmed (after fabrication of the circuit) to store control
parameter data determining at least one control parameter for the system. Such control parameter data can, for example, determine control parameters for adjusting the magnitude and duration of voltage pulses applied to the memory during programming and
erasing operations, or parameters for controlling the length of words read out and programmed into the memory.
The circuit also includes a default parameter means for asserting at desired times one or both of: default control parameter data determining default values of at least a subset of the control parameters (regardless of the control parameter data
stored in the data storage units); and at least one default voltage level (in place of an otherwise asserted voltage, e.g., an analog reference voltage). Typically, such default data (or default voltage levels) are asserted during a test mode of the
circuit in response to a test mode initialization or control signal from the control means. In preferred embodiments, the default data (or default voltage levels) are asserted during a test initialize mode in response to a test mode initialization
signal from the control means, to permit initialization of internal control registers (and analog voltage levels) of the memory system so that an external program for controlling test mode operation of the system can start from a known condition. In
some such preferred embodiments, the default parameter means responds to the test mode initialization signal by asserting a default value of a control parameter (regardless of the content of data in a storage unit corresponding to the control parameter),
and also by asserting a default analog voltage level (in place of a reference voltage otherwise asserted by the system).
More generally, other embodiments of the invention are methods for asserting default values of control parameters of memory systems at desired times during system operation such as during a test initialize mode (regardless of the values of
control parameter data stored in storage units of the systems) or methods for asserting default voltage values (analog or digital values) at desired times during operation of such systems (such as during a test initialize mode), and memory systems
capable of performing such methods.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a memory system which can be modified to implement the present invention.
FIG. 2 is an overall block diagram of a memory system in accordance with the present invention, which includes circuit 17A containing a non-volatile data storage unit for storing control parameter data used for,control of addressing polarity, and
non-volatile data storage unit 14A for storing control parameter data used for controlling word length.
FIG. 3 is a schematic diagram of part of the FIG. 2 system showing details of circuitry (including non-volatile data storage unit 14A) for control of word length based upon a stored control parameter.
FIG. 4 is a schematic diagram of part of the FIG. 2 system showing circuit 17A (including non-volatile data storage unit 14B) for controlling addressing polarity based upon a stored control parameter.
FIGS. 5A and 5B are a flow chart showing operation of the memory system state machine.
FIG. 6 is a schematic diagram of a data storage unit used for storing control parameter data.
FIG. 7 is a timing diagram illustrating various functions that can be carried out by the data storage unit of FIG. 6.
FIG. 8 is a block diagram of a circuit used for detecting when the FIG. 2 system has been placed in a test mode and for determining which test mode has been detected, which includes a preferred embodiment of the default parameter means of the
invention.
FIG. 9 is a block diagram of a variation on the FIG. 8 circuit, which includes an alternative embodiment of the default parameter means of the invention.
DETAILED DESCRIPTION OF THE INVENTION
Many conventional memory chips operate in either a test mode in which input/output ("I/O") pads are connected directly to an array of memory cells, or a "normal" (or "active") mode in which the I/O pads are connected through buffer circuitry to
the array of memory cells. In the latter ("normal") mode the chip can perform read/write operations in which data is written to selected ones of the cells through an input buffer (or data is read from selected ones of the cells through an output
buffer).
FIG. 1 is a simplified block diagram of a conventional memory chip (integrated circuit 3) capable of operating in a normal or test mode. Memory chip 3 of FIG. 1 includes at least one I/O pad 30 (for asserting output data to an external device or
receiving input data from an external device), I/O buffer circuit 10 for I/O pad 30, test mode switch M1, address buffers A0 through Ap for receiving memory address bits from an external device, row decoder circuit (X address decoder) 12, column
multiplexer circuit (Y multiplexer) 14, memory array 16 (comprising columns of nonvolatile memory cells, such as column 16A), pad 90, switch 121 connected between pad 90 and other components of chip 3, and control unit 29. Each of address buffers A0
through Ap includes an address bit pad for receiving (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym.
I/O buffer circuit 10 includes a "write" branch and a "read" branch." The write branch comprises input buffer 18. The read branch comprises sense amplifier 19 and output buffer 20.
In the normal operating mode of chip 3, control unit 29 can cause chip 3 to execute a write operation in which it receives data (to be written to memory array 16) from an external device at I/O pad 30, buffers the data in the write branch, and
then writes the data to the appropriate memory cell. Also in this normal operating mode, control unit 29 can cause chip 3 to execute a read operation in which it amplifies and buffers data (that has been read from array 16) in the read branch, and then
asserts this data to I/O pad 30.
Although only one I/O pad (pad 30) is shown in FIG. 1, typical implementations of the FIG. 1 circuit include a plurality of I/O pads, and each I/O pad is buffered by an I/O buffer circuit similar or identical to circuit 10. For example, one
implementation of the FIG. 1 circuit includes eight I/O pads, eight buffer circuits identical to circuit 10, one line connected between the output of the output buffer 20 of each buffer circuit and one of the I/O pads (so that eight data bits can be read
in parallel from buffers 20 to the pads), and one line connected between the input of the input buffer 18 of each buffer circuit and one of the I/O pads (so that eight data bits can be written in parallel from the pads to buffers 18). Each I/O pad
(including I/O pad 30) typically has high impedance when the output buffer is not enabled.
Each of the cells (storage locations) of memory array circuit 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index output determined by circuit 14). Each column of cells of memory array 16
(e.g., column 16A of FIG. 1) comprises "n" memory cells, each cell implemented by a floating-gate N-channel transistor. The drains of all transistors of a column are connected to a bitline, and the gate of each of the transistors is connected to a
different wordline, and the sources of the transistors are held at a source potential (which is usually ground potential for the chip during a read or programming operation). Each memory cell is a nonvolatile memory cell since the transistor of each
cell has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of the N-channel transistors) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating
gate determines a data value that is stored "semipermanently" in the corresponding cell. In cases in which each of the N-channel transistors is a flash memory device, the charge stored on the floating gate of each is erasable (and thus the data value
stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
In response to address bits Y0-Ym, circuit 14 (of FIG. 1) determines a column address which selects one of the columns of memory cells of array 16 (connecting the bitline of the selected column to Node 1 of FIG. 1), and in response to address
bits X0-Xn, decoder circuit 12 (of FIG. 1) determines a row address which selects one cell in the selected column.
The function of switch M1 in FIG. 1 is to switch chip 3 between its test mode and its normal operating mode. Conventionally, switch M1 is an NMOS transistor whose gate receives a control signal ("Test Mode Enable") from internal control logic
within control unit 29. The source and drain of M1 are connected in series with I/O pad 30 and circuit 14. Switch M1 operates as follows in response to the control signal:
M1 is "on" when Test Mode Enable is high (when the value of Test Mode Enable triggers the "test" mode of FIG. 1), and thus M1 functions as a pass transistor which passes a signal (a "test" signal) indicative of test data to be written to or read
from a selected cell of array 16 (e.g., a current signal indicative of test data read from the selected cell) between its source and drain (and thus between I/O pad 30 and the selected cell of array 16). If buffers 18 and 20 of circuit 10 are disabled
when M1 is on, the test signals pass through M1 but not through circuit 10; and
M1 is "off" when Test Mode Enable is low (when the value of Test Mode Enable triggers the "normal" operating mode of FIG. 1), so that signals (indicative of data to be written to memory array 16) provided from an external device to I/O pad 30 are
buffered in input buffer 18 and then asserted to memory array 16, or signals (indicative of data read from memory array 16) are asserted from memory array 16 to sense amplifier 19, amplified in amplifier circuit 19, and then buffered in output buffer 20
and asserted to I/O pad 30. Typically, the "low" value of Test Mode Enable is ground potential.
In the normal operating mode of FIG. 1 (with M1 "off"), the FIG. 1 circuit executes a write operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to decoder circuit 12, and each of address buffers An+1 through Ap
asserts one of bits Y0-Ym to circuit 14. In response to these address bits, circuit 14 determines a column address (which selects one of the columns of memory cells of array 16, such as column 16A), and circuit 12 determines a row address (which selects
one cell in the selected column). In response to a write command supplied from control unit 29, a signal (indicative of data) present at the output of input buffer 18 (which has been enabled by the appropriate level of the control signal "DATA DRIVER
ON") is asserted through circuit 14 to the cell of array 16 determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffer 20 is disabled (in response to an appropriate level of control signal
OUTPUT ENABLE).
A data latch (not shown in FIG. 1) is typically provided between input buffer 18 and I/O pad 30 for storing data (to be written to a memory cell) received from I/O pad 30. When the latched data is sent to input buffer 18, input buffer 18
produces a voltage at Node 1 which is applied to the selected memory cell. Input buffer 18 is typically implemented as a tri-statable driver having an output which can be placed in a high impedance mode (and thus disabled) during a read operation.
Input buffer 18 is disabled by asserting (to input buffer 18) an appropriate level of the control signal DATA DRIVER ON. In some implementations, the functions of the latch and input buffer 18 are combined into a single device.
In the normal operating mode (with M1 "off"), the FIG. 1 circuit executes a read operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to address decoder circuit 12, and each of address buffers An+1 through Ap
asserts one of bits Y0-Ym to circuit 14. In response to these address bits, circuit 14 asserts a column address to memory array 16 (which selects one of the columns of memory cells, such as column 16A), and circuit 12 asserts a row address to memory
array 16 (which selects one cell in the selected column). In response to a read command supplied from control unit 29, a current signal indicative of a data value stored in the cell of array 16 (a "data signal") determined by the row and column address
is supplied from the drain of the selected cell through the bitline of the selected cell and then through circuit 14 to sense amplifier 19. This data signal is amplified in amplifier 19, buffered in output buffer 20 (which is enabled by an appropriate
level of control signal "OUTPUT ENABLE"), and finally asserted at I/O pad 30. During such read operation, input buffer 18 is disabled (in response to an appropriate level of control signal DATA DRIVER ON).
Chip 3 of FIG. 1 also includes a pad 90 which receives a high voltage V.sub.pp from an external device, and a switch 121 connected to pad 90. During some steps of a typical erase or program sequence (in which the cells of array 16 are erased or
programmed), control unit 29 sends a control signal to switch 121 to cause switch 121 to close and thereby assert the high voltage V.sub.pp to various components of the chip including X decoder 12. Voltage V.sub.pp is higher (typically V.sub.pp =12
volts) than the normal operating mode supply voltage (typically V.sub.cc =5 volts or V.sub.cc =5.5 volts) for the MOS transistors of chip 3.
When reading a selected cell of array 16, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in sense amplifier 19. If the cell is in a programmed state, it will conduct a second
current which is converted to a second voltage in sense amplifier 19. Sense amplifier 19 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 0 or 1, respectively) by comparing the voltage
indicative of the cell state to a reference voltage. The outcome of this comparison is an output which is either high or low (corresponding to a digital value of one or zero) which sense amplifier 19 sends to output buffer 20, which in turn asserts a
corresponding data signal to I/O pad 30 (from which it can be accessed by an external device).
During the test mode, input buffer 18, sense amplifier 19, and output buffer 20 are all disabled (in response to appropriate levels of their respective control signals DATA DRIVER ON, SENSE AMPLIFIER ENABLE, and OUTPUT ENABLE, which are generated
by control unit 29).
During a write operation in the normal operating mode, control signal SENSE AMPLIFIER ENABLE disables sense amplifier 19. During a read operation in the normal operating mode, circuit 14 is employed to access the desired cell in array 16 and
control signal SENSE AMPLIFIER ENABLE enables sense amplifier 19 so that sense amplifier 19 can determine the state of the selected cell as described.
It is important during a write operation (in the normal operating mode) to provide the wordline of the selected cell with the proper voltage and the drain of the selected cell with the appropriate voltage level (the voltage determined by the
output of input buffer 18), in order to successfully write data to the cell without damaging the cell.
FIG. 2 is a block diagram of a flash memory chip 103 which is an integrated circuit memory system that is a variation on memory chip 3 of FIG. 1. Chip 103 performs essentially all the same functions as does chip 3, but includes additional
elements (to be described) so as to embody the present invention. The components of flash memory system 103 which correspond to components of memory chip 3 of FIG. 1 are identified by identical reference numerals in FIGS. 3 and 1. Memory array 16 of
system 103 consists of flash memory cells arranged in rows and columns. The individual cells (not depicted) are addressed by eighteen address bits (A0-A17), with nine bits being used by X decoder circuit 12 to select the row of array 16 in which the
target cell is located and the remaining nine bits being used by Y decoder circuit 13 (of Y-multiplexer 14) to select the appropriate column of array 16.
Internal state machine 120 of control unit 29 of chip 103 controls detailed operations of chip 103 such as the various individual steps necessary for carrying out programming, reading and erasing operations. State machine 120 thus functions to
reduce the overhead required of a processor (not depicted) typically used in association with chip 103.
Memory operations, including programming, reading, and erasing can be initiated in various ways. For all operations, the chip enable signal CE must be made active (low). To perform a read operation, write enable signal WE must be made inactive
(high). For a write operation, signal WE must be made active (low). In order to reduce the likelihood of accidental modification of data, erase and program operations require receipt of two consecutive commands that are processed by command execution
logic unit 124. The program and erase commands are provided by the associated processor to data I/O pins DQ0-DQ7, forwarded to input buffer 122, and then forwarded to the command execution logic unit 124 for processing.
If memory array 16 is to be erased (typically, all or large blocks of cells are erased at the same time), the processor causes the Output Enable OE pin to be inactive (high), and the Chip Enable CE and Write Enable WE pins to be active (low).
The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins DQ0-DQ7, typically called an Erase Setup command (one of I/O pins DQ0-DQ7 corresponds to I/O pad 30 of FIG. 1). This is followed by issuance of a second eight bit command D0H
(1101 0000), typically called an Erase Confirm command. Two separate commands are used to reduce the possibility of an inadvertent erase operation.
The commands are transferred to data input buffer 122 (input buffer 18 of FIG. 1 corresponds to a component of buffer 122 which receives one bit of each command) and the commands are then transferred to command execution logic unit 124 of control
unit 29. Logic unit 124 then instructs state machine 120 to perform all the numerous and well known steps for erasing array 16.
Once an erase sequence is completed, state machine 120 updates an 8 bit status register 126, the contents of which are transferred to data output buffer 128A which is connected to data I/O pins DQ0-DQ7 of the memory system (output buffer 18 of
FIG. 1 corresponds to a component of buffer 128A which receives one bit from register 126). The processor periodically polls the data I/O pins to read the contents of status register 126 in order to determine whether an erase sequence has been completed
and whether it has been completed successfully.
It is contemplated that in preferred embodiments of a memory chip implementing the invention, each memory cell in each memory array of the chip (e.g., array 16) is a nonvolatile memory cell such as a flash memory cell.
Generation of the control signals needed for entry into each of the test modes of the inventive memory chip is preferably accomplished in the manner described in U.S. patent application Ser. No. 08/508,924, entitled "Memory System Having
Internal State Monitoring Circuit," filed on Jul. 28, 1995, and U.S. patent application Ser. No. 08/386,704 entitled "Apparatus for Entering and Executing Test Mode Operations for Memory," filed Feb. 10, 1995, the disclosures of which are hereby
incorporated in full into the present disclosure by reference. Control unit 29 preferably includes the circuitry for generating the control signals needed for entry into each test mode (in response to signals received at external pads of the chip), and
the circuitry for generating the control signals needed for controlling operation of the chip during execution of some test mode operations and for controlling operation of the chip in the normal operating mode.
The operation of chip 103 of FIG. 2 can be altered by stored control parameters CPN (e.g., parameter CP2 determined by data stored in data storage unit 14B of chip 103, shown in FIG. 4) which can themselves be changed any time after the chip has
been fabricated. Different types of exemplary operations which can be controlled in this manner will next be described.
Word Length (Bus Size)
Chip 103 of FIG. 2 can be permanently configured using a stored programmable control parameter CP1 to provide either a total of 256K of eight bit words or a total of 128K of sixteen bit words. The state of this control parameter is determined by
a bit stored in non-volatile data storage unit 14A (shown in FIG. 3). Data storage unit 14A can be of the type described below with reference to FIG. 6 and in above-cited U.S. application Ser. No. 08/508,864 (filed on Jul. 28, 1995), which is a
non-volatile data storage unit having flash memory cells which permit a control parameter, such as parameter CP1, to be programmed to a desired state after fabrication of the memory system has been completed.
Control parameter CP1 is thus used to control the size of the memory system data bus, that is, the size of the data words of the memory. In the present example, the size is either an eight bit word or a sixteen bit word. The output of storage
unit 14A is connected (through AND gate 453, discussed below) to I/O control logic unit 15 which controls the memory system input and output functions so as to provide either sixteen bit or eight bit word operation.
In the event the memory has been configured to read and write eight bit words (i.e., when control parameter CP1 is set to indicate eight bit words), a total of nineteen address bits are provided to chip 103 by the associated processor. Eighteen
bits of address are forwarded to address terminals A0-A17 and then to address buffer (and latch) 17. The last address bit is provided to the A-1/DQ15 terminal (shown at the right side of FIG. 2), which is used as the least significant address A-1 when
the memory is in an "eight bit word" configuration and as bit DQ15 of the sixteen bit data I/O (DQ0-DQ15) when the memory is in a "sixteen bit word" configuration.
Each addresses A0-A17 is forwarded to X decoder 12 and Y decoder 13 to select one sixteen bit word out of array 16. When a read operation is being performed, the sixteen bits read out of array 16 are forwarded to data multiplexer 124. I/O
control logic unit 15 directs input buffer 122B to forward address A-1 to multiplexer 124, which responds by selecting either the lower or higher of the eight bit words of the sixteen bits read from memory, depending on the state of address bit A-1. The
selected eight bits of output data are forwarded to output buffer 128A which, in turn, couples the output data to memory terminals DQ0-DQ7. In this mode (eight bit mode), the outputs of data output buffer 128, which are connected to terminals DQ8-DQ14,
are set to a high impedance state.
If a memory program operation is to be performed (to write eight bits to memory 16) when the memory system is in the eight bit mode, the associated processor provides the eighteen most significant bits of address to terminals A0-A17 and the least
significant bit to terminal DQ15/A-1. The eight bits of data to be programmed at that address are forwarded by the processor to terminals DQ0-DQ7 and then to data input buffer 122. The eight bits of data are then fed to input data latch/multiplexer 130
which selects the eight bits of data from input buffer 122 to be written to either the upper or lower half of the sixteen bits provided to Y select gate unit 14, based upon address A-1.
The eighteen bits of address A0-A17 are used by X decoder 12 and Y decoder 13 to select a sixteen bit word in array 16. Latch/multiplexer 130 further functions to force the deselected eight bits of its output to a disabled state so these bits
will not be programmed. Thus, either the upper or lower half of the sixteen bit word addressed by decoders 12 and 13 will be programmed with the eight bits of data provided by latch/multiplexer 130. The deselected half will not be programmed.
In the event control parameter CP1 is set to indicate sixteen bit (rather than eight bit) words, the associated processor need provide only eighteen bits of address to chip 103. These address bits are applied to terminals A0-A17. If a read
operation is to be performed, the eighteen bits of address are used by X decoder 12 and Y decoder 13 to select a sixteen bit word in array 16. Eight bits of the word are forwarded to multiplexer 124 which will forward these bits to output buffer 128A
then to terminals DQ0-DQ7. An additional seven bits of the data read from array 16 are forwarded to output buffer 128 and then to terminals DQ8-DQ14. The sixteenth data bit DQ15 of the word is forwarded to output buffer 128B and then to dual function
terminal DQ15/A-1.
In the event a memory program operation is to be performed when the system is in the sixteen bit mode, the eighteen address bits provided by the associated processor to terminals A0-A17 will select a sixteen bit word of array 16 to be programmed. The associated processor then forwards the sixteen bits to be programmed to terminals DQ0-DQ7, DQ8-DQ14, and DQ15/A-1. Fifteen of the data bits are received by input buffers 122 and 122A. The sixteenth bit is received by input buffer 122B. The outputs
of buffers 122, 122A, and 122B are fed to latch/multiplexer 130 and then forwarded to Y select gates unit 14 to be programmed into the memory location selected by the eighteen address bits.
Additional details regarding the word size control feature of chip 103 of FIG. 2 will be described with reference to FIG. 3 (with reference to a read operation). Data storage unit 14A stores a bit which determines the value of word size control
parameter CP1. A CP1 value of "1" indicates a word size of eight bits; a value of "0" indicates a word size of sixteen bits. As previously noted, signal CE is made active (low) for any memory system operation, and signal OE is made active (low) for a
memory read operation. As shown in FIG. 3, signals CE and OE are buffered respectively by circuits 38 and 40 (which are elements of I/O control logic unit 15 of FIG. 2), and the outputs of circuits 38 and 40 are fed to the inputs of NOR gate 42. The
output of gate 42 is inverted by inverter 44, with the output of inverter 44 functioning as an enable signal for data output buffer 128A. Thus, when signals CE and OE are both active, the low signal out of inverter 44 will cause outputs DQ0-DQ7 of
output buffer 128A to be active. When either signal CE or OE is inactive, the output of buffer 128A goes to an inactive or high impedance state.
Still with reference to FIG. 3, the output of inverter 44 is also connected to an input of NOR gate 46. The other input of gate 42 is connected (through gate 352, to be described with reference to FIG. 9) to the output of data storage unit 14A
for receiving a data signal representing the value of control parameter CP1. The output of gate 46 is inverted by inverter 48 which is coupled to the enable input of output buffer 128B and output buffer 128. When a read operation is being performed and
when CP1 is a "1" indicating eight bit word length, both buffers 128 and 128B are disabled so that their outputs will be at a high impedance. Thus, eight bits of data will be provided by buffer 128A, as previously described. When CP1 is a "0", thereby
indicating a sixteen bit word, all three buffers 128A, 128 and 128B are enabled so that all sixteen bits can be output therefrom.
Another aspect of operation of chip 103 (of FIG. 2) that is controlled by parameter CP1 pertains to sense amplifier block 33. Block 33 comprises a total of sixteen sense amplifiers, which are used to implement memory read operations, and also in
program verification and in erase verification. As can be seen from FIG. 3, when signal CE is active (low), eight of the sense amplifiers, those associated with DQ0-DQ7, are made active in response to the high ("1") output of inverter 52. As also
apparent from FIG. 3, the output of storage unit 14A is fed to inverter 50, the output of inverter 50 is fed to one input of NAND gate 54, the output of inverter 52 is fed to the other input of gate 54, and the output of gate 54 is inverted by inverter
56. Accordingly, when CP1 is set to a "1" indicating eight bit operation, the output of inverter 56 is a "0" thereby causing the sense amplifiers associated with DQ8-DQ15 to be disabled. When CP1 is a "0" indicating sixteen bit operation (and CE is
low), the output of inverter 56 is a "1" and all of the sixteen sense amplifiers are enabled.
Top/Bottom Addressing
As shown in FIG. 2, memory array 16 is divided into several blocks of memory cells. The system is implemented so the memory can be erased in blocks rather than by bulk erasure (in which the entire memory is erased). Among the blocks is one
(block 16A) of the type commonly referred to as a boot block. Boot block 16A is intended to contain the kernel code used to initialize the system at power on. Typically, boot block 16A is hardware protected so that it cannot be erased unless special
steps are taken.
At power on, the processor associated with chip 103 is typically automatically directed to read the data stored in boot block 16A so that chip 103 can be initialized. Some processors will attempt to start reading of the boot block data at
address 3FFFF(H) (A0-A17 are all "1") and other processors will attempt to start reading the boot block data at address 00000(H) (A0-A17 are all "0"). These two approaches are sometimes called top and bottom addressing, respectively.
By writing control parameter data into a non-volatile data storage unit, a memory system (such as chip 103 of FIG. 2) can be configured after fabrication to perform either top or bottom addressing. This eliminates the necessity of fabricating
both types of memory systems. FIG. 4 is a more detailed diagram of a portion of chip 103 showing the manner in which the system is configured to provide either top or bottom addressing after fabrication, in response a control parameter CP2 determined by
a single bit stored in unit 14B.
With reference to FIG. 4, parameter CP2 is stored in non-volatile programmable data storage unit 14B (included in chip 103 but not shown in FIG. 2). Storage unit 14B can have identical design to that of storage unit 14A which stores parameter
CP1. If CP2 is a "0", the external addresses A0-AN output from circuit 17 are left unchanged. Thus, if the processor initially looks for boot block data to begin at address 00000 (H) and that is the internal address of the boot block, no changes are
made to the external addresses, and the internal addresses applied to the X and Y decoders 12, 13 are the same as the external addresses output from circuit 17. The parameter CP2 would also be a "0" if the processor initially looks at address 3FFFF(H)
and that is, if fact, the internal address of boot block 16A.
If the processor initially looks at address 3FFFF(H) for the boot block data and the actual boot block is located beginning at 00000(H), then the bit stored in unit 14B determines parameter CP2 to be a "1". The same would be true if the initial
processor address is 00000(H) and the actual starting address is 3FFFF(H).
The circuitry shown in FIG. 4 includes one XOR (exclusive OR) gate 58 for each of the "N" external address bits A0-AN. Address bits A0-AN are forwarded to address buffer/latch 17 and each address bit is then asserted from circuit 17 to an input
of a different XOR gate 58. The other input of each XOR gate 58 is connected to data storage unit 14B in which the data determining parameter CP2 is stored. If CP2 has been programmed to a "0", XOR gates 58 will simply forward the external addresses to
X and Y decoders 12, 13 (as described above). However, if CP2 has been programmed to a "1", XOR gates 58 will invert the external addresses output from circuit 17 in order to create internal addresses that are asserted to X and Y decoders 12, 13.
Sense Amplifier Reference Voltage
As discussed above, the sense amplifiers represented by block 33 of FIG. 2 are used in various memory functions, such as memory read operations in which the programmed state of cells in array 16 is ascertained. The sense amplifiers are also used
to verify proper programming of the cells and to verify proper erasure of the cells. In all these operations, a voltage is developed which is indicative of current flow through each cell being sensed. That sensing voltage is compared to a reference
voltage by the sense amplifier. Typically, one reference voltage used in read operations and program verify operations, and another reference voltage is used in erase verification operations.
Because some embodiments of the invention control levels of reference voltages (during test mode operation of a memory system such as chip 103), further description of the way in which chip 103 generates and uses reference voltages may be
helpful. With reference to FIG. 2, memory system 103 contains control unit 29, which in turn includes internal state machine 120, command execution logic 124, other elements shown in FIG. 2, and typically also additional elements (to be discussed) not
shown in FIG. 2 for simplicity. State machine 120 controls detailed operations of the system, such as the various individual steps necessary for carrying out programming, reading and erasing operations. State machine 120 thus functions to reduce the
overhead required of the processor (not depicted) typically used in association with system 103.
If memory cell array 16 is to be erased (either in bulk or by block), the associated processor will cause the output enable OE pin to be inactive (high), and the chip enable CE and write enable WE terminals to be active (low). The processor then
issues the above-described Erase Setup and Erase Confirm commands.
The commands are transferred to data input buffer 122 and then transferred to command execution logic unit 124. Logic unit 124 then instructs state machine 120 to perform all of the numerous and well known steps for erasing array 16. Once the
erase sequence is completed, state machine 120 updates 8 bit status register 126, the contents of which are transferred to through multiplexer 124 to data output buffer 128A which is connected to data I/O terminals DQ0-DQ7 of chip 103.
FIGS. 5A and 5B are a flow chart showing a typical erase sequence as it is carried out by state machine 120. It should be understood that during any erase operation, there is a possibility that one or more cells of array 16 will become what is
termed "overerased." The objective of the erase sequence is to erase all the cells of array 16 so that the threshold voltages are all within a specified voltage range (typically a small positive voltage range such as +1.5 to +3.0 volts). If the erased
cells fall within this range, the cell to be read (the selected or target cell), will produce a cell current in a read operation. The presence of cell current flow indicates that the cell is in an erased state (logic "1") rather than a programmed state
(logic "0").
Cell current is produced in an erased cell because the voltage applied to the control gate, by way of the word line from the array connected to the X decoder 12, exceeds the threshold voltage of the erased cell by a substantial amount. In
addition, cells which are not being read, the deselected cells, are prevented from producing a cell current even if such cells have been erased to a low threshold voltage state. By way of example, for cells located in the same row as the selected cell,
by definition, share the same word line as the selected cell. However, the drains will be floating thereby preventing a cell current from being generated. Deselected cells in the same column will not conduct cell current because the word lines of such
deselected cell are typically grounded. Thus, the gate-source voltage of these cells will be insufficient to turn on these deselected cells even if they are in an erased state.
Once array 16 has been erased, the vast majority of cells will have a proper erased threshold voltage. However, it is possible that a few of the cell, or even one, may have responded differently to the erase sequence and such cells have become
overerased. If a cell has been overerased, the net charge on the floating gate will be positive. The result will be that the threshold voltage will be negative to some extent. Thus, when the word line connected to such overerased deselected cells is
grounded, the deselected cells will nevertheless conduct current. This current will interfere with | | |
