A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes. Source/drain regions are formed in the second well self-aligned with the stacks as well as spacer dielectric structures formed adjacent to the sidewalls of the stacks. A third doped polysilicon layer patterned into raised bitlines overlies source/drain regions.
A method for fabricating compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.
An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 74 (e.g. a well) formed in the substrate having a first conductivity type, a second region 84 below the first region 74 having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the well. The trench 70 is filled with a non-conductive material 71 that forms a frame around the transistor, whereby soft errors due to electron-hole pairs caused by ionizing radiation in the frame are substantially eliminated.
A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks typically consist of the following layers: silicon nitride (310), tungsten (320), titanium nitride (330), and polysilicon (340). The process includes one step for each of the four layers in the gate stack, and one step to ash the photoresist. These five process steps can preferably be performed in four separate chambers on a cluster tool platform. The innovative etch process of the present invention fabricates gates with lengths of 0.25 microns and below with excellent profile, excellent linewidth uniformity across the wafer, and minimal loss of the gate oxide.
A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.
