Manufacture of semiconductor device with ashing and etching

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including the step of forming a contact hole passing through an insulating film and reaching the surface of a semiconductor substrate.

2. Description of the Related Art

A wiring is formed over a semiconductor substrate made of Si or other semiconductors after active regions such as transistors and resistors are formed in the semiconductor substrate. In the general case, the surface of the semiconductor substrate is covered with an insulating film, a contact hole is formed in the insulating film so as to reach the electrode contact area of the active region, and a wiring layer is formed on the insulating film.

In forming a contact hole, a resist pattern is generally formed on the insulating film, and the insulating film is etched by using the resist pattern as an etching mask. Anisotropic etching such as reactive ion etching (RIE) using fluorocarbon gas such as CF.sub.4 +CHF.sub.3 is often used in order to form a contact hole of highly precise size.

After the contact hole is formed, the unnecessary resist is removed, for example, by ashing with oxygen containing plasma. If dry etching and ashing processes are used, a good process performance is ensured because both the processes are dry process.

When a contact hole is formed by dry etching, a thin damaged layer of about several nm is formed on the exposed surface of a semiconductor substrate by plasma exposure. If a wiring layer contacts the damaged layer, a contact resistance increases, or other objectionable effects may occur. It is therefore desired to remove the damaged layer.

Prior to the ashing process, light etching is therefore performed in order to remove the semiconductor damaged layer on the surface of the semiconductor substrate. Although light etching removes the damaged layer, it is desired that light etching etches the insulating film as less as possible so as not to change the size of the contact hole. Light etching is generally performed by plasma down-flow etching by using mixed gas of CF.sub.4 and O.sub.2. The resist pattern is not removed by this plasma down-flow etching because the surface thereof has been fluorinated by RIE of the insulating film. The ashing process as well as the etching process for the damaged layer is therefore necessary.

As described above, if a contact hole is formed by etching an insulating film on a semiconductor substrate with fluorine containing gas and by using a resist pattern as an etching mask, a damaged layer is formed on the semiconductor surface. It has been necessary to remove the damaged layer and resist pattern by different processes.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method of manufacturing a semiconductor device, the method having simplified processes including the process of patterning an insulating film and forming a contact hole.

It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a good contact by efficiently removing a damaged layer on the semiconductor surface and a resist pattern on an insulating film after a contact hole is formed in the insulating film.

According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: forming an insulating film on a silicon substrate; forming a resist pattern on the insulating film; etching the insulating film by using the resist pattern as an etching mask to expose the surface of the silicon substrate; and ashing the resist pattern and etching an exposed surface layer of the silicon substrate at the same time.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: forming an insulating film on a silicon substrate; coating a resist film on the insulating film and exposing and developing the resist film to form a resist pattern; etching the insulating film by using the resist pattern as a mask to form a contact hole; partially ashing the resist pattern by raising a temperature of the substrate to 50.degree. C. or higher; and wholly ashing the resist pattern and etching a silicon surface layer at the bottom of the contact hole at the same time after the substrate temperature is lowered to 30.degree. C. or lower.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: forming an insulating film on a silicon substrate; coating a resist film on the insulating film, exposing and developing the resist film to form a resist pattern; etching the insulating film by using the resist pattern as a mask to form a contact hole; etching a silicon surface layer at the bottom of the contact hole while maintaining a silicon substrate temperature at 30.degree. C. or lower; and thereafter raising the silicon substrate temperature to 50.degree. C. or higher and ashing the resist pattern.

The surface of resist is changed in quality after an etching process using fluorine containing gas such as fluorocarbon, and the changed surface layer cannot be removed by usual ashing.

However, if the substrate is heated to 40.degree. C. or higher and ashing/etching is performed using gas containing oxygen and fluorine, the changed resist surface layer can be removed.

The manufacturing processes for a semiconductor device can be simplified by ashing a resist pattern used for forming a contact hole and etching the damaged layer on the silicon substrate surface at the same time. A good contact can be obtained because the damaged layer is removed at the same time when ashing is performed.

For example, gas containing O.sub.2 and CF.sub.4 may be used. The temperature is preferably heated in the range from 50.degree. to 200.degree. C. As the temperature is raised to 50.degree. C. or higher, an ashing start delay time of removing a changed layer becomes small. If the temperature is raised to 200.degree. C. or higher, contamination by a resist layer becomes a problem.

In the case of mixed gas of CF.sub.4 +O.sub.2, a selectivity ratio of resist ashing to SiO.sub.2 etching can be raised by setting a ratio of CF.sub.4 flow rate to the total flow rate to about 1 to 8 volume %, or preferably to about 2.5 to 5 volume %.

After the changed resist layer is removed at the temperature of 50.degree. C. or higher, the remaining ashing/etching process can be performed at a lower temperature. The selectivity ratio of resist ashing to SiO.sub.2 etching can also be raised by lowering the temperature. If an insulating film is a laminate of two or more layers having different etching characteristics, a good pattern is ensured by raising an etching ratio of Si to the insulating film. It is also possible to facilitate an etching control by exchanging gases. For example, etching is not performed although ashing is performed if O.sub.2 +N.sub.2 or O.sub.2 +H.sub.2 O is used.

A silicon surface layer can be etched selectively at the temperature of 30.degree. C. or lower. If the substrate temperature is raised to 50.degree. C. or higher after the silicon surface layer is etched, both the changed resist layer and the resist layer can be selectivity etched with an enhanced selection ratio to silicon and the insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic cross sectional views explaining a method of manufacturing a semiconductor device according to an embodiment of the invention.

FIGS. 2 and 3 are schematic cross sectional views of plasma down-flow systems used by the embodiment manufacturing method of the invention.

FIGS. 4A and 4B are schematic cross sectional views explaining the process of forming a contact hole according to a prior art.

FIGS. 5 to 8 are graphs showing the experiment results of ashing.

FIG. 9 is a graph showing the etching rate of other materials during ashing.

FIG. 10 is a graph showing the temperature dependency of an ashing rate.

FIGS. 11 is a graph showing the temperature dependency of a selectivity ratio of ashing to etching.

FIG. 12 is a graph showing the CF.sub.4 concentration dependency of an etching rate.

FIG. 13 is a graph showing the CF.sub.4 concentration dependency of a selectivity ratio of ashing to etching.

FIG. 14 is a graph showing the CF.sub.4 concentration dependency of an ashing start delay time.

FIGS. 15A and 15B are a schematic cross sectional view and a graph, explaining the etching ratio of Si to SiO.sub.2 and BPSG.

FIGS. 16A to 16C are schematic cross sectional views explaining a method of manufacturing a semiconductor device according to another embodiment of the invention.

FIGS. 17A and 17B are a schematic plan view and a schematic cross sectional view of a vapor phase process system used by the embodiment manufacturing method of the invention.

FIGS. 18A to 18C are schematic cross sectional views explaining a method of manufacturing a semiconductor device according to still another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The conventional technology will be first explained briefly prior to giving the description of the embodiments of the invention.

As shown in FIG. 4A, an SiO.sub.2 film 53 is formed on an Si substrate 51. A resist film 54 is coated on the insulating film 53, and developed and exposed to form an opening 54 for a contact hole. By using the resist film 54 with the opening 55 as an etching mask, a contact hole 56 is formed in the insulating film 53 by reactive ion etching (RIE) using fluorine containing gas such as CF.sub.4 +CHF.sub.3.

When the contact hole 56 is formed by RIE, the surface of the Si substrate 51 is exposed to plasma and a surface damaged layer 57 is formed. If electrical contact is made without removing the damaged layer 57, the electrical characteristics of contact are deteriorated.

A dry process is performed under the following conditions, trying to remove the damaged layer 57 and resist film 54 at the same time.

______________________________________ O.sub.2 flow rate 800 sccm CF.sub.4 flow rate 200 sccm Pressure 1.0 torr Microwave power 1.5 kW Wafer temperature 25.degree. C. ______________________________________

O.sub.2 is a composition necessary for ashing the resist layer 54, and CF.sub.4 is a composition necessary for removing the damaged layer 57 on the Si substrate 51.

FIG. 4B is a schematic cross sectional view of a wafer after such a dry process. The damaged layer 57 on the surface of the Si substrate was removed. Although the resist film 54 at the side wall of the opening 55 was removed by ashing, the surface layer 59 of the resist film 54 was left without being ashed. The reason why the surface layer 59 of the resist film 54 is left, can be ascribed that the surface of the resist film 54 is fluorinated when the insulating film 54 is subjected to RIE. Since the resist film at the side wall of the opening 55 was removed by ashing, if there were no surface layer 59, the resist film 54 could be wholly removed. However, because of the presence of the fluorinated surface layer 59, it can be considered that the damaged layer 57 and resist mask 54 cannot be removed at the same time.

The inventor has conducted various studies and experiments in order to find the dry process conditions capable of removing a damaged layer on the surface of an Si substrate and ashing a resist pattern at the same time. It has been found that both a resist film with a fluorinated surface layer and a damaged layer on the surface of an Si substrate can be removed under certain conditions by raising the temperature of the wafer.

The following description is directed to the experiment results on which the present invention is based. In order to perform ashing of a resist film and light etching of a damaged layer, it is necessary to remove a thick resist film at high speed, and at the same time to remove a thin damaged layer of about several nm on an Si surface.

In order to maintain a size allowance of a contact hole, it is desired to set an etching rate of an insulating film as low as possible and to suppress broadening the contact hole. In other words, it is desired that the resist film and the Si damaged layer can be removed at the same time and that the etching selectivity ratios of a resist film to Si and of the resist film to an insulating film such as SiO.sub.2 are high.

As described above, the etching (ashing) performance of a resist film changes with whether or not the film was exposed to fluorine containing plasma. From this viewpoint, there were prepared samples of Si substrates each being formed with an SiO.sub.2 film of about 1 .mu.m coated with a resist film, and similar samples each being formed with an SiO.sub.2 film having been subjected to RIE in a parallel plate type RIE system by using a resist pattern as an etching mask. The RIE conditions were as follows.

______________________________________ CF.sub.4 flow rate 50 sccm CHF.sub.3 flow rate 50 sccm Pressure 0.1 torr RF power 1.0 kW Wafer temperature 20.degree. C. ______________________________________

Ashing was performed for the samples underwent an RIE process and for the samples without the RIE process under the following conditions.

______________________________________ O.sub.2 flow rate 950 sccm CF.sub.4 flow rate 50 sccm Pressure 1.0 torr Microwave power 1.4 kW Wafer temperature 25, 50, 80, 100.degree. C ______________________________________

FIGS. 5 to 8 are graphs explaining the ashing of resist films by a dry process under the above conditions at substrate temperatures of 25.degree., 50.degree., 80.degree., and 100.degree. C. In each graph, the abscissa represents time and the ordinate represents an ashing amount in .mu.m.

The graph of FIG. 5 shows the experiment results at a substrate temperature of 25.degree. C. A line x shows the experiment results of the sample without plasma exposure by RIE (untouched resist). The resist film is gradually ashed as the time lapses. Another line y shows the experiment results of the sample with plasma exposure by RIE. The film thickness is hardly thinned, which indicates no ashing. The data of this graph of FIG. 5 corresponds to the conventional technology that a fluorinated resist film surface cannot be removed by mixed gas of O.sub.2 and CF.sub.4.

The experiment results shown in the graphs of FIGS. 6 to 8 indicate that both the samples without plasma exposure (lines a, c, and e) and the samples with plasma exposure (lines b, d, and f) can be ashed.

The graph of FIG. 6 shows the experiment results at a substrate temperature of 50.degree. C. The characteristics b of the sample with plasma exposure rise later by a delay of about 15 seconds than the characteristics of the sample without plasma exposure, and thereafter the former sample is ashed at an ashing rate generally the same as the latter sample.

The graph of FIG. 7 shows the experiment results at a substrate temperature of 80.degree. C. Both the sample c without plasma exposure and the sample d with plasma exposure can be ashed. Although the rising start of the sample d with plasma exposure is delayed, its delay time is very small as compared to the substrate temperature of 50.degree. C.

The delay time is about 2 to 3 seconds as measured from the graph and about 1/5 or less of 15 seconds of the substrate temperature of 50.degree. C. Although the ashing rate d of the sample with plasma exposure is slightly lower than the ashing rate c of the sample without plasma exposure, the tendency of the ashing rate is similar to that shown in FIG. 6.

The graph of FIG. 8 shows the experiment results at a substrate temperature of 100.degree. C. The characteristics of the sample e without plasma exposure become more like the characteristics of the sample f with plasma exposure. The delay time of the rising start of the ashing f of the sample with plasma exposure is perhaps about 1 to 2 seconds.

A delay time of the rising start of ashing a resist film with plasma exposure has been described above. Ashing a resist film is completed when a predetermined thickness is ashed. Assuming that the thickness of a resist film is 1.0 .mu.m, a delay time of the end of ashing a resist film with plasma exposure from the end of ashing a resist film without plasma exposure is about 16 to 17 seconds in FIG. 6, about 7 seconds in FIG. 7, and about 6 seconds in FIG. 8.

The experiment results shown in FIGS. 6 to 8 indicate that after the fluorinated surface layer of a resist film is removed, the ashing progresses in generally the similar manner as the resist film without plasma exposure.

As seen from FIGS. 6 to 8, the resist film with plasma exposure can be ashed by raising the substrate temperature. It is to be noted that the resist film with plasma exposure can't be ashed at a room temperature (25.degree. C.). In order to ash the resist film with plasma exposure, the substrate temperature is supposedly required to be raised to at least 40.degree. C. or higher. It is preferable to heat the substrate to at least 50.degree. C. or higher when a delay time of the ashing start is taken into consideration.

A decomposed, cured layer on the surface of a resist film made of novolak resist for g-line and i-line of a mercury lamp was checked. It has been found from X-ray photoelectron spectroscopy that such a surface layer is formed mainly by CF.sub.x. Resist forming such a surface layer is not limited to novolak resist, but other resist materials such as chemically amplified resist may also form such a surface layer. It is conceivable that RIE of an insulating film by fluorine containing gas forms the cured surface layer.

From the experiment results shown in FIGS. 6 and 7, it has been found that the resist film with plasma exposure can be ashed by raising the substrate temperature. It is desired that the above process conditions can remove a damaged layer on the surface of an Si substrate and don't etch the insulating film at the side wall of a contact hole as much as possible.

FIG. 9 shows the results of measurement of the etching rates of polycrystalline Si and SiO.sub.2 under the above process conditions. The abscissa represents a wafer temperature in .degree.C., and the ordinate represents an etching rate in nm/min. Samples used were not subjected to plasma exposure.

As the temperature rises, the etching rate h of polycrystalline Si gradually increases in the temperature range from 50.degree. C. to 100.degree. C., and is in the order of several nm/min to ten and several nm/min. This etching speed is suitable for removing a damaged layer on the surface of an Si substrate, because the damaged layer has a thickness of about several nm.

The etching rate g of SiO.sub.2 also gradually increases in the temperature range from 50.degree. C. to 100.degree. C., and has generally the same value as polycrystalline Si. More precisely, the etching rate of SiO.sub.2 is faster than that of polycrystalline Si at a relatively low temperature of 50.degree. C., and a difference between the etching rates becomes small as the temperature rises.

The graph of FIG. 10 shows a change in an ashing rate of a resist film without plasma exposure, by using a wafer temperature as a parameter. The process conditions are the same as above, and the process time is 30 seconds. The abscissa represents a wafer temperature in .degree.C., and the ordinate represents an ashing rate in .mu.m/min. As the temperature rises, the etching rate i of the resist film gradually increases in the temperature range from 50.degree. C. to 100.degree. C. In this temperature range, the ashing rate is 2 .mu.m/min or higher and a resist film of about 1 .mu.m can be fully ashed in 30 seconds.

From the experiment results shown in FIGS. 9 and 10, the etching selectivity ratios of a resist film to polycrystalline silicon and SiO.sub.2 were calculated.

FIG. 11 is a graph showing an etching selectivity ratio. The abscissa represents a wafer temperature in .degree.C., and the ordinate represents a selectivity ratio in the term of etching (ashing) rate ratio. As the temperature rises, both the selectivity ratio j of a resist film to SiO.sub.2 and the selectivity ratio k of a resist film to polycrystalline Si decrease in the temperature range from 50.degree. C. to 100.degree. C.

The selectivity ratio k of resist ashing to polycrystalline Si etching is higher than the selectivity ratio k of resist ashing to SiO.sub.2 etching at 50.degree. C. This relationship is inverted at a temperature of 100.degree. C. A lower process temperature is preferable because it is desired that a resist film is ashed and SiO.sub.2 is not etched.

The selectivity ratio of a resist film to Si changes with the thickness of a surface damaged layer to be removed. It is understood that if proper conditions are set, while Si is etched by a necessary thickness, a resist film can be ashed by a necessary thickness.

The above-described experiment results were obtained when the concentration of CF.sub.4 in the mixed gas of O.sub.2 and CF.sub.4 was set to 5 volume %. The etching (ashing) performance changes with the CF.sub.4 concentration.

FIG. 12 is a graph showing a change in the etching rate of polycrystalline Si and SiO.sub.2, by using as a parameter the concentration of CF.sub.4 in the mixed gas of O.sub.2 and CF.sub.4. The abscissa represents the concentration of CF.sub.4 in volume %, and the ordinate represents the etching rate in nm/min. The experiments were performed under the conditions of a total gas flow rate of 1000 sccm, a pressure of 1 torr, a microwave (.mu. wave) power of 1.4 kW, and a wafer temperature of 100.degree. C.

The CF.sub.4 concentration was changed from 2.5 volume % to 10 volume %. The etching rate m of polycrystalline Si increases from about 7 nm/min to about 25 nm/min as the CF.sub.4 concentration increases. The etching rate n of SiO.sub.2 increases from about 5 nm/min to about 33 nm/min as the CF.sub.4 concentration increases.

FIG. 13 is a graph showing a change in the etching selectivity ratio under the same conditions as FIG. 12, by using as a parameter the CF.sub.4 concentration. The wafer temperature was set to 100.degree. C. The abscissa represents the CF.sub.4 concentration in volume %, and the ordinate represents the selectivity ratio. The selectivity ratio q of resist to polycrystalline Si abruptly lowers from about 300 to about a little less than 100 in the range from 2.5 volume % to 10 volume % as the CF.sub.4 concentration increases. Similarly, the selectivity ratio p of resist to SiO.sub.2 abruptly lowers from about 330 to about 100 as the CF.sub.4 concentration increases from 2.5 volume % to 10 volume %.

When it is considered that a resist film to be ashed has generally a thickness of about 1 .mu.m and a damaged layer on the Si substrate surface to be removed has generally a thickness of about several nm, the Si surface is excessively etched if the selectivity ratio is too low. For example, a selectivity ratio of 100 may be too low under some conditions.

A selectivity ratio is preferable about 150 or higher. As the RIE technique advances, the depth of a damaged layer possibly becomes shallow so that a high selectivity ratio is expected. However, if Si can't be etched at all, the damaged layer can't be removed. If mixed gas of O.sub.2 +CF.sub.4 is used, the CF.sub.4 concentration is preferably in the range from about 1 to 8 volume % when other parameters such as temperature are taken into consideration.

FIG. 14 is a graph showing a change in a delay time, by using as a parameter the concentration of CF.sub.4 in the mixed gas of O.sub.2 +CF.sub.4. The wafer temperature was set to 100.degree. C. The abscissa represents a CF.sub.4 concentration in volume %, and the ordinate represents a delay time in second. The delay time r increases as the concentration increases. In the range from 2.5 volume % to 10 volume %, the delay time changes from about 1 second to about 10 seconds. A short delay time is preferable. From this viewpoint, a low CF.sub.4 concentration is preferable.

From the experiment results shown in FIGS. 6 to 8 and FIG. 14, a high wafer temperature and a low CF.sub.4 concentration are preferable in order to reduce the delay of the etching start of ashing a resist film with plasma exposure.

From the experiment results of the selectivity ratio shown in FIGS. 11 and 13, a low wafer temperature and a low CF.sub.4 concentration are preferable in order to obtain a high selectivity ratio.

A high wafer temperature is preferable in order to shorten the delay time, whereas a low wafer temperature is preferable in order to raise a selectivity ratio. Although these conditions appear to be contradictory, there is a temperature range satisfying both the conditions. For example, in the characteristics shown in FIG. 11, a selectivity ratio almost sufficient for some practical use can be obtained in the substrate temperature range from about 50.degree. C. to about 150.degree. C. when the measurement results are extrapolated. The substrate temperature is desired to be in the range from about 50.degree. C. to about 110.degree. C. and more preferably from abut 50.degree. C. to about 100.degree. C. in order to obtain a more sufficient selectivity ratio.

A delay of an ashing start time poses no problem after the ashing starts once. The selectivity ratio is, however, a factor which affects the whole process from the ashing start to end.

If ashing (light etching) starts at a high temperature and thereafter the wafer temperature is lowered, a delay of an ashing start time can be shortened and a selectivity ratio can be maintained high. In this case, the upper limit of the wafer temperature may be set higher. However, at a wafer temperature of 200.degree. C. or higher, heavy metals in resist may contaminate semiconductor and such a high temperature is often undesired. After ashing of a resist film starts once, it continues even if the wafer temperature is lowered to 25.degree. C. or lower.

Embodiments of the invention will be described next.

Referring to FIG. 1A, on the surface of an Si substrate 1, a high impurity concentration region 2 is formed by ion implantation or other processes, to which region 2 an electrode is contacted. An SiO.sub.2 insulating film 3 is deposited on the surface of the Si substrate 1 by chemical vapor deposition (CVD) or other processes. Other constituent elements such as an insulating gate of a MOSFET and a resistor region for a resistor element may be formed before the insulating film 3 is deposited. A resist pattern 4 is formed by usual photolithography on the insulating film 3. The resist pattern 4 has an opening 5 at the position corresponding to a contact hole to be next formed.

The Si substrate 1 with the resist pattern 4 is transported into a parallel plate type RIE system shown in FIG. 2 to anisotropically etch the insulating film 3. Parallel plate electrodes 14f and 15 are disposed in a hermetic chamber 11 capable of being evacuated via a valve 12 by a gas exhauster 13.

A gas flow path connected to a gas pipe 16 is formed in the upper plate electrode 15. A punched metal board 17 is mounted on the bottom of the electrode 15. Gas supplied via the pipe 16 is flowed through the punched board 17 toward the lower electrode 14. The upper electrode 15 is being grounded.

The lower plate electrode 14 is connected to an RF power source 18. The RF power source 18 may be connected to the upper electrode 15 or to both the upper and lower electrodes. A subject 19 to be processed is placed on the lower plate electrode 14, gas is supplied via the pipe 16, the inside of the hermetic chamber 11 is set to a predetermined pressure by the exhauster 13, and an RF power is supplied from the RF power source 18 to start RIE.

RIE is performed under the following conditions assuming that the thickness of the insulating film 3 shown in FIG. 1A is 1 .mu.m.

______________________________________ CF.sub.4 flow rate 50 sccm CHF.sub.3 flow rate 50 sccm Pressure 0.1 torr RF power 1.0 kW Wafer temperature 20.degree. C. Overetch 30% ______________________________________

A contact hole 6 is formed by RIE of the insulating film 3 under the above conditions. The surface of the Si substrate 1 exposed in the contact hole 6 is formed with a damaged layer because of RIE plasma exposure.

The wafer subjected to the RIE process shown in FIG. 1A is transported to a plasma down-flow system shown in FIG. 3 to perform both ashing and etching.

In FIG. 3, a chamber 21 communicates with a microwave guide room 24 via a window 23 made of alumina ceramic. Microwaves propagated in a microwave guide 25 is introduced via the microwave guide room 24 and window 23 into the chamber 21. Similar to the chamber shown in FIG. 3, the chamber 21 is connected via a valve to an exhauster so that the inside of the chamber can be evacuated to a desired vacuum degree.

A punched aluminum board 22 is mounted under the window 23 forming a plasma generating room 28 between the window 23 and board 22. The plasma generating room 26 communicates with a gas inlet pipe 27. Process gas is introduced via the gas inlet pipe 27 and microwaves are supplied so that plasma is generated in the plasma generating room 26.

A susceptor 28 with a temperature controller 29 is disposed under the punched board 22. A subject 19 to be processed is placed on the susceptor 28. The temperature controller 29 is constituted by a heater and a chiller, a temperature controlling device for flowing heat transfer medium at a desired temperature, or another device.

As gas is introduced via the gas pipe 27 and plasma is generated in the plasma generating room 26 at a desired pressure of the inside of the chamber 21, charged particles in plasma are confined in the upper space by the punched board 22 and only neutral particles including neutral active particles are conveyed through the punched board 22 onto the subject 19. In this manner, a dry process is performed by using mainly neutral active particles.

The Si substrate shown in FIG. 1A was transported into the chamber 21 shown in FIG. 8 and placed on the susceptor 28. A dry process for ashing/light etching was performed under the following conditions.

______________________________________ O.sub.2 flow rate 950 sccm CF.sub.4 flow rate 50 sccm Pressure 1.0 torr Microwave power 1.4 kW Wafer temperature 80.degree. C. ______________________________________

With this plasma down-flow process, a dry process proceeds by using O* radicals and F* radicals. Under the above conditions, the CF.sub.4 concentration is 5 volume % and the wafer temperature is 80.degree. C. It is therefore understood from the above-described experiment results that not only the fluorinated surface layer 9 on the surface of the resist film 4 can be ashed, but also the damaged layer 7 on the surface of the Si substrate 1 can be etched.

When the resist film 4 was completely peeled off, the etching amount of the surface of the Si substrate at the bottom of the contact hole 6 was about 10 nm or less. The damaged layer 7 on the surface of the Si substrate 1 is supposedly removed completely. The etching amount of the insulating film at the side wall of the contact hole was smaller than a measurement limit. The pattern precision of the contact hole 6 is supposedly maintained sufficiently. The cross section of the wafer after the plasma down-flow process is schematically shown in FIG. 1B.

According to this embodiment, after a resist pattern with an opening for a contact hole is formed, the contact hole with a surface damaged layer being removed can be formed by two dry processes.

Another embodiment of the invention will be described hereinunder. Similar to the already described embodiment, a contact hole such as shown in FIG. 1A was formed in an insulating film by RIE. Thereafter, the wafer was transported to the plasma down-flow system shown in FIG. 3 and a dry process for ashing/light etching was performed under the following conditions.

______________________________________ O.sub.2 flow rate 975 sccm CF.sub.4 flow rate 25 sccm Pressure 1.0 torr Microwave power 1.4 kW Wafer temperature 100.degree. C. ______________________________________

The CF.sub.4 concentration was lowered to 2.5 volume % and the wafer temperature was raised to 100.degree. C. When the resist film was completely peeled off by the dry process, the sample was picked up and the etching amount of the Si layer on the bottom of the contact hole 6 was measured. The etching amount was 5 nm. The etching amount of the insulating film at the side wall of the contact hole was smaller than a measurement limit. The etching amount of Si can be therefore controlled by changing the wafer temperature or the CF.sub.4 concentration.

Similar to the already described embodiment, a sample with a contact hole such as shown in FIG. 1A was transported to the plasma down-flow system shown in FIG. 3, and a dry process by mixed gas of O.sub.2 +SF.sub.6 as well as a dry process by mixed gas of O.sub.2 +NF.sub.3 was performed. Also in these cases, the surface of the Si substrate at the bottom of the contact hole can be etched by a predetermined amount at the same time when ashing is completed, by controlling the concentration of fluorine containing gas to be 3 volume % or lower.

Since the dissociation factor of SF.sub.6 is high, the concentration of SF.sub.6 is required to be controlled in a very low concentration range. Since a process margin is narrow, a precise control is necessary.

The concentration of NF.sub.3 is also required to be controlled in a very low concentration range, similar to SF.sub.6. NF.sub.3 is poisonous gas