Methods of forming nonvolatile memory devices include the steps of forming a plurality of field oxide isolation regions on a semiconductor substrate. A thermal oxidation step may then be performed to define first gate insulating layers on active regions within the substrate. A blanket layer of polysilicon is then deposited as a first electrically conductive layer. Next, a blanket layer of an electrically insulating layer, which may comprise an oxide-nitride-oxide (ONO) composite insulating layer, is deposited. A blanket photoresist layer is then deposited on the electrically insulating layer. Conventional photolithography steps may then be performed to convert the blanket photoresist layer into a photoresist pattern on a memory cell array portion of the substrate. A dry etching step is then performed to define a floating gate electrode having an ONO electrically insulating cap thereon, on the memory cell array portion of the substrate. A wet etching step is then performed to remove the first gate insulating layer from the peripheral circuit portion of the substrate. This wet etching step is performed using the same mask (i.e., photoresist pattern) that was used during the dry etching step. Because this etching step causes portions of the floating gate electrodes to be undercut, a thermal oxidation step is then performed to grow sidewall insulating spacers on the sidewalls and undercut portions of the floating gate electrodes. Based on this thermal oxidation step, the floating gate electrodes become encapsulated by electrically insulating material.

A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating dielectric layer is then formed over the first gate. The insulating dielectric has a lens-shaped cross-section located above the sharp corner. Next, a second gate is formed over the insulating dielectric layer, and surrounded the first gate. A first doped region is formed in the substrate below the sharp corner. Then, a second doped region is formed in the substrate located on the other side of the first gate just opposite the first doped region, furthermore, the second doped region is separated from the first gate by a distance. There is a channel region between the first doped region and the second doped region, and the sharp corner of this invention is located above the semiconductor substrate outside the channel region.

A semiconductor memory device, having at least one floating gate, includes a semiconductor substrate; at least one device-isolation region buried in the semiconductor substrate, having a top surface protruding from a top surface of the semiconductor substrate, the top surface of the device isolation region having a concave section that has a depression thereon; at least one gate-insulating film formed on the semiconductor substrate; a first gate formed on the gate-insulating film, the device-isolation region and the depression; a gate-to-gate insulating film formed on the first gate and in the concave section and the depression of the device-isolation region; and a second gate formed on the gate-to-gate insulation film, the depression being filled with the second gate.

Described is a semiconductor device having a silicon oxide (SiO.sub.2) film into which nitrogen atoms, in a range between approximately 2.times.10.sup.20 atoms/cm.sup.3 or more and 2.times.10.sup.21 atoms/cm.sup.3 or less, are introduced, used as an insulator film in the semiconductor device. For example, the device can be a nonvolatile memory device, and the silicon oxide film can be used as an insulator film between, e.g., a floating gate electrode and control gate electrode of the nonvolatile memory device. Stable operations and a retention capability of a nonvolatile memory device are obtained even if the nonvolatile memory device is scaled. Moreover, a programming voltage can be lowered. Also described are methods of fabricating the semiconductor device.

A polysilicon layer 38 located upward of a local oxidation of silicon (LOCOS) layer 20 is removed partially when selective etching of the polysilicon layer 38 for forming a floating gate FG is carried out by carrying out anisotropic etching. The etching is stopped when only the polysilicon layer 38 is removed. Wet-etching usually carried out at the final phase of the anisotropic etching process is not performed. In this way, the LOCOS layer 20 located underneath the polysilicon layer 38 is not over-etched. As a result, an inter layer 34 is not formed in a shape of eaves on the LOCOS layer 20 when the inter layer 34 is formed. Therefore, the probability of causing stringers underneath the inter layer 34 is remarkably low.