E and D mode HEMTs are integrated in a laminated layer of pairs of GaAs/AlGaAs layers formed on the same GaAs-on-Si substrate. The gate electrodes of E and D mode HEMTs are formed on different GaAs layers. The GaAs layer on Si contains crystal defects. It is hypothesized that the defects extend upward in the laminated layer of pairs of GaAs/AlGaAs layers formed on the GaAs layer with such crystal defects. Etch pits are generated as the AlGaAs layer is etched by ammonium etchant. Generation of etch pits can be suppressed by etching the whole part of the exposed AlGaAs layer and exposing the GaAs layer under the gate electrode.
A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over the channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.
A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over the channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.
A field effect type semiconductor device is disclosed wherein a channel is easily depleted just under a gate electrode to implement an E-mode, but a channel is hard to be depleted just under a gate recess region so that the transconductance gm and the cutoff frequency f.sub.T can be set to sufficiently high values. The present device includes a first etching stop layer Schottky contacting with an end face of the gate electrode and a second etching stop layer extending to a position in the proximity of a side face of the gate electrode. The first etching stop layer is formed from a material which is easily depleted (one of materials of a group including InAlP, InP, InAsP, InSbP, InAlAsP, and InAlSbP), and the second etching stop layer is formed from a material which is hard to be depleted (one of materials of a group including InGaP, InGaAsP, InGaSbP).
A heterojunction field effect transistor operative from the micro wave band to the millimeter wave band has a gate recess structure formed in a manner such that its eye-empty areas have a significant effect on the voltage durability of the transistor. The eye-empty areas extend from a gate electrode to a source electrode as well as to a drain electrode and are formed by at least two material layers having different impurity concentrations, thereby making it possible to obtain an improved heterojunction field effect transistor having a reduced series resistance and an increased voltage durability.
A field effect transistor device and method, such device having source and drain electrodes in ohmic contact a semiconductor. A gate electrode-field plate structure is disposed between the source and drain electrodes. The gate electrode-field plate structure comprises: a dielectric; a first metal in Schottky contact the semiconductor; and a second metal. The second metal has: a first portion disposed over and electrically connected to a portion of the first metal; and a second portion, separated from a second portion of the first metal by a portion of the dielectric and extending beyond an edge of the first metal to an edge of the second metal. The edge of the first metal is further from the drain electrode than the edge of the second metal to provide a field-plate for the field effect transistor.
