A high speed and low power D/A converter which is capable of accurately outputting an analog value and implementing a high speed operation by reducing noise and errors during the conversion. The converter includes an upper current cell plate for forming analog voltages from a 126th level to a 255th level in accordance with decoding of inputted digital values by a first column decoder and a first row decoder, a lower current cell plate for forming analog voltages from a 0th level to a 125th level in accordance with decoding of the inputted digital values by a second column decoder and second row decoder, and a multiplexer for selectively outputting the analog voltage from the upper current cell plate or the lower current cell plate in accordance with a binary bit value of a most significant bit (MSB) of the inputted digital signal.

A digital to analog converter according to the principles of the invention provides increased dynamic range by utilizing multiple digital to analog converters (DACs) to provide a balanced output. On the positive side of the topology, two or more DACs connect in parallel to a digital input. A summer adds the DAC outputs to provide the positive side of the balanced output. On the negative side, an inverter provides the negative of the digital input to two or more DACs connected in parallel. A summer adds the DAC outputs to provide the negative side of the balanced output. The averaging effect of the summing operations reduces noise due to random errors, thereby increasing the dynamic range achievable with one DAC. The balanced design of the topology and the use of highly matched components for the positive and negative sides assure that common mode errors, noise and distortion are reduced as well.

Wide band CMOS digital to analog converters (DACs), including converters with selectable impulse response, using multiple DAC cores. The DAC cores operate on the same data at the DAC clock rate, but staggered in phase. Switches are used to switch the later part of the output time of each DAC core to the DAC output, otherwise to a dummy load. Thus each DAC conversion is comprised of a later part of each DAC core conversion, at least the first part of each DAC core conversion being ignored to allow each DAC core to settle before utilizing its output. Since the same switches and switching sequence is used on each DAC data conversion, the effects of switch imbalances are negated. Various embodiments are disclosed, including manipulation of the input to one of the DAC cores to selectively provide an NRZ, RZ and an RF response.

A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are complementary with respect to a voltage present at the center of the resistor segment disposed in that decoder. A second decoding stage receives the first and second voltages delivered by each of the N decoders and delivers two of these voltages, that are complementary with respect to a voltage present at the center of the resistor, to a pair of third and fourth output nodes.

A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.