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Claims  |
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I claim:
1. A scannable D-flip-flop circuit for processing data bits, said scannable
D-flip-flop circuit comprising:
(a) a first latch circuit coupled to a first input of said scannable
D-flip-flop, said first latch circuit receives a first data input signal
and a first clock signal and stores said first data input signal in
response to said first clock signal during a normal mode of operation,
said first latch having an output;
(b) a second latch circuit coupled to a second input of said scannable
D-flip-flop, said second latch circuit receives a second data input signal
and a second clock signal and stores said second data input signal in
response to said second clock signal during a scan mode of operation, said
second latch having an output;
(c) a third latch circuit having a data path and a feedback path wherein
said data path is coupled to said output of said first latch circuit and
said feedback path is coupled to said output of said second latch circuit,
said third latch circuit receives said first data input signal and said
first clock signal and stores said first data input signal in response to
said first clock signal during said normal mode of operation, said third
latch circuit receives said second data input signal and said second clock
signal and stores said second data input signal in response to said second
clock signal during said scan mode of operation, said third latch circuit
is coupled to an output of said D-flip-flop.
2. The scannable D-flip-flop circuit of claim 1, wherein said first and
third latch circuits operate respectively as master and slave latch
circuits in response to said first clock signal, and said second and third
latch circuits operate respectively as master and slave latch circuits in
response to said second clock signal.
3. The scannable D-flip-flop circuit of claim 1, wherein said first latch
circuit comprises a first inverter having an input coupled to said first
input of said scannable D-flip-flop, said first inverter having an output
coupled to an input of a first transmission gate, said first transmission
gate having an output coupled to an input of a second inverter, said
second inverter having an output coupled to an output of said first latch
circuit, said second inverter having said output coupled to an input of a
third inverter, said third inverter having an output coupled to an input
of a third transmission gate, said third transmission gate having an
output coupled to said output of said first transmission gate;
during a first clock subcycle when a first signal of said first clock is in
a first state, said first data input signal of said first latch circuit
passes through to said output of said first latch circuit but is prevented
from passing through to said input of said third latch circuit,
furthermore, said first data input signal of said first latch circuit is
prevented from latching into said first latch circuit;
during a second clock subcycle when said first signal of said first clock
is in a second state, said first data input signal of said first latch
circuit latches into said first latch circuit and passes through to said
input of said third latch circuit.
4. The scannable D-flip-flop circuit of claim 3, wherein said third latch
circuit comprises said second transmission gate having an input coupled to
said input of said third latch circuit, said second transmission gate
having an output coupled to an input of a fourth inverter, said fourth
inverter having an output coupled to an input of a fifth inverter and
coupled to an input of a sixth inverter having an output coupled to an
output of said third latch circuit which is coupled to the output of said
scannable D-flip-flop, said fifth inverter having an output coupled to an
input of a fourth transmission gate, said fourth transmission gate having
an output coupled to an input of a fifth transmission gate, said fifth
transmission gate having an output coupled to said input of said fourth
inverter and said output of said second transmission gate;
during said second clock subcycle when said first signal of said first
clock is in said second state, said first data input signal of said first
latch circuit passes from said output of said first latch circuit to said
input of third latch circuit and through to said output of said third
latch circuit, furthermore, said first data input signal of said first
latch circuit is prevented from latching into said third latch circuit;
during a third clock subcycle when said first signal of said first clock is
in said first state, said first data input signal of said first latch
circuit that passes to said input of said third latch circuit during said
second clock subcycle latches into said third latch circuit.
5. The scannable D-flip-flop circuit of claim 4, wherein said first latch
circuit is available to receive a new first data input signal during said
third clock subcycle.
6. The scannable D-flip-flop circuit of claim 1, wherein said second latch
comprises a seventh inverter having an input coupled to said second input
of said scannable D-flip-flop, said seventh inverter having an output
coupled to an input of a sixth transmission gate, said sixth transmission
gate having an output coupled to an input of an eighth inverter, said
eighth inverter having an output coupled to an output of said second latch
circuit and to an input of a ninth inverter, said ninth inverter having an
output coupled to an input of a eighth transmission gate, said eighth
transmission gate having an output coupled to said output of said sixth
transmission gate;
during a first clock subcycle when a second signal of said second clock is
in a first state and a control signal for selecting between a normal mode
and a test mode of a scan clock driver circuit selects said normal mode of
said scan clock driver circuit, said second data input signal of said
second latch circuit passes through to said output of said second latch
circuit but is prevented from passing through to said input of said third
latch circuit, furthermore, said second data input signal of said second
latch circuit is prevented from latching into said second latch circuit;
during a second clock subcycle when said second signal of said second clock
is in a second state and said normal mode of said scan clock driver
circuit is selected, said second data input signal of said second latch
circuit latches into said second latch circuit and passes through to said
input of said third latch circuit.
7. The scannable D-flip-flop circuit of claim 6, wherein said third latch
circuit comprises a seventh transmission gate having an input coupled to
an input of said third latch circuit, said seventh transmission gate
having an output coupled to an input of a fourth inverter, said fourth
inverter having an output coupled to an input of a sixth inverter having
an output coupled to an output of said third latch circuit which is
coupled to said output of said scannable D-flip-flop, said output of said
fourth inverter further coupled to an input of a fifth inverter, said
fifth inverter having an output coupled to an input of a fourth
transmssion gate, said fourth transmission gate having an output coupled
to an input of a fifth transmission gate, said fifth transmission gate
having an output coupled to said output of said seventh transmission gate;
wherein said seventh transmission gate, said fourth inverter and said sixth
inverter form said data path of said third latch circuit and said fifth
inverter, said fourth transmission gate and said fifth transmission gate
form said feedback path of said third latch circuit;
during said second clock subcycle when said second signal of said second
clock is in said second state, said second data input signal of said
second latch circuit passes from said output of said second latch circuit
to said input of said third latch circuit and through to said output of
said third latch circuit, furthermore, said second data input signal of
said second latch circuit is prevented from latching into said third latch
circuit;
during a third clock subcycle when said second signal of said second clock
is in said first state, said second data input signal of said second latch
circuit that passes to said input of said third latch circuit during said
second clock subcycle latches into said third latch circuit.
8. The scannable D-flip-flop circuit of claim 7, wherein said second latch
circuit is available to receive a new second data input signal during said
third clock subcycle.
9. The scannable D-flip-flop circuit of claim 1, wherein said first clock
generates a first clock signal from a system clock and a clock driver
circuit, said first clock operates independently from said second clock.
10. The scannable D-flip-flop circuit of claim 1, wherein said second clock
generates a second clock signal from a scan clock and a scan clock driver
circuit, said second clock operates independently from said first clock.
11. The scannable D-flip-flop of claim 10, wherein said scan clock driver
circuit comprises a first inverter having an input coupled to said input
of said scan clock driver circuit, said first inverter having an output
coupled to said input of a second inverter and a first input of a first
multiplexer and a first input of a second multiplexer, said second
inverter having an output coupled to a second input of said first
multiplexer and a second input of said second multiplexer, said first
multiplexer having an output coupled to a first output of said scan clock
driver circuit, said second multiplexer having an output coupled to a
second output of said scan clock driver circuit;
said scan clock driver circuit further comprises a control signal wherein
said control signal selects a normal mode of operation of said scannable
D-flip-flop or a test mode of operation of said scannable D-flip-flop,
said normal mode of operation of said scannable D-flip-flop enables said
second and third latch circuits to operate respectively as master and
slave latch circuits in response to said second clock signal, said test
mode of operation of said scannable D-flip-flop enables said second and
third latch circuits to provide a direct path from said input of said
second latch circuit to said output of said third latch circuit to provide
a performance testing function for a device which contains said scannable
D-flip-flops.
12. The scannable D-flip-flop circuit of claim 1, wherein said second clock
signal is an edge-triggered clock signal. |
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Claims |
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Description |
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BACKGROUND
The present invention relates to memory storage devices and more
particularly to memory storage devices, such as flip-flops, which are
testable. Today, with the extensive utilization of LSI and VLSI
technology, and with the explosive growth in the availability of complex
IC devices, it is apparent that careful consideration should be taken
during the component design stage in order to insure adequate testability
and producibility of digital ICs. This proliferation of complex IC devices
has led to the need for more rigorous and highly structured device design
practices to provide for adequate testing developed in a timely and
cost-efficient manner.
Structured design, otherwise known as scan design is a design-for-test
(DFT) technique in which storage elements, except those in storage arrays,
can be controlled and observed. The most common form of scan design is the
serial scan in which storage elements are connected to form one or more
shift registers for testing. Most scan design practices are built on the
concept that if the value of all of the latches internal to the design can
be controlled to specific values and observed with a straight forward
operation, then the task of test generation, and possibly fault
simulation, can be reduced to that of doing test generation and fault
simulation for a combinatorial logic circuit. A control signal can switch
the storage elements from their normal mode of operation to a mode that
makes them controllable and observable.
Over 20 years ago, IBM developed the structural design technique referred
to as the level-sensitive scan design (LSSD). According to the LSSD
technique, scan refers to the ability to shift any state into or out of
the circuit and level sensitive refers to constraints on circuit
excitation, logic depth, and the handling of clocked circuitry. A key
element in the design is the shift register latch pair (SRL) 10 as shown
in FIG. 1a which includes latch 11 and latch 12. Data inputs D and C form
the normal mode memory function, while data input I, clock input A and
clock input B, together with latch 12 compose additional circuitry for the
shift register function. The extra data input I, clock input A and clock
input B of SRL 10 allow each latch to be set to any state directly. The
individual latches are cascaded to form an on-chip SRL scan chain 15 shown
in FIG. 1b with clock A and clock B operating in a two-phase fashion. SRL
scan chain 15 consists of three SRLs 10a, 10b and 10c that are cascaded by
connecting the L2 output of latch 12a to the input I of latch 11b and the
output L2 of latch 12b to the input I of latch 11c. The input I of latch
11a is the scan-in input of SRL scan chain 15 and the L2 output of latch
12c is the scan-out output of the scan chain. Furthermore, FIG. 1c
illustrates a generalized LSSD approach block diagram such that a LSSD
design circuitry 17 can be thought of as combinatorial logic 16
interconnected to the SRL scan chain 15.
The basic idea behind using the extra circuitry, which can consume up to 20
percent of the available functional circuitry on an IC, is to make
sequential circuitry look combinatorial during testing. In otherwords, the
extra circuitry provides the capability to force states at any node and to
similarly be able to observe the state of any node. The extra inputs allow
any latch to be set or reset by cycling the A and B clock inputs between
the logic 0 and logic 1 levels. The design of the scan circuitry 17 allows
automatic test generation programs to treat even sequential circuitry as
simple combinatorial circuitry. Full scan designs, such as those that use
full LSSD, essentially reduce the problem of test generation for a
sequential ciurcuit to that of a combinatorial one.
Although the LSSD structured design approach for design for testability can
alleviate some of the problems in designing, manufacturing, and
maintaining LSI/VLSI systems at a reasonable cost, the LSSD design
philosophy can have some negative impacts on cost and as well as
performance. First of all, the shift register latches in the shift
register are two or three times as complex as simple latches. Up to four
additional primary inputs/outputs are required at each package level for
control of the shift registers. External asynchronous input signals must
not change more than once every clock cycle. Finally, all timing within
the subsystem may be controlled by internally generated clock signals.
While scan methodologies, which includes LSSD as well as other scan
technologies, may offer the advantages of fully structured test generation
and testing techniques, strict adherence to scan-based designs can
sometimes actually increase product costs. The long test sequences
required for scannable designs can increase test time, which can, in turn,
limit production throughput. Furthermore, as the industry moves toward
larger and more complex IC devices, routing becomes more of a design
limitation making it impractical to make every D-flip-flop in the design
scannable. Thus, scan design, while well known and widely discussed, has
not been widely adopted. It is apparent that a fully structured approach,
while sometimes desirable, is not always necessary. In recent years,
software algorithms for test generation have been improving, albeit
slowly, to handle partially sequential (and hence partially scannable)
circuits with certain limitations. This has led to the development and
implementation of partial scan design techniques. Partial scan is a DFT
technique that requires only a subset of all circuit D-flop-flops to be
scannable, unlike the fully structured technique which requires all memory
storage-elements to be scannable. Only a few physical device I/O pins and
very little on-chip overhead, compared to full scan techniques, are
required for the test circuitry when using a partial scan technique.
The most widely adopted scan technique is the mux-type-scan-D-flip-flop
shown in FIG. 2a in which multiplexer 21 is used in conjunction with
D-flip-flop 22. D-flip-flop 22 is typically a conventional D-flip-flop
consisting of a master latch and a slave latch that operate together in
response to a system clock. Multiplexer 21, connected to the input of
D-flip-flop 22 enables the mux-type-scannable-D-flip-flop 20 to select
either Data-In input or Scan-In input by using a scan enable control
signal (SE). Thus, mux-type-scan-D-flip-flop 20 may operate as a
conventional D-flip-flop during normal mode of operation (with the Data-In
input selected by the multiplexer 21) or as a scannable D-flip-flop during
scan mode of operation. During normal operation, multiplexer 21 passes the
data from the Data-In input of multiplexer 21 through to the Data-Out
output of D-flip-flop 22. On the other hand, when the scan mode of
operation is selected, data can be fed into the Scan-In input and passed
through to the Data-Out output of D-flip-flop 22 to be scanned.
For the purposes of test generation, only those flip-flops in the circuit
that are difficult to control and observe need to be made scannable.
Software algorithms that use partial scan methodologies allow these
critical nodes within the circuit under test to be identified and
observed, and each such node is augmented with a scannable D-flip-flop
circuit that can be used to control and observe the circuit under test.
These scannable D-flip-flop circuits are then connected in series, very
much like a scan chain, to allow the needed communication with the
critical internal nodes for the device under test. FIG. 2b illustrates a
partial scan chain 23 utilizing the mux-type-scan-D-flip-flop. Partial
scan chain 23 comprises of two mux-type-scan-D-flip-flops designated by
20a and 20b and two conventional (non-scannable) D-flip-flops 24 and 25.
D-flip-flop 24 is coupled to mux-type-scan-D-flip-flop 20a, comprised of
multiplexer 21a and D-flip-flop 22a, through combinatorial logic 29.
Mux-type-scan-D-flip-flop 20b, comprised of multiplexer 21b and
D-flip-flop 22b, is coupled to D-flip-flop 25 through combinatorial logic
30. Mux-type-scan-D-flip-flop 20b is connected directly to
mux-type-scan-D-flip-flop 20a as consecutive elements of the partial scan
chain (shift register). Combinatorial logic 29 and 30 may be the same or
separate function logic. Furthermore, partial scan chain 23 may be
expanded to include additional conventional D-flip-flops as well as
mux-type-scannable-D-flip-flops.
When the normal mode of operation of mux-type-scan-D-flip-flop 20a is
selected, the Data-In input of multiplexer 21a is selected such that
D-flip-flop 22a receives data which was processed through combinatorial
logic 29, which received as an input the data at the Q output previously
stored in D-flip-flop 24. On the other hand, when the scan mode of
operation of mux-type-scan-D-flip-flop 20a is selected, the Scan-In input
of multiplexer 21a is selected such that D-flip-flop 22a receives data
which was previously stored in mux-type-scan-D-flip-flop 20b.
The mux-type-scan-D-flip-flop 20 approach for partial scan DFT scheme has
not been widely accepted due to the fact that the non-scan D-flip-flops
(e.g. flip-flop 20) can not hold their states while scanning the
mux-type-scan-D-flip-flops. This is because, in order to load scan data
into the scannable D-flip-flops, it is necessary to toggle the clock,
which happens to be the same clock feeding the non-scan D-flip-flops.
Unfortunately, the tools used to implement partial-scan based sequential
automatic-test-pattern-generation (ATPG) perform very poorly when the
non-scan D-flip-flops can not hold their previous states during scan
loading, thereby making this type of testing ineffective and inefficient.
Furthermore, the multiplexer adversely impacts the set-up and hold timing
of Data-In at input D of D-flip-flop 22a and similarly at the D input of
flip-flop 22b and the gate count of the scannable D-flip-flip 20a is
increased by one multiplexer as compared to the conventional D-flip-flop
24.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects, features, and advantages of the present invention will be
apparent from the following detailed description of the preferred
embodiment of the invention with references to the drawings in which:
FIGS. 1a-c illustrate a prior art fully structured approach utilizing a
shift register latch (SRL) as the scan design element.
FIGS. 2a-b illustrate a prior art partial scan approach utilizing a
mux-type-scan-D-flip-flop as the scan design element.
FIG. 3a depicts the prior art conventional D-flip-flop latch circuit.
FIG. 3b is a timing diagram of the prior art conventional D-flip-flop latch
circuit illustrating the input and output signals responding to the system
clock.
FIG. 4 is a block diagram of the preferred embodiment of the present
invention.
FIG. 5a is a detailed diagram of the preferred embodiment of the present
invention.
FIG. 5b is a timing diagram showing the operation of the
scannable-D-flip-flop in both normal and scan modes.
FIGS. 6a-b is a drawing of the system clock driver circuit and the
scan/test clock driver circuit.
FIG. 7 illustrates a partial scan chain ultilizing both conventional
D-flip-flops and scannable-D-flip-flops.
FIGS. 8a-b illustrate the test circuitry for the performance testing
function at the chip level of the present invention.
FIG. 9 illustrates a method for testing according to the present invention,
SUMMARY OF THE INVENTION
An apparatus for controlling and observing test data stored in
scannable-D-flip-flops independent of a system clock is disclosed. The
apparatus has particular application for partial-scan Design-For-Test
(DFT) techniques. Furthermore, a method for performance testing integrated
circuits (ICs) utilizing the scanning application of the
scannable-D-flip-flops is disclosed.
Under the present invention, the scannable-D-flip-flop is comprised of two
master latches and one slave latch such that the scannable-D-flip-flop may
operate in a normal mode of operation or a scan/test mode of operation.
During normal mode of operation, the first master latch operates together
with the slave latch in response to the system clock. During the scan/test
mode of operation, the second master latch operates together with the
slave latch in response to a scan clock. Furthermore, the scan/test mode
of operation provides an additional performance testing function for the
IC containing the scannable-D-flip-flops.
It is desirable to produce significantly higher fault coverages and more
efficient test generation times for partial-scan applications. This is
accomplished by the ability of the present invention to scan external test
data independently of a system clock. By scanning external test data
independently of the system clock, the conventional non-scannable
D-flip-flops in the design maintain their previous states during a
scanning operation. In contrast, a conventional mux-type-scan-D-flip-flop
approach, which requires the usage of the same system clock for both the
scannable and non-scannable D-flip-flops during a scan operation, loses
data stored in the non-scannable D-flip-flops when a scanning operation is
performed with the system clock.
It is also desirable to reduce the overall scan/test logic silicon area
overhead required by the design while attempting to achieve a high fault
coverage. By allowing an Automatic Test Pattern Generation (ATPG) tool to
select fewer D-flip-flops in the design for scanning, the scan/test
silicon overhead is significantly reduced. Furthermore, since the design
requires only one extra clock for the scan operation, the scan/test logic
area overhead at the device level as well as at the chip-level is
maintained at significantly low levels.
It is also desirable to provide a scan function without any impact on the
setup-time and minimal impact on the hold-time required on the functional
path of the D-flip-flop. In a mux-type-scan-D-flip-flop, a multiplexer
device is placed on the functional path of scannable D-flip-flops to
achieve the scanning function. This multiplexer increases the set-up time
and hold-time thereby adversely affecting the performance of the IC by
reducing the overall clock frequency.
It is also desirable to provide for performance testing of IC production
devices, which includes the ability to do scan-based performance
characterization of the Application Specific Integrated Circuits (ASIC)
devices. Because IC devices may vary in frequency as a result of the
semiconductor processing, it is desirable to characterize the performance
of ICs into different performance ranges such that the high performance
devices can be distinguished from the lower performance devices. This type
of performance testing is called "binning" since each performance range of
devices is placed into a separate bin. Quite often, the conventional and
time-consuming delay fault testing methods used for binning are not
practicable for large volume production testing since production
throughput will be significantly limited. In such a scenario, the
technique of scan-based performance testing, using the scannable
D-flip-flops in the present invention, can be a very quick and efficient
method to accurately determine the frequency range of chips.
This is accomplished by constructing a test circuit that spans the entire
silicon die area. By using a special AC-TEST-MODE control signal, the
scannable D-flip-flops are set to a "flow-through" mode to provide a
direct path through the scannable flip-flops such that the test circuit
forms an oscillator such as a ring oscillator. Once the ring oscillator is
formed, the frequency of the IC can be measured. The traditional
mux-type-scan-D-flip-flop, which is comprised of a master and a slave
component, allows only one component be turned ON at any given time
thereby making it impossible to set the mux-type-scan-D-flip-flop in a
"flow-through" mode to provide this type of performance testing. This is
evident by the application of opposite polarity system clocks operating
the master and slave components of the D-flip-flop.
DETAILED DESCRIPTION OF THE INVENTION
This description is given for the purpose of describing the general
principles of the invention and is not to be taken in a limiting sense.
The true scope of the invention should be determined with reference to the
appended claims.
In order to appreciate and better understand the present invention, prior
art latch circuits will first be discussed in conjunction with FIG. 3a
which is a typical D-flop-flop latch circuit used in LSI and VLSI chips.
The latch consists of two sections, master section 31, comprised of
transmission gates 33 and 36 and inverters 34 and 35, and a slave section
32 comprised of transmission gates 37 and 40 and inverters 38 and 39.
Transmission gates 33, 36, 37 and 40, in the embodiment of FIG. 3a, are
typically circuits that are turned on when the signal on the control input
that is shown as a small empty circle is low, and turned off when the
signal on that control input is high. When a transmission gate is turned
on, the gate functions as a closed switch and a signal may pass through.
When a transmission gate is turned off, it functions as an open switch and
a signal is blocked from passing through. Other embodiments of
transmission gates are well known and in each case they typically can be
switched between an open switch and closed switch operation.
The signal CK is the system clock signal, while the signal CK.sub.-- is
the complement of the system clock signal. Thus, CK and CK.sub.-- always
have opposite logic values; when CK is high, CK.sub.-- is low, and
vice-versa. The system clock driver circuit 68 is illustrated in FIG. 6a
such that the system clock is coupled to inverter 69 and inverter 70. The
output of inverter 69 provides the CK.sub.-- signal and the output of
inverter 70 provides the CK signal. Inverters 34, 35, 38 and 39 are
circuits whose output signal always have the opposite polarity of its
input signal.
The latch in FIG. 3a functions in the following manner. When the clock
signal CK.sub.-- is high, CK is low, and transmission gates 33 and 40 are
turned on while transmission gates 36 and 37 are turned off. The input
data signal, D, is passed through transmission gate 33, inverted by
inverter 34, reinverted to its original polarity by inverter 35, but is
blocked by transmission gate 36. The output of inverter 34 is blocked by
transmission gate 37. When the clock signal reverses polarity, CK.sub.--
is low, CK is high, transmission gates 33 and 40 are turned off while
transmission gates 36 and 37 are turned on. The signal on the output of
inverter 34 (the same signal as D, but of opposite polarity) is thus
applied to the input of inverter 38 and "latches" signal D into master
section 31 of the latch since signal D will circulate through the loop
formed by inverter 34 and 35.
At the same time, transmission gate 37 is turned on, and the input signal
D, after a double inversion by inverters 34 and 38, appears on the output
as the output data signal Q. When the clock signal goes low again,
CK.sub.-- is high, CK is low and the transmission gates of the latch are
back to their original condition. Since transmission gate 37 is turned off
and transmission gate 40 is turned on, the signal D is now latched in the
slave section 32 of the latch. It is apparent from FIG. 3a that
D-flip-flop 30 operates in response to the system clock. It will be
appreciated that numerous other circuit implementations are well known for
master-slave flip-flops and these implementations may be utilized rather
than the specific circuit shown in FIG. 3a, see, for example, the
flip-flop of FIG. 8.52A on page 508 of The Art of Electronics, Horowitz &
Hill, Cambridge University Press, 1989, (Second Edition).
FIG. 3b is a timing diagram for the latch of FIG. 3a, showing the input
data signal D, the system clock signal CK, signal M at the output of
master section 31, and signal Q at the output of slave section 32. Circuit
delays are not shown in FIG. 3b in order to make the timing diagram easier
to understand.
Still referring to FIG. 3b, it is seen that during a first clock sub-cycle,
that is between times tp0 and tp1, the clock signal CK is low,
transmission gate 33 is turned on, and signal M of master section 31
follows the input data signal D. At time tp1, at the beginning of the next
clock sub-cycle, input data signal D latches into master section 31 and,
since transmission gate 37 is turned on, passes on to the output of slave
section 32 to provide output data signal Q. During the clock sub-cycle
defined between tp1 and tp2, signal M of master section 31 is not affected
by changes in signal D since transmission gate 33 is turned off and the
signal Q at the output of slave section 32 remains constant. At tp2, the
contents of master section 31 are latched in slave section 32. The clock
sub-cycle between tp2 and tp3 is similar to that between tp0 and tp1 and
signal M at the of master section 31 will again follow input data signal
D.
As shown in FIG. 3b, a clock cycle may be defined as the time between the
falling edges of the clock signal CK, e.g. tp0 to tp2, tp2 to tp4, etc
(although it may also be defined as the time between rising edges of CK).
The master-slave latch ensures that the output Q of the latch will be
constant during the entire cycle tp1 to tp3, unaffected by changes on the
input, and will have the same logic level the input had just prior to the
start of the cycle.
The preferred embodiment of the present invention is a scannable
D-flip-flop latch circuit which includes two master sections, 41 and 43,
and one slave section 42 as shown in FIG. 4. Unlike the conventional
D-flip-flop described above with reference to FIG. 3a, a scannable
D-flip-flop has the ability of selecting between a normal mode of
operation and a test/scan mode of operation. The normal mode refers to the
scannable-D-flip-flop operating (under control of the system clock CK at
input 47 of the master latch 41) in a manner similar to the conventional
D-flip-flop described above with reference to FIG. 3a. The test/scan mode
of the scannable-D-flip-flop provides the ability to control and observe
the values stored in the scannable-D-flip-flops without affecting the data
in the non-scannable flip-flops. The test/scan mode is most commonly used
in scan designs such that the scannable D-flop-flops are connected
serially to form one or more shift registers thereby having the ability to
shift any state into or out of the scannable D-flip-flop. Master section
41 is dependent on the system clock whereas master section 43 receives the
scan-in (SI) input signal at input 45 and is dependent on the scan/test
clock signal supplied at input 46 such that the architecture of the
present invention enables the scanning of external test data independent
of the system clock; thus, making the present invention an excellent
vehicle for highly efficient "partial-scan based sequential"
automatic-test-pattern-generation (ATPG). Furthermore, when the scan/test
mode of operation is selected, a special performance testing function may
be specified.
The advantages of present invention will become more apparent, particularly
with respect to partial-scan applications, as the embodiment illustrated
in FIG. 5a is described in further detail. In normal operation ("normal
mode"), the system clock, CK, is running such that master section 41 is
operating in conjunction with slave section 42. This is shown in FIG. 5b.
Also note that the scan clock signal SCK is kept low during normal
operation. On a first subcycle when system clock CK is low and CK.sub.--
is high, transmission gates 52 and 61 are turned on and transmission gates
55 and 56 are turned off. In normal mode, transmission gate 60 is on (as
SCK is low). The input data signal D is inverted by inverter 51,
reinverted to its original polarity by inverter 53, and then inverted by
inverter 54. Since transmission gates 56 and 55 are turned off, the input
data signal D is prevented from passing from master section 41 to slave
section 42 and from latching into master section 41.
On a second subcycle of a system clock, when CK is high and CK.sub.-- is
low, transmission gates 52 and 61 are turned off and transmission gates 55
and 56 are turned on such that the input signal D latches into master
section 41 by circling the loop formed by inverter 53 and 54. Furthermore,
the input signal D is passed from master section 41 to slave section 42
(through the "on" transmission gate 56), inverted by inverter 57, and
reinverted to its original polarity by inverter 58 and appearing as the
output signal Q. During the second subcycle, the output of master section
41 is unaffected by any change in value of data input signal D at the
input of master section 41.
During a third subcycle of a system clock, transmission gates 52 and 61 are
turned on and transmission gates 55 and 56 are turned off. Given that the
scan clock signal SCK is low and SCK.sub.-- is high such that
transmission gate 60 is turned on during normal operation, the input data
signal D will latch into slave section 42 by circling the loop formed by
inverter 57 and 59. During the third subcycle, slave section 42 is
unaffected by any change in value of the data input signal at the output
of master section 41 and the data input signal which is latched into slave
section 42 appears as the output signal Q, available at the output of
slave section 42. Although the slave section 42 is unable to receive a new
data input signal D during the third subcycle when transmission gate 56 is
turned off, transmission gate 52 in master section 41 is turned on again
such that master section 41 is ready to receive a new data input signal D
at the input of master section 41.
It will be appreciated that the scannable D-flip-flop of the present
invention, as is the case with most flip-flops, requires that the input
data be valid and stable a minimum amount of time (so called "set-up
time") before the triggering edge of the clock (in the case of a flip-flop
which latches the D input into the flip-flop on the rising edge of the
clock, then the triggering edge is the rising edge), and further requires
that the input data be valid a stable minimum amount of time (so called
"hold time") after the triggering edge. Unlike other scannable
D-flip-flops (e.g. the mux-type-scan-D-flip-flop), the flip-flop of the
present invention does not require an extended set-up time relative to
non-scannable flip-flops, but the hold time is a bit extended (5%)
relative to the non-scannable flip-flops. This restriction however is
acceptable as set-up time more critically affects circuit design and
performance and thus this hold-time requirement of the flip-flop of the
invention does not significantly adversely impact overall circuit
performance.
In the test/scan mode of operation, the test/scan clock, SCK, is running
such that master section 43 is operating in conjunction with slave section
42 and the system clock CK is normally kept low in order to preserve
signal states in the non-scannable flip-flops on the IC. This is shown in
that test/scan mode of operation provides the ability to select between a
scan mode of operation and a performance test mode of operation by
asserting an AC.sub.-- TEST.sub.-- MODE control signal in the test/scan
clock driver circuit in FIG. 6b. When the AC.sub.-- TEST.sub.-- MODE
control signal is asserted low, the scan mode of operation is selected
such that master slave 43 operates in conjunction with slave section 42
similar to the conventional D-flip-flop described above. When the
AC.sub.-- TEST.sub.-- MODE control signal is asserted high, the test mode
of operation is selected such that the master section 43 and the slave
section 42 operates together to provide a performance test function for an
integrated circuit device in which the scannable D-flip-flops are located.
A more detailed discussion of the scan and test modes will be described
below.
When the scan mode is selected (AC.sub.-- TEST.sub.-- MODE is low), the "0"
input lines of multiplexers 74 and 75 of the scan clock driver circuit in
FIG. 6b are selected. The input of scan clock driver circuit 71 receives
the scan clock signal SCK and is coupled to inverter 72 which is coupled
to the "0" input select line of multiplexer 75 such that the output of
multiplexer 75, SCKN, has the opposite polarity of SCK in the scan mode.
Furthermore, the input of the scan clock driver circuit is coupled to
inverter 72 which is coupled to the "0" input select line of multiplexer
74 through inverter 73 such that the output of multiplexer 74, SCKP, has
the same polarity as SCK in the scan mode.
On a first subcycle of the scan clock signal, when SCK is low and
SCK.sub.-- is high such that SCKP is low and SCKN is high, transmission
gates 63 and 60 are turned on and transmission gates 65 and 67 are turned
off. The input data signal D is inverted by inverter 62, reinverted to its
original polarity by inverter 64, and then inverted by inverter 66. Since
transmission gates 65 and 67 are turned off, the input data signal SI is
prevented from passing from master section 43 to slave section 42 and from
latching into master section 43.
On a second subcycle of the scan clock signal, when SCK is high and
SCK.sub.-- is low such that SCKP is high and SCKN is low, transmission
gates 63 and 60 are turned off and transmission gates 65 and 67 are turned
on such that the input signal SI latches into master section 43 by
circling the loop formed by inverters 64 and 66. Furthermore assuming the
system clock signal CK is low and CK.sub.-- is high such that
transmission gate 61 is turned on during the scan mode, the input signal
SI is passed from master section 43 to slave section 42, inverted by
inverter 57, and reinverted to its original polarity by inverter 58 and
appearing as the output signal Q. During the second subcycle, master
section 43 is unaffected by any change in value of data input signal SI at
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