Memory controller with low skew control signal

Claims

What is claimed is:

1. An apparatus for controlling a memory in response to an access request from a processor, the apparatus and the memory each electrically coupled to the processor across a bus of the type having information transferred thereon that is aligned with a clock signal, the memory of the type for receiving at least one strobe control signal, the apparatus comprising:

(a) a memory control circuit for providing control signals to the memory in response to an access request, wherein the control signal generating circuit generates a strobe enable signal; and

(b) a strobe generating circuit, electrically coupled to receive the strobe enable signal and the clock signal, for providing a strobe control signal to the memory, the strobe generating circuit including:

(1) a first delay for delaying the clock signal by a first alignment delay value to generate a strobe clock signal;

(2) a second delay for delaying the strobe enable signal by a second alignment delay value to generate a delayed strobe enable signal; and

(3) an output device, electrically coupled to the memory, for gating the strobe clock with the delayed strobe enable signal to thereby provide the strobe control signal to the memory; wherein the first alignment delay value is selected to align the strobe control signal with the clock signal and the second alignment delay value is selected to align the delayed strobe enable signal with the strobe clock.

2. The apparatus of claim 1, wherein the memory control circuit comprises a state machine, and wherein the state machine generates additional control signals which are output directly to the memory in response to the access request.

3. The apparatus of claim 2, wherein the strobe enable signal has a duration of four cycles of the clock signal; whereby the strobe control signal includes a burst of four pulses of the strobe clock that are aligned with the clock signal at the memory.

4. The apparatus of claim 3, wherein the memory comprises a plurality of burst extended data out DRAMs, wherein the processor is an 80.times.86 compatible microprocessor, and wherein the bus is a system bus.

5. The apparatus of claim 4, wherein the apparatus is implemented in a system controller which is additionally coupled to an input/output bus, and wherein the system controller includes an arbitration controller for arbitrating access requests received across the system and input/output busses.

6. The apparatus of claim 1, wherein the first and second delays are programmable delays, each having a signal input, a signal output, and a select input for selecting a variable number of delay elements to insert between the signal input and signal output, and wherein the strobe generating circuit further comprises first and second registers respectively coupled to the select inputs of the first and second delays to store first and second delay counts related to the number of delay elements which respectively correspond to the first and second alignment delay values.

7. The apparatus of claim 6, wherein the delay elements of each delay include inputs and outputs and are coupled in series with one another, with the input of a first delay element electrically coupled to the signal input of the delay, and wherein each delay further includes a multiplexer having a plurality of inputs coupled to the outputs of the delay elements, and an output, coupled to the signal output of the delay, which is selectively coupled to one of the plurality of inputs responsive to the select input.

8. The apparatus of claim 6, further comprising a delay control circuit, coupled to the first and second registers, for calculating the first and second delay counts, the delay control circuit including:

(a) a delay factor determining circuit for determining a delay factor for the apparatus which is related to the relative speed of the apparatus; and

(b) delay count generating means for calculating the first and second delay counts from the delay factor.

9. The apparatus of claim 8, wherein the delay factor determining circuit includes:

(a) a third programmable delay having a data input coupled to receive the clock signal, an output for providing a delayed clock signal, and a select input for selecting a variable number of delay elements to insert between the data input and the output;

(b) a detector, coupled to receive the clock signal and the delayed clock signal, for comparing the delayed clock signal with the clock signal and indicating when the delayed clock signal is aligned with the clock signal; and

(c) a compare circuit, coupled to the detector, for applying a third delay count to the select input of the third programmable delay to align the delayed clock signal with the clock signal; whereby the delay factor is related to the third delay count when the delayed clock signal and the clock signal are aligned.

10. The apparatus of claim 9, further comprising a third register electrically coupled to the compare circuit to store the third delay count and thereby provide the third delay count to the select input of the third programmable delay.

11. The apparatus of claim 10, wherein the compare circuit includes a start-up routine for selectively incrementing the third delay count until the detector indicates that the clock signal and the delayed clock signal are aligned.

12. The apparatus of claim 11, wherein the detector includes an edge-triggered D-type flip flop having an edge triggered clock input coupled to receive the clock signal, a D input coupled to receive the delayed clock signal, and an output coupled to the compare circuit, and wherein the compare circuit determines when the delayed clock signal and the clock signal are aligned by detecting a transition in the output of the D-type flip flop.

13. The apparatus of claim 10, wherein the delay count generating means includes:

(a) a look-up table for providing first and second delay counts in response to the third delay count stored in the third register; and

(b) means for storing the first and second delay counts in the first and second registers.

14. The apparatus of claim 13, wherein the first, second and third registers are addressable by the processor across the bus, and wherein the delay count generating means is implemented in software by the processor.

15. The apparatus of claim 10, wherein the delay count generating means includes a scaling circuit for calculating the first and second delay counts by scaling the third delay count by first and second scaling constants.

16. The apparatus of claim 10, wherein the delay factor generating circuit further includes an adjust routine for adjusting the first and second delay counts in response to temperature or voltage variations.

17. The apparatus of claim 16, wherein the first, second and third registers are counter registers which may be selectively incremented and decremented by an adjust signal provided by the compare circuit, and wherein the adjust routine periodically realigns the delayed clock signal with the clock signal by selectively applying the adjust signal to the third register to control the third delay count; whereby adjusting the third delay count likewise adjusts the first and second delay counts stored respectively in the first and second registers.

18. The apparatus of claim 17, wherein the adjust routine operates by first decrementing the third delay count until the rising edge of the delayed clock signal leads the rising edge of the clock signal, then incrementing the third delay count until the delayed clock signal and the clock signal are aligned.

19. A method of aligning a strobe control signal and a clock signal received by a memory device, that is coupled to a processor across a bus, comprising the steps of:

(a) generating a strobe enable signal in response to an access request from the processor;

(b) determining a first alignment delay having a value that, when summed with the propagation delay of the strobe control signal, is related to at least one integral cycle of the clock signal;

(c) determining a second alignment delay;

(d) delaying the clock signal by the first alignment delay to generate a strobe clock signal and delaying the strobe enable signal by the second alignment delay to generate a delayed strobe enable signal;

(e) gating the strobe clock with the delayed strobe enable signal to thereby provide the strobe control signal to the memory device such that the strobe control signal is aligned with the clock signal at the memory device;

wherein the first alignment delay is determined so as to align the strobe control signal with the clock signal and the second alignment delay value is determined so as to align the delayed strobe enable signal with the strobe clock.

20. The method of claim 19, wherein the generating step generates a strobe enable signal with a duration of four cycles of the clock signal; whereby the strobe control signal includes a burst of four pulses of the strobe clock that are aligned with the clock signal at the memory device.

21. The method of claim 20, wherein the delaying step includes the steps of passing the clock signal and the strobe enable signal through first and second programmable delays, the first and second programmable delays having select inputs respectively responsive to first and second delay counts, the first and second delay counts respectively related to numbers of delay elements relating respectively to the first and second alignment delay values.

22. The method of claim 21, wherein the determining step includes the steps of determining a delay factor for the controller, the delay factor being related to the relative speed of the controller, and generating the first and second delay counts from the delay factor.

23. The method of claim 22, wherein the delay factor determining step includes the steps of:

(a) delaying the clock signal with a third programmable delay to generate a delayed clock signal, wherein the amount of delay inserted into the delayed clock signal is related to a third delay count input to the programmable delay;

(b) comparing the delayed clock signal with the clock signal and indicating when the delayed clock signal is aligned with the clock signal; and

(c) selectively adjusting the third delay count to control the third programmable delay and thereby align the delayed clock signal with the clock signal; whereby the delay factor is related to the third delay count when the delayed clock signal and the clock signal are aligned.

24. The method of claim 23, wherein the adjusting step includes the step of, during start-up of the controller, selectively incrementing the third delay count until the clock signal and the delayed clock signal are aligned.

25. The method of claim 23, wherein the delay count generating step includes the step of accessing a look-up table of first and second delay counts indexed by the third delay count to provide the first and second delay counts.

26. The method of claim 23, wherein the delay count generating step includes the step of scaling the third delay count by first and second scaling constants to calculate the first and second delay counts.

27. The method of claim 23, further comprising the step of adjusting the first and second delay counts dynamically in response to temperature or voltage variations.

28. The method of claim 27, wherein the first, second and third delay counts are stored in counter registers coupled respectively to the select inputs of the programmable delays, and wherein the adjusting step includes the step of applying a common adjust signal to the counter registers to selectively increment or decrement the first, second and third delay counts until the delayed clock signal is aligned with the clock signal.

29. The method of claim 28, wherein the adjusting step operates by first decrementing the third delay count until the rising edge of the delayed clock signal leads the rising edge of the clock signal, then incrementing the third delay count until the delayed clock signal and the clock signal are aligned.

FIELD OF THE INVENTION

The invention is generally directed to a memory controller for coordinating transfer to and from one or more memory devices across a bus. More particularly, the invention is directed to a memory controller which provides a low skew control signal for coordinating the memory transfer with the memory devices across the bus.

BACKGROUND OF THE INVENTION

Signal skew poses many concerns in high speed data processing environments. By "skew", what is meant is a time shift in a signal, generally relative to a clock or other signal, which results in the transitions between individual data bits in a digital signal stream which are offset in time from the transitions in the clock.

A signal may be skewed, or out of alignment, relative to another signal either between individual integrated circuit chips, or within different areas of the same chip. This often occurs due to signal propagation delays along transmission lines and through integrated circuitry. A skewed signal poses a concern because it may result in errors due to missed data or register ripple-through. Often, to account for skew, one or more "wait states", or full clock cycles, may be added to a signal to ensure that the data is valid. However, the insertion of wait states into signals slows down processing and results in a slower information transfer.

Signal skew is conventionally handled in two manners. First, signal skew between different integrated circuit chips may be handled by low skew clock distribution networks. Often the skew between different chips is due to different transmission line lengths between a common signal source and the chips. This form of skew is often handled by making the signal lengths between the chips and the signal source the same, and/or by measuring the delays to the different chips and compensating for the delays using phase locked loops or inserted delays. However, it has been found that feedback systems for measuring and compensating for transmission delays may also introduce some skew. In addition, many of these systems do not account for signal propagation delays through the chips themselves.

Second, signal skew may be handled through internal chip clock synchronization to align signals throughout a chip. For example, one particular application which requires low skew signals is a memory controller, which coordinates data transfers to and from one or more memory devices across a bus. Memory controllers typically provide control signals to control the memory devices to receive or transmit data across the bus, for example to a processor or other controlling or peripheral devices.

The control signals generated by a conventional memory controller, however, often have at least some skew relative to the system clock which drives the bus. This is because some logic components are always downstream of a clock input when producing output signals in a chip, often resulting in a minimum of about 7-10 nanoseconds of skew. Often, conventional memory controllers must insert one or more wait states into the control signals to handle the access delays associated with the memory devices.

Further, as memory systems get faster, skew becomes more significant relative to the clock cycle, and the risk of errors increases. For example, memory devices such as DRAMs are capable of operating at 66 MHz or more (i.e., with 15 ns clock cycles). Other memory devices such as SRAMs may run even faster. With conventional memory controllers providing a minimum of 7-10 nanoseconds of skew in the control signal, the skew in the control signals may thus represent up to 67% of the total clock cycle.

Synchronous DRAMs are another option for minimizing control signal skew relative to a bus, as they receive a system clock directly and use the clock to gate control signals from a memory controller. This typically minimizes the propagation delay downstream of the gates in the memory devices, thereby minimizing the skew of the control signals. However, synchronous DRAMs are often not particularly desirable because space on memory devices is very expensive both economically and performance-wise, so any additional control circuitry on a memory device is generally discouraged.

Therefore, a substantial need exists for a memory controller which is capable of generating low skew control signals to control memory devices.

In addition, we have found that a unique concern exists with regard to signal skew in applications which utilize memory devices having enhanced memory transfer modes such as page mode and extended data out (EDO) mode, where memory addresses located within the same page or column of a memory device may be transferred without having to repeatedly send full address information to the device for each memory location. In particular, we have found that the higher operating speeds and enhanced operating modes of many memory devices are beyond the capabilities of many conventional memory controllers. Since less delay is required when accessing multiple addresses in such memory devices, wait states, or slower transfer rates, are often the only available alternatives for many conventional memory controllers.

Therefore, in view of our realization of the inadequacy of conventional memory controllers in handling the particular concerns associated with the use of high speed memories operating in enhanced transfer modes, a substantial need has also arisen for a memory controller which is capable of generating low skew control signals to control such high speed enhanced mode devices.

SUMMARY OF THE INVENTION

The invention addresses these and other problems associated with the prior art in providing an apparatus which delays or skews a control signal to an electronic device such as a memory device relative to a clock signal from a system clock with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting the control signal to the electronic device substantially equals one or more integral clock cycles. As a result, the control signal received at the electronic device is substantially aligned with the clock signal, and therefore also with the bus to which the electronic device is connected. In effect, this results in synchronizing or realigning the asynchronously-generated control signal back into a synchronous environment. This is in contrast to conventional low skewed clock distribution and internal chip synchronization systems which fully remove signals from a synchronous domain and operate upon them asynchronously.

The invention has unique applicability with memory devices having enhanced memory transfer modes such as the EDO and page modes provided on many commercially available memory devices, as well as in higher speed memory devices, since in each of these applications, even a small amount of skew between a control signal and a clock signal may significantly degrade the overall performance of the system. Another enhanced operating mode which has become available, the Burst Extended Data Out (BEDO) transfer mode, has been found to be particularly suitable for use with preferred embodiments of the invention. The BEDO transfer mode permits bursts of memory addresses to be transferred 1-1-1 (i.e., with one address transferred per clock cycle). After loading initial memory address information, a memory controller may provide a strobe control signal to the memory device each clock cycle, and the memory device will perform the read or write transfer at the current address, then automatically increment the address pointer to point to the next memory address in the device. By virtue of the extremely low skew realized in preferred embodiments of the invention, we have been able to address the particular problems associated with memory devices implementing the BEDO transfer mode.

Moreover, in preferred embodiments of the invention, the added delay to a control signal for the purposes of realigning it with a clock signal will not substantially affect the performance of the overall system, since the initial delay inserted into the control signal will generally occur during the initial access time for the memory devices.

The preferred embodiments of the invention also address several additional concerns which are raised as a result of the practical difficulties in determining the propagation delay associated with outputting a control signal. In these embodiments, a propagation delay, or delay factor, for the memory controller may be calculated to determine the suitable alignment delay inserted into the control signals to realign them with the system clock.

In determining a delay factor, a process factor for the controller may be determined, which is related to the relative speed of the controller, and which varies based upon the particular properties of the materials used to construct the actual controller chip. Further, in operation, temperature and voltage variations will often modify the overall propagation delay inherent in an integrated circuit, and accordingly, the delay factor may be modified dynamically to account for real-time voltage and/or temperature variations.

Therefore, in accordance with one aspect of the invention, an apparatus is provided for controlling a memory in response to an access request from a processor, the apparatus and the memory each electrically coupled to the processor across a bus of the type having information transferred thereon that is aligned with a clock signal, the memory of the type for receiving at least one strobe control signal. The apparatus includes a memory control circuit for providing control signals to the memory in response to an access request, wherein the control signal generating circuit generates a strobe enable signal; and a strobe generating circuit, electrically coupled to receive the strobe enable signal and the clock signal, for providing a strobe control signal to the memory. The strobe generating circuit includes a first delay for delaying the clock signal by a first alignment delay value to generate a strobe clock signal; a second delay for delaying the strobe enable signal by a second alignment delay value to generate a delayed strobe enable signal; and an output device, electrically coupled to the memory, for gating the