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Claims  |
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What is claimed is:
1. In a computer implemented synthesis system, a subtractive method of generating a netlist having scan replaced sequential cells and satisfying determined optimization
constraints, said method comprising the computer implemented steps of:
(a) receiving a ranked list ordering sequential cells by their contribution to testability;
(b) receiving an input netlist including scan replaced sequential cells;
(c) determining a set of critical paths within said input netlist;
(d) selecting a selected critical path of said set of critical paths and identifying a first sequential cell and a second sequential cell located on either end of said selected critical path;
(e) provided said first sequential cell and said second sequential cell are both scan replaced, determining which sequential cell of said first and second sequential cells contributes least to testability, said step of determining performed using
said ranked list;
(f) within said input netlist, unscanning said sequential cell of said selected critical path that contributes least to testability; and
(g) repeating steps (c)-(f) while there are critical paths in said set of critical paths that have scan replaced cells and there are no worse critical paths that have no scan replaced cells.
2. A method as described in claim 1 wherein said input netlist originates from a test ready (TR) compiler.
3. A method as described in claim 1 wherein said input netlist is a fully scan replaced netlist.
4. A method as described in claim 1 wherein said input netlist is a fully scan replaced netlist including a loopback connection associated with each scan replaced sequential cell.
5. A method as described in claim 1 wherein said optimization constraints include timing constraints and wherein said step (c) comprises the steps of:
performing a timing analysis on said input netlist; and
identifying paths within said input netlist that do not satisfy said timing constraints based on said timing analysis.
6. A method as described in claim 5 wherein said step of performing a timing analysis on said input netlist comprises the step of performing a static timing analysis on said input netlist.
7. A method as described in claim 1 wherein said ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to testability, and wherein said step (e) comprises the steps of:
identifying a first rank number associated with said first sequential cell;
identifying a second rank number associated with said second sequential cell; and
determining which sequential cell of said first and second sequential cells contributes least to testability based on said first and said second rank numbers.
8. A method as described in claim 1 further comprising the steps of:
determining if one of fast and said second sequential cells is unscanned and if the other sequential cell is scan replaced; and
if said one sequential cell is unscanned and said other sequential cell is scan replaced, unscanning said scan replaced sequential cell regardless of said ranked list.
9. A method as described in claim 1 wherein said step (f) comprises the step of replacing said sequential cell that contributes least to testability by a functionally equivalent unscanned sequential cell.
10. A method as described in claim 1 wherein said optimization constraints include timing and area constraints and further comprising the steps of:
(h) provided area constraints are violated by said input netlist, identifying a selected scan replaced cell within said ranked list having a lowest rank value and unscanning said selected scan replaced cell within said input netlist; and
(i) repeating step (h) until all cells within said rank list are unscanned or until said area constraints are satisfied by said input netlist.
11. In a computer system having a processor coupled to a bus and a memory coupled to said bus, a computer implemented subtractive method of generating a netlist having scan replaced sequential cells and satisfying determined timing and area
constraints, said method comprising the computer implemented steps of:
(a) provided a timing critical selection is asserted, unscanning scan replaced sequential cells that violate said timing constraints, said step (a) comprising the steps of:
(1) accessing a ranked list ordering sequential cells by their contribution to testability;
(2) accessing a fully scan replaced input netlist;
(3) performing a timing analysis on said input netlist to determine a set of critical paths located therein;
(4) selecting a particular critical path of said set of critical paths and identifying a first sequential cell and a second sequential cell located on either end of said particular critical path;
(5) provided said first and second sequential cells are both scan replaced, determining which contributes least to testability, said step of determining performed using said ranked list;
(6) within said input netlist, unscanning said sequential cell of said particular critical path that contributes least to testability;
(7) repeating steps (3)-(6) while critical paths having scan replaced cells exist within said set of critical paths and no worse critical paths exist that have no scan replaced cells;
(b) provided said area constraints are violated by said input netlist, selecting a particular scan replaced cell within said ranked list having a lowest rank value and unscanning said particular scan replaced cell; and
(c) repeating step (b) until all cells within said ranked list are unscanned or until said area constraints are satisfied.
12. A method as described in claim 11 wherein said fully scan replaced input netlist originates from a test ready (TR) compiler.
13. A method as described in claim 11 wherein said input netlist includes a loopback connection associated with each scan replaced sequential cell.
14. A method as described in claim 11 wherein said step (3) comprises the steps off
performing a static timing analysis on said input netlist; and
identifying paths within said netlist that do not satisfy said determined timing constraints based on said static timing analysis.
15. A method as described in claim 11 wherein said ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to testability, and wherein said step (5) comprises the steps
of:
identifying a first rank number associated with said first sequential cell;
identifying a second rank number associated with said second sequential cell; and
determining which sequential cell of said first and second scan replaced sequential cells contributes least to testability based on said first and second rank number.
16. A method as described in claim 11 further including the steps of:
determining if one of said first and second sequential cells is unscanned and if the other sequential cell of said first and second sequential cells is scan replaced; and
if said one sequential cell is unscanned and said other sequential cell is scan replaced, unscanning said scan replaced sequential cell regardless of said ranked list.
17. A method as described in claim 11 wherein said step (6) comprises the step of replacing said sequential cell that contributes least to testability by a functionally equivalent unscanned sequential cell.
18. A computer system having a processor coupled to a bus and a computer readable memory coupled to said bus, said computer readable memory including a logic program stored therein for causing said computer system to generate a netlist having
scan replaced sequential cells and satisfying determined timing and area constraints, said logic program comprising:
(a) logic accessing a ranked list ordering sequential cells by their contribution to testability;
(b) logic accessing a fully scan replaced input netlist including scan replaced sequential cells;
(c) logic determining a set of critical paths within said input netlist by performing a timing analysis on said input netlist;
(d) logic selecting a particular critical path of said set of critical paths and identifying a first sequential cell and a second sequential cell associated with said particular critical path;
(e) logic determining if said first and second sequential cells are both scan replaced and, if so, also for determining which sequential cell of said first and second sequential cells contributes least to testability by accessing said ranked
list;
(f) logic unscanning said sequential cell of said particular critical path that contributes least to testability; and
(g) logic executing (c)-(f) while critical paths exit that include scan replaced cells and no worse critical paths exist that have no scan replaced cells.
19. A computer system as described in claim 18 wherein said input netlist originates from a test ready compiler.
20. A computer system as described in claim 18 wherein said input netlist includes a loopback connection associated with each scan replaced sequential cell.
21. A computer system as described in claim 18 wherein said (c) logic comprises:
logic performing a static timing analysis on said input netlist; and
logic identifying paths within said netlist that do not satisfy said determined timing constraints based on said static timing analysis.
22. A computer system as described in claim 18 wherein said ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to testability, and wherein said (e) logic comprises:
logic identifying a first rank number associated with said first sequential cell;
logic identifying a second rank number associated with said second sequential cell; and
logic determining which sequential cell of said first and second sequential cells contributes least to testability based on said first and second rank number.
23. A computer system as described in claim 18 further comprising:
logic determining if one of said first and second sequential cells is unscanned and if the other sequential cell is scan replaced; and
logic unscanning said scan replaced sequential cell regardless of said ranked list provided said one sequential cell is unscanned and said other sequential cell is scan replaced.
24. In a computer system, an additive method of generating a netlist having scan replaced sequential cells and satisfying determined timing constraints, said method comprising the computer implemented steps of:
(a) accessing a ranked list ordering sequential cells by their contribution to testability;
(b) accessing an unscanned input netlist including unscanned sequential cells and having an indication of its worst critical path;
(c) selecting a particular unscanned sequential cell from said ranked list starting from an end of said ranked list that identifies sequential cells having high contributions to testability;
(d) scanning said particular unscanned sequential cell within said input netlist provided said step of scanning does not worsen timing characteristics of said input netlist;
(e) selecting a next particular unscanned sequential cell from said ranked list; and
(f) repeating steps (d)-(e) for each unscanned sequential cell within said ranked list.
25. A method as described in claim 24 wherein said step (d) further comprises the steps of:
copying said input netlist to generate an input netlist copy;
scanning said particular unscanned sequential cell within said input netlist copy;
determining the worst critical path of said input netlist copy; and
scanning said particular unscanned sequential cell within said input netlist provided said worst critical path of said input netlist copy is not worse than said worse critical path of said input netlist.
26. A method as described in claim 25 wherein said step of determining the worst critical path of said input netlist copy comprises the step of performing a static timing analysis on said input netlist copy.
27. A method as described in claim 25 wherein said ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to testability.
28. A method as described in claim 25 wherein said step of scanning said particular unscanned sequential cell within said input netlist provided said worst critical path of said input netlist copy is not worse than said worse critical path of
said input netlist comprises the step of replacing said particular unscanned sequential cell with a functionally equivalent scannable sequential cell.
29. In a computer system, an additive method of generating a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said method comprising the computer implemented steps of:
(a) accessing a ranked list ordering sequential cells by their contribution to testability wherein said ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to
testability;
(b) accessing an unscanned input netlist including unscanned sequential cells and having an indication of its worst critical path;
(c) selecting a particular unscanned sequential cell from said ranked list starting from an end of said ranked list that identifies sequential cells having high contributions to testability;
(d) scanning said particular unscanned sequential cell, provided said step of scanning does not worsen timing characteristics or violate timing constraints of said input netlist, wherein said step (d) further comprises the steps of:
(1) copying said input netlist to generate an input netlist copy;
(2) scanning said particular unscanned sequential cell within said input netlist copy;
(3) determining the worst critical path of said copy of said input netlist;
(4) summing the areas of each logic and routing element of said input netlist copy to determine an area of said input netlist copy;
(5) scanning said particular unscanned sequential cell within said input netlist provided said worst critical path of said input netlist copy is not worse than said worse critical path of said input netlist and provided said area of said input
netlist copy does not violate said area constraints;
(e) selecting a next particular unscanned sequential cell from said ranked list; and
(f) repeating steps (d)-(e) for each unscanned sequential cell within said ranked list.
30. A method as described in claim 29 wherein said step (3) comprises the step of performing a static timing analysis on said input netlist copy.
31. A method as described in claim 29 wherein said step (5) comprises the step of replacing said particular unscanned sequential cell by a functionally equivalent scannable sequential cell.
32. A computer system comprising:
a processor coupled to a bus; and
a computer readable memory unit coupled to said bus, said memory unit having a program stored therein causing said computer system to generate a netlist having scan replaced sequential cells and satisfying determined timing and area constraints,
said program causing said processor to perform the steps of:
(a) accessing a ranked list ordering sequential cells by their contribution to testability wherein said ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to
testability;
(b) accessing an unscanned input netlist including unscanned sequential cells and having an indication of its worst critical path;
(c) selecting a particular unscanned sequential cell from said ranked list starting from an end of said ranked list that identifies sequential cells having high contributions to testability;
(d) scanning said particular unscanned sequential cell, provided said step of scanning does not worsen timing characteristics or violate timing constraints of said input netlist, wherein said step (d) further comprises the steps of:
(1) copying said input netlist to generate an input netlist copy;
(2) scanning said particular unscanned sequential cell within said input netlist copy;
(3) determining the worst critical path of said copy of said input netlist;
(4) summing the areas of each logic and routing element of said input netlist copy to determine an area of said input netlist copy;
(5) scanning said particular unscanned sequential cell within said input netlist provided said worst critical path of said input netlist copy is not worse than said worse critical path of said input netlist and provided said area of said input
netlist copy does not violate said area constraints;
(e) selecting a next particular unscanned sequential cell from said ranked list; and
(f) repeating steps (d)-(e) for each unscanned sequential cell within said ranked list. |
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Description |
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BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to the field of logic synthesis for integrated circuit devices. More particularly, aspects of the present invention relate to methods and apparatus for design for test within a logic synthesis system.
(2) Background of the Related Art
Complex integrated circuits are designed with the use of computer aided design (CAD) tools. Specifically, application specific integrated circuits (ASICs) and field programmable gate array (FPGA) circuits can be designed using a variety of CAD
tools. The development of ASICs and FPGA circuits with the aid of CAD tools is referred to as electronic design automatic or EDA. Design, checking and testing of large scale integrated circuits are so complex that the use of programmed computer systems
are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly became the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also
partly because considerable computation is required in order to achieve an efficient layout of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a
particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary
forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral
and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures and functions. At the logic level, the descriptions of the
circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer implemented compiler (also called a "silicon compiler"). The computer implemented compiler program processes this
description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a "netlist." The components of a netlist can include primitive cells such as
full-adders, NAND gates, NOR gates, XOR gates, latches and D-flip flops, etc. and their interconnections used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order
to generate a technology dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells
which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
An important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is known to take the mapped
netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of
applying test vectors is called stimulation of the design and the special memory cells and associated circuitry are referred to as DFT implementations. Issues concerning controllability deal with facilitating the application of the test vectors to the
circuitry to be tested. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its "mission mode" circuitry while the portions added to the integrated circuit to facilitate testability are called "test
mode" circuitry or DFT implementations. The resultant circuit therefore has two functional modes, mission and test.
An exemplary flow chart diagram of a typical logic synthesis process, including a DFT process, is shown in FIG. 1. The processes 200 described with respect to this flow chart is implemented within a computer system in a CAD environment. High
level design language (HDL) descriptions of the integrated circuit enter at block 201. Also accompanying the HDL 201 is a set of performance constraints 205 applicable to the design which typically include timing, area, power consumption, and other
performance related limitations that the compiler 225 will attempt to satisfy when synthesizing the integrated circuit design. Constraints 205 can also include non-performance related constraints such as structural and routing constraints. Compiler 225
consists of a generic compiler 203 (also called an HDL compiler, RTL synthesizer, or architectural optimizer) that inputs the HDL 201 description and generates therefrom a technology independent or "generic" netlist 207 which is also dependent on the
constraints 205. As discussed above, the netlist 207 is a list of technology independent components or operators and the interconnections between them.
The generic netlist 207 is then input to a design compiler 209 that includes a computer implemented logic optimization procedure and a mapping procedure which interfaces with a technology dependent cell library 230 (e.g., from LSI, VLSI, TI or
Xilinx technologies, etc.). The cell library 230 contains specific information regarding the cells of the specific technology selected such as the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in
the library 230. Logic optimization procedure of block 209 includes structuring and flattening procedures. The mapping procedure of block 209 generates a gate level mapped netlist 211 that is technology dependent having cells specifically selected to
satisfy the constraints 205. This gate level netlist 211 consists at this point of "mission mode" circuitry.
At block 212 of FIG. 1, DFT process 213 performs a particular test insertion process (here a scan) to implement testability cells or "test mode" cells into the overall integrated circuit design. In this process 213, memory cells of the mapped
netlist 211 are replaced with memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In one particular DFT process, these memory cells specially designed for test are called
scannable memory cells. The test vector patterns can be derived from combinational or sequential automatic test pattern generation (ATPG) processes depending on whether or not a full or partial scan is performed by the scan insertion process 213.
Process 213 also performs linking groups of scannable memory cells into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 213 is a scannable netlist 215 that
contains both mission and test mode circuitry.
A problem occurs in the prior art process of FIG. 1 in that the scan insertion process 213 does not take into account its impact on the mission mode design. Specifically, the addition of the testability cells (scannable cells), and
interconnections there between (chaining resources), and the addition of other dedicated connections required for operation of the scan chains (e.g., scan clock routing and scan enable signal routing) can cause the overall design to violate one or more
of the defined constraints 205.
Therefore, a second compile process 217 of FIG. 1 (full or incremental compile) is invoked by the prior art process 200 in order to more effectively optimize the scannable netlist 215 to the constraints 205. An incremental compile 217 does not
process all existing structure as in a full compile, it only applies high level logical optimization to the unmapped portions of the design. Those unmapped portions are then mapped using a technology dependent library. During a process iteration, an
incremental compile 217 always processes to decrease the circuit cost. However, although this second compile process 217 is only an incremental compile process, it applies mapping optimizations iteratively on the entire scannable netlist 215. As a
result, processing time to perform the second compile process 217 can be on the order of weeks given conventional CAD technology and circuit complexity.
Alternatively, many prior systems utilize a full compile as the second compile process 217. The full compile process is similar to process 225 in that the full compile process at 217 applies mapping and logic optimizations to the entire design,
not just the unmapped portions.
After the second compile process 217 of FIG. 1 completes, a scannable netlist 219 is again generated that contains the testability cells but that may or may not meet the original performance constraints 205. Therefore, at block 221, the prior
art then performs a test to determine if the scannable netlist 219 meets the constraints 205. If the netlist 219 meets the constraints, then at block 235, other circuit synthesis procedures continue until the integrated circuit design can be fabricated
onto a substrate and tested.
However, as is often the case, the addition of the testability cells by the scan insertion process 213 does not allow the second compile process 217 to meet constraints 205 without a design modification to the original HDL program 201. In such
case, the overall process 200 flows from block 221 back to the HDL 201 where the architect modifies the HDL program 201 so that the addition of the testability cells and other resources will eventually satisfy, when possible, the given constraints 205
after the incremental compile step 217 is again executed.
The prior art process 200 of FIG. 1 has several disadvantages. It is disadvantageous to execute a second substantial compile process 217 in an attempt to match the testability cells and linking resources to the given set of constraints.
Although this process can be an incremental compile step in that much of the gate level connections are not removed, mapping optimization portions of this compile process still operate in an iterative fashion over the entire design. The addition of this
second compile process, using conventional technology, delays the overall integrated circuit synthesis process by as much as one to two weeks. Even after this long delay, there are no guarantees that the incremental compile process 217 will generate a
scannable netlist satisfying the constraints 205. In this case, a time consuming task of returning to the HDL for redesign is required. This process involves the chip architect designers once more and, therefore, it is unclear under the prior art
system when a designer can sign off on his or her work in the design process. Another problem faced by prior art designs involving the introduction of scan cells for testability while maintaining optimization constraints (e.g., timing and area
constraints) is that the timing and area constraints cannot be met in some designs if the entire design is scan replaced. This is true no matter how many conventional compile processes are executed after the scan insertion block. Therefore, it would be
desirable to determine a set of sequential cells that can be scan replaced to just meet the timing and area constraints while offering significant testability for the design. What is needed is a system that effectively determines a set of sequential
cells within a design that can be scan replaced while satisfying given timing and area constraints of the design. The present invention provides this functionality. Further, what is needed is a system that can perform the above based on iterations
through determined critical paths of the design. The present invention additionally provides this functionality.
Accordingly, the present invention advantageously provides a system for effectively determining the mount of sequential cells within a design that can be scan replaced while satisfying given timing and area constraints of the design and still
offering significant testability for the design. It is an object of the present invention to provide the above within a selected set of scan cells that attempts to offer a high degree of testability given the timing and area constraints to be satisfied. It is an object of the present invention to provide a subtractive system for performing the above wherein a fully scan replaced netlist (that violates timing and area constraints) is input and selected cells are unscanned until the timing and area
constraints are met. It is another object of the present invention to provide an additive system wherein an unscanned netlist is received, and using a cell based or a critical path based system, cells are scanned that do not make the timing of the
original system any worse than originally submitted until a significant number of sequential cells are scan replaced or area constraints are violated. These and other objects of the present invention not specifically recited above will become clear
within discussion of the present invention herein.
SUMMARY OF THE INVENTION
A computer implemented process and system are described for effectively determining a set of sequential cells within a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability
while still maintaining specified timing and area constraints that are applicable to the design. The novel system selects sequential cells of the set for scan replacement that offer best testability contribution while not selecting sequential cells for
scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design.
The novel system is composed of a subtractive method and an additive method that individually operate on different netlist types. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are call scan replaced)
that does not meet determined optimization (e.g., area and/or timing) constraints. The subtractive process of the present invention can receive input, for example, from the output of a test ready compiler (TR) also of the present invention. The novel
subtractive system unscans selected scannable cells until the timing constraints are met if a timing critical flag is set by the user. Additional cells are unscanned if area constraints are violated. Selection for unscanning is based on a testability
cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned first. The additive process of the present invention receives an unscanned netlist (the "original design") and scan
replaces cells using the TCL until area constraints are violated or, if a timing-critical flag is set, until the performance of the design having the scan replaced cells are worse than the original design. An unscanned netlist for the additive process
can be output from an conventional compiler or can be an imported netlist. The additive system iterates through the TCL list with the cells offering the most contribution for testability scan replaced first. Cells on critical paths, or subcritical
paths that become critical when the cells are replaced, are not replaced if the user has asserted a timing-critical flag.
Specifically, embodiments of the present invention include, in a computer system having a processor coupled to a bus and a memory coupled to the bus, a computer implemented subtractive method of generating a netlist having scannable sequential
cells and satisfying determined optimization constraints (e.g., timing and area constraints), the method comprising the computer implemented steps of: receiving a ranked list ordering sequential cells by their contribution to testability; receiving a
fully scan replaced input netlist including scannable sequential cells, the input netlist not satisfying one of the determined optimization constraints (e.g., area and/or timing); if timing constraints are violated and the user has asserted a
timing-critical flag, determining a set of critical paths within the input netlist by performing a timing analysis on the input netlist and selecting a selected critical path of the set of critical paths and identifying a first and a second sequential
cell located on either end of the selected critical path and if both sequential cells are scannable, determining, using the ranked list, which sequential cell of the selected critical path contributes least to testability and unscanning that sequential
cell; repeating the above while critical paths with scannable sequential cells exist within the set of critical paths; and provided area constraints are violated, continue unscanning scannable cells that contribute least to testability until either area
constraints are met or until there are no more scannable cells in the netlist.
Embodiments further include the above and wherein if only one sequential cell of the first and second sequential cells is scan replaced, unscanning it regardless of the ranked list. Embodiments further include the above and wherein the input
netlist includes a loopback connection associated with each scannable sequential cell. Embodiments of the present invention include the above and wherein the ranked list comprises a list of sequential cells, each sequential cell having a rank number
identifying its relative contribution to testability, and wherein sequential cells are determined to contribute least to testability by their rank number within the ranked list. The present invention also includes a computer system implemented in
accordance with the above.
Embodiments of the present invention also include, in a computer system, an additive method of generating a netlist having scannable sequential cells and satisfying determined optimization constraints (e.g., timing and area constraints), the
method comprising the computer implemented steps of: (a) accessing a ranked list ordering sequential cells by their contribution to testability; (b) accessing an unscanned input netlist including unscanned sequential cells; (c) selecting a selected
unscanned sequential cell from the ranked list starting from an end of the ranked list that identifies sequential cells having high contributions to testability; (d) scanning the selected unscanned sequential cell, provided the step of scanning does not
worsen timing characteristics or violate timing constraints of the input netlist, wherein the step (d) further comprises the steps of: (1) copying the input netlist to generate an input netlist copy; (2) scanning the selected unscanned sequential cell
within the input netlist copy; (4) determining the worst critical path of the copy of the input netlist; (5) summing the areas of each logic and routing element of the input netlist copy to determine an area of the input netlist copy; (6) scanning the
selected unscanned sequential cell within the input netlist provided the worst critical path of the input netlist copy is not worse than the worse critical path of the input netlist and provided the area of the input netlist copy does not violate the
area constraints; (e) selecting a next selected unscanned sequential cell from the ranked list; and (f) repeating steps (d)-(e) for each unscanned sequential cell within the ranked list. The present invention also includes a computer system implemented
in accordance with the above.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow diagram illustrating a prior art process for logic synthesis with design for test implementations.
FIG. 2 is an exemplary computer system used in accordance with the present invention as a CAD system for design synthesis.
FIG. 3A is a diagram of a logic model including combinational logic and memory cells used by the present invention to represent the design of a synthesized integrated circuit.
FIG. 3B illustrates replacement performed by the present invention from non-scan memory cells specified by or inferred from the original HDL description into scannable memory cells used for DFT implementation.
FIG. 4 illustrates a procedure of the present invention (Design Rule Checker) that determines valid scan chains and marks as violated any scannable memory cell not part of a valid scan chain.
FIG. 5A illustrates an exemplary edge triggered D flip-flop used in the HDL description in an embodiment of the present invention.
FIG. 5B illustrates an exemplary scannable memory cell version of the memory cell presented in FIG. 5A according to an embodiment of the present invention.
FIG. 5C illustrates an exemplary edge triggered memory cell used in the HDL description that also contains other combinational logic in addition to the memory cell circuitry.
FIG. 5D illustrates an exemplary scannable memory cell version of the memory cell presented in FIG. 5C according to an embodiment of the present invention including other combinational logic present.
FIG. 6A illustrates an exemplary circuit implementation of a loopback line added by the test ready (TR) compiler of the present invention to simulate a linked scan chain where the loopback is taken from the output (Q).
FIG. 6B illustrates an exemplary circuit implementation of a loopback line added by the TR compiler of the present invention to simulate a linked scan chain where the loopback is taken from the inverted output (/Q).
FIG. 7 illustrates a task performed by the modified scan insertion process of the present invention where the scan chain is buffered in links that span more than one module allowing the loopback lines to accurately simulate this condition.
FIG. 8 is an overall flow diagram of the embodiments of the present invention starting from HDL description to the generation of test vectors having a scannable gate level netlist.
FIG. 9 is a flow diagram illustrating processes of the test ready (TR) compiler of the present invention.
FIG. 10 is an overall flow diagram illustrating processes of the modified scan insertion process of the present invention including the constraint driven compile process.
FIG. 11A and FIG. 11B represent a flow diagram illustrating processes of the constraint driven compile process of the modified scan insertion process of the present invention.
FIG. 12 is a flow diagram illustrating processes of the size design process of the constraint driven compile process of the present invention.
FIG. 13A and FIG. 13B illustrate an exemplary circuit transition performed by the phasing subprocess of the size design process shown in FIG. 12.
FIG. 14A and FIG. 14B illustrate an exemplary circuit transition performed by the buffering subprocess of the size design process shown in FIG. 12.
FIG. 15A and FIG. 15B illustrate an exemplary circuit transition performed by the downsizing subprocess of the size design process shown in FIG. 12.
FIG. 16A and FIG. 16B illustrate an exemplary circuit transition performed by the isolation subprocess of the size design process shown in FIG. 12.
FIG. 17A and FIG. 17B illustrate an exemplary circuit transition performed by the offloading subprocess of the size design process shown in FIG. 12.
FIG. 18A and FIG. 18B illustrate an exemplary circuit transition performed by the balancing subprocess of the size design process shown in FIG. 12.
FIG. 19A and FIG. 19B illustrate an exemplary circuit transition performed by the splitting subprocess of the size design process shown in FIG. 12.
FIG. 20 illustrates the present invention test ready (TR) compiler and modified scan insertion process within a hierarchical design illustrating the practical nature of the present invention on a chip level netlist.
FIG. 21A illustrates a top level flow diagram of the novel subtractive (e.g., partial) scan procedure of the present invention.
FIG. 21B illustrates a top level flow diagram of the novel additive (e.g., near full) scan procedure of the present invention.
FIG. 22A is a flow diagram of steps of the novel subtractive system of the present invention.
FIG. 22B illustrates a sample critical path (bounded by ranked sequential cells) involved in the processing of the novel subtractive system of the present invention.
FIG. 23A is a flow diagram of initial steps of the novel additive system of the present invention.
FIG. 23B is a flow diagram of steps of the novel additive system of the present invention.
FIG. 24 is a flow diagram illustrating an embodiment of the present invention using near full scan as a front end for the partial unscan process.
DETAILED DESCRIPTION OF THE INVENTION
In the following detailed description of the present invention numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present
invention may be practiced without these specific details. In other instances well known processes, methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions which follow are presented in terms of procedures, processes, and symbolic representations of operations on data bits within a computer memory. These procedure descriptions and representations are the
means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, process, or logic block is here, and generally, conceived to be a self-consistent sequence of steps
leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined,
compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of t | | |
