 |
Claims  |
|
|
What is claimed is:
1. In a computer implemented synthesis system, a method of generating a
netlist comprising the computer implemented steps of:
receiving an HDL specification representing a design to be realized in
physical form and storing said HDL specification in a computer memory
unit;
receiving constraints applicable to said design;
compiling said HDL specification with a compiler to produce a netlist
description of said design wherein said netlist comprises functional logic
blocks and connections there between including sequential cells and
combinational logic, said step of compiling further comprising the steps
of:
(i) replacing non-scan sequential cells specified in or inferred from said
HDL specification with scannable sequential cells specially adapted to
apply test vectors to combinational logic of said design; and
(ii) installing a loopback connection between an output and an input of
each scannable sequential cell;
storing said netlist description into said computer memory unit, said
netlist description including said scannable sequential cells and loopback
connections associated with said scannable sequential cells.
2. A method as described in claim 1 wherein said non-scan sequential cells
and said scannable sequential cells are level sensitive latches.
3. A method as described in claim 1 wherein said non-scan sequential cells
are D flip-flops and wherein said scannable sequential cells are
multiplexed input D flip-flops.
4. A method as described in claim 3 wherein said step of installing a
loopback connection between an output and input of each scannable
sequential cell installs a loopback connection between said output and a
multiplexed scan-in input of each scannable sequential cell.
5. A method as described in claim 3 wherein said step of installing a
loopback connection between an output and input of each scannable
sequential cell installs a loopback connection between an inverse output
and a multiplexed scan-in input of each scannable sequential cell.
6. A method as described in claim 1 wherein said step of replacing non-scan
sequential cells with scannable sequential cells specially adapted to
apply said test vectors comprises the steps of:
identifying a non-scan sequential cell for replacement, said non-scan
sequential cell including combinational logic and further having a first
identifier listing functions of said non-scan sequential cell;
scanning identifiers within a technology dependent library against said
first identifier to locate an equivalent scatunable sequential cell having
a second identifier including functions that match said functions of said
non-scan sequential cell; and
replacing said non-scan sequential cell with said equivalent scannable
sequential cell.
7. A method as described in claim 1 wherein said step of replacing non-scan
sequential cells with scannable sequential cells specially adapted to
apply said test vectors comprises the step of performing sequential
mapping based scan equivalence.
8. A method as described in claim 1 wherein said constraints define design
rule and performance limitations applicable to said design.
9. In a computer implemented synthesis system, a method of compiling an HDL
specification having associated design rule and performance constraints,
said method comprising the computer implemented steps of:
compiling said HDL specification to produce a netlist description of a
circuit design wherein said netlist comprises functional logic blocks and
connections there between, said step of compiling further comprising the
steps of:
(i) replacing non-scan sequential cells with scannable sequential cells
specially adapted to apply test vectors to combinational logic of said
design, said scannable sequential cells being technology dependent;
(ii) installing a loopback connection between an output and an input of
each scannable sequential cell to simulate a scan chain link; and
(iii) performing mapping optimization to modify results of said step of
installing a loopback connection in an effort to satisfy said design rule
and performance constraints; and
storing said netlist description into a memory unit of a computer system,
said netlist description including said scannable sequential cells and
said loopback connection of each scannable sequential cell.
10. A method as described in claim 9 wherein said non-scan sequential cells
and said scannable sequential cells are level sensitive latches.
11. A method as described in claim 9 wherein said non-scan sequential cells
are D flip-flops and wherein said scannable sequential cells are
multiplexed input D flip-flops.
12. A method as described in claim 11 wherein said step of instailing a
loopback connection between an output and input of each scannable
sequential cell installs a loopback connection between said output and a
multiplexed scan-in input of each scannable sequential cell.
13. A method as described in claim 11 wherein said step of installing a
loopback connection between an output and input of each scannable
sequential cell installs a loopback connection between an inverse output
and a multiplexer scan-in input of each scannable sequential cell.
14. A method as described in claim 9 wherein said step of replacing
non-scan sequential cells with scannable sequential cells specially
adapted to apply said test vectors comprises the steps of:
identifying a non-scan sequential cell for replacement, said non-scan
sequential cell including combinational logic and further having a first
identifier listing functions of said non-scan sequential cell;
scanning identifiers within a technology dependent library against said
first identifier to locate an equivalent scannable sequential cell having
a second identifier including functions that match said functions of said
non-scan sequential cell; and
replacing said non-scan sequential cell with said equivalent scannable
sequential cell.
15. A method as described in claim 9 wherein said step of replacing
non-scan sequential cells with scannable sequential cells specially
adapted to apply said test vectors comprises the step of performing
sequential mapping based scan equivalence.
16. A computer implemented synthesis system, said system having a processor
coupled to a memory unit wherein said processor is programmed to perform
logic processing, said system further comprising:
logic for receiving an HDL specification representing a design to be
realized in circuit form and storing said HDL specification in said memory
unit;
logic for receiving constraints applicable to said design;
compile logic for compiling said HDL specification to produce a netlist
description of said design wherein said netlist comprises functional logic
blocks and connections there between, said compile logic further
comprising:
(i) logic for replacing a genetic HDL specified or inferred sequential cell
with scannable sequential cells specially adapted to apply test vectors to
combinational logic of said design; and
(ii) loopback logic for installing a loopback connection between an output
and an input of each scannable sequential cell; and
store logic for storing said netlist description into said memory unit,
said netlist description including said scannable sequential cells and
said loopback connection of each scannable sequential cell.
17. A system as described in claim 16 wherein said (i) logic for replacing
further comprises:
translation logic for translating said generic HDL specified or inferred
sequential cell to a non-scan sequential cell that is technology
dependent; and
replacement logic for replacing said non-scan sequential cells with said
scannable sequential cells specially adapted to apply test vectors to
combinational logic of said design.
18. A system as described in claim 17 wherein said non-scan sequential
cells are D flip-flops and wherein said scannable sequential cells are
multiplexed input D flip-flops.
19. A system as described in claim 18 wherein said loopback logic installs
a loopback connection between said output and a multiplexed scan-in input
of each scannable sequential cell.
20. A system as described in claim 18 wherein said loopback logic installs
a loopback connection between an inverse output and a multiplexed scan-in
input of each scannable sequential cell.
21. A system as described in claim 17 wherein said non-scan sequential
cells and said scannable sequential cells are level sensitive latches.
22. A system as described in claim 17 wherein said replacement logic
comprises:
logic for identifying a non-scan sequential cell for replacement, said
non-scan sequential cell including combinational logic and further having
a first identifier listing functions of said non-scan sequential cell;
logic for scanning identifiers within a technology dependent library
against said first identifier to locate an equivalent scannable sequential
cell having a second identifier including functions that match said
functions of said non-scan sequential cell; and
logic for replacing said non-scan sequential cell with said equivalent
scannable sequential cell.
23. A system as described in claim 17 wherein said constraints define
design rule and performance limitations applicable to said design.
24. A system as described in claim 17 further comprising a design rule
checker analyzing said netlist description produced by said compile logic,
said design rle checker identifying and marking as violated scannable
sequential cells of said netlist description that cannot be part of a
valid scan chain.
25. A system as described in claim 17 wherein said HDL specification
represents a module of an overall integrated circuit design.
26. A computer implemented synthesis system, said system having a processor
coupled to a memory unit wherein said processor is programmed to perform
logic processing, said system further comprising:
logic receiving an HDL specification representing a design to be realized
in circuit form and storing said HDL specification in said memory unit;
logic receiving constraints applicable to said design;
compile logic compiling said HDL specification to produce a netlist
description of said design wherein said nefiist comprises scannable
sequential cells, functional logic blocks and connections there between,
said compile logic further comprising:
loopback logic installing a loopback connection between an output and an
input of each scannable sequential cell to simulate a scan link of a scan
chain for design for test implemented circuitry; and
store logic storing said netlist description into said memory unit, said
netlist description including scannable sequential cells and said loopback
connection of each scannable sequential cell.
27. A system as described in claim 26 further comprising a design rule
checker analyzing said netlist description produced by said compile logic,
said design rule checker identifying and marking as violated sequential
cells of said netlist description that cannot be part of a valid scan
chain.
28. A system as described in claim 26 wherein said compile logic further
comprises:
translation logic translating generic non-scan cells to technology
dependent non-scan cells; and
replacement logic replacing said non-scan cells with scannable sequential
cells specially adapted to apply test vectors to combinational logic of
said design.
29. A system as described in claim 28 wherein said scannable sequential
cells are multiplexed input D flip-flops.
30. A system as described in claim 28 wherein said loopback logic installs
a loopback connection between said output and a multiplexed scan-in input
of each scannable sequential cell.
31. A system as described in claim 28 wherein said constraints define
design rule and performance limitations applicable to said design.
32. In a computer implemented synthesis system, a method comprising the
computer implemented steps of:
receiving an HDL specification representing a design and storing said HDL
specification in a computer memory unit;
receiving performance constraints applicable to said design;
compiling said HDL specification with a compiler to produce a netlist
description of said design optimized to said performance constraints
wherein said netlist comprises functional logic blocks and connections
there between including generic sequential eelIs and combinational logic,
said step of compiling further comprising the step of:
replacing said generic cells of said HDL specification with scannable
sequential cells specially adapted to apply test vectors to combinational
logic of said design;
storing said netlist description into said computer memory unit, said
netlist description including said scarunable sequential cells; and
identifying and marking as violated those scannable sequential cells that
cannot be part of a valid scan chain and replacing said violated scannable
sequential cells with non-scan sequential cells.
33. A method as described in claim 32 wherein said step of replacing said
generic cells of said HDL specification with scannable sequential cells
specially adapted to apply test vectors to combinational logic of said
design comprises the steps of:
replacing said generic cells of said HDL specification with non-scan
sequential cells that are technology dependent;
replacing said non-scan sequential cells with scannable sequential cells
specially adapted to apply test vectors to combinational logic of said
design.
34. A method as described in claim 33 wherein said step of compiling
further comprises the step of installing a loopback connection between an
output and an input of each scannable sequential cell to simulate a scan
chain link and wherein said netlist description stored in said computer
memory unit includes said loopback connections.
35. A method as described in claim 34 wherein said non-scan sequential
cells are D flip-flops and wherein said scannable sequential cells are
multiplexed input D fliip-flops.
36. A method as described in claim 34 wherein said step of replacing said
non-scan sequential cells with scannable sequential cells specially
adapted to apply said test vectors comprises the steps of:
identifying a non-scan sequential cell for replacement, said non-scan
sequential cell including combinational logic and further having a first
identifier listing functions of said non-scan sequential cell;
scanning identifiers within a technology dependent library against said
first identifier to locate an equivalent non-scan sequential cell having a
second identifier including functions that match said functions of said
non-scan sequential cell; and
replacing said non-scan sequential cell with said equivalent scannable
sequential cell. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to the field of logic synthesis for
integrated circuit devices. More particularly, aspects of the present
invention relate to an HDL compiler and a scan insertion process used for
test implementations designed for circuit synthesis.
(2) Background of the Related Art
Complex integrated circuits are designed with the use of computer aided
design (CAD) tools. Specifically, application specific integrated circuits
(ASICs) and field programmable gate array (FPGA) circuits can be designed
using a variety of CAD tools. The development of ASICs and FPGA circuits
with the aid of CAD tools is referred to as electronic design automatic or
EDA. Design, checking and testing of large scale integrated circuits are
so complex that the use of programmed computer systems are required for
realization of normal circuits. This is partly because the integrated
devices are inherently complex and partly because the circuit design needs
to be decomposed into simpler functions which are recognized by the CAD
tool. It is also partly because considerable computation is required in
order to achieve an efficient layout of the resultant network. The result
of the computerized design process is a detailed specification defining a
complex integrated circuit in terms of a particular technology. This
specification can be regarded as a template for the fabrication of the
physical embodiment of the integrated circuit using transistors, routing
resources, etc.
Integrated circuit designs can be represented in different levels of
abstraction, such as the register transfer level (RTL) and the logical
level, using a hardware description language (HDL), also called high level
design language. Two exemplary forms of HDL are Verilog and VHDL. The
integrated circuit can be represented by different layers of abstractions
(e.g., behavioral levels, structural levels and gate levels). An RTL level
is an intermediary level of abstraction between the behavioral and
structural levels. HDL descriptions can represent designs of all these
levels.
The behavior levels and RTL levels consist generally of descriptions of the
circuit expressed with program-like constructs, such as variables,
operators conditional loops, procedures and functions. At the logic level,
the descriptions of the circuit are expressed with Boolean equations. The
HDL can be used along with a set of circuit constraints as an input to a
computer implemented compiler (also called a "silicon compiler"). The
computer implemented compiler program processes this description of the
integrated circuit and generates therefrom a detailed list of logic
components and the interconnections between these components. This list is
called a "netlist." The components of a netlist can include primitive
cells such as full-adders, NAND gates, NOR gates, XOR gates, latches and
D-flip flops, etc. and their interconnections used to form a custom
design.
In processing the HDL input, the compiler first generates a netlist of
generic primitive cells that are technology independent. The compiler then
applies a particular cell library to this generic netlist (this process is
called mapping) in order to generate a technology dependent mapped
netlist. The mapping process converts the logical representation which is
independent of technology into a form which is technology dependent. The
mapped netlist has recourse to standard circuits, or cells which are
available within a cell library forming a pan of the data available to the
computer system.
Compiler programs and mapping programs are well known in the an and several
of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et
al.
An important pan of the logic synthesis process involves designing for
testability. Programs that aid in the testability process of logic
synthesis are called design for test (DFT) processes. As part of DFT, it
is known to take the mapped netlist generated from a compiler and add
and/or replace certain memory cells and associated circuitry with special
memory cells that are designed to allow the application of test vectors to
certain logic portions of the integrated circuit. The act of applying test
vector is called stimulation of the design and the special memory cells
and associated circuitry are referred to as DFT implementations. Issues
concerning controllability deal with facilitating the application of the
test vectors to the circuitry to be tested. The same memory cells can be
used to capture the output of the circuitry for observation and compare
this output to the expected output in an effort to determine if circuit
(e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its
intended or expected operational function are called its "mission mode"
circuitry while the portions added to the integrated circuit to facilitate
testability are called "test mode" circuitry or DFT implementations. The
resultant circuit therefore has two functional modes, mission and test.
An exemplary flow chart diagram of a typical logic synthesis process,
including a DFT process, is shown in FIG. 1. The processes 200 described
with respect to this flow chart is implemented within a computer system in
a CAD environment. High level design language (HDL) descriptions of the
integrated circuit enter at block 201. Also accompanying the HDL 201 is a
set of performance constraints 205 applicable to the design which
typically include timing, area, power consumption, and other performance
related limitations that the compiler 225 will attempt to satisfy when
synthesizing the integrated circuit design. Constraints 205 can also
include non-performance related constraints such as structural and routing
constraints. Compiler 225 consists of a generic compiler 203 (also called
an HDL compiler, RTL synthesizer, or architectural optimizer) that inputs
the HDL 201 description and generates therefrom a technology independent
or "generic" netlist 207 which is also dependent on the constraints 205.
As discussed above, the netlist 207 is a list of technology independent
components or operators and the interconnections between them.
The generic netlist 207 is then input to a design compiler 209 that
includes a computer implemented logic optimization procedure and a mapping
procedure which interfaces with a technology dependent cell library 230
(e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library
230 contains specific information regarding the cells of the specific
technology selected such as the cell logic, number of gates, area
consumption, power consumption, pin descriptions, etc., for each cell in
the library 230. Logic optimization procedure of block 209 includes
structuring and flattening procedures. The mapping procedure of block 209
generates a gate level mapped netlist 211 that is technology dependent
having cells specifically selected to satisfy the constraints 205. This
gate level netlist 211 consists at this point of "mission mode" circuitry.
At block 212 of FIG. 1, DFT process 213 performs a particular test
insertion process (here a scan) to implement testability cells or "test
mode" cells into the overall integrated circuit design. In this process
213, memory cells of the mapped netlist 211 are replaced with memory cells
that are specially designed to apply and observe test vectors or panems to
and from portions of the integrated circuit. In one particular DFT
process, these memory cells specially designed for test are called
scannable memory cells. The test vector patterns can be derived from
combinational or sequential automatic test pattern generation (ATPG)
processes depending on whether or not a full or partial scan is performed
by the scan insertion process 213. Process 213 also performs linking
groups of scannable memory cells into scan chains so that the test vectors
can be cycled into and out of the integrated circuit design. The output of
the scan insertion process 213 is a scannable netlist 215 that contains
both mission and test mode circuitry.
A problem occurs in the prior art process of FIG. 1 in that the scan
insertion process 213 does not take into account its impact on the mission
mode design. Specifically, the addition of the testability cells
(scannable cells), and interconnections there between (chaining
resources), and the addition of other dedicated connections required for
operation of the scan chains (e.g., scan clock routing and scan enable
signal routing) can cause the overall design to violate one or more of the
defined constraints 205.
Therefore, a second compile process 217 of FIG. 1 (full or incremental
compile) is invoked by the prior art process 200 in order to more
effectively optimize the scannable netlist 215 to the constraints 205. An
incremental compile 217 does not process all existing structure as in a
full compile, it only applies high level logical optimization to the
unmapped portions of the design. Those unmapped portions are then mapped
using a technology dependent library. During a process iteration, an
incremental compile 217 always processes to decrease the circuit cost.
However, although this second compile process 217 is only an incremental
compile process, it applies mapping optimizations iteratively on the
entire scatmable netlist 215. As a result, processing time to perform the
second compile process 217 can be on the order of weeks given conventional
CAD technology and circuit complexity.
Altematively, many prior systems utilize a full compile as the second
compile process 217. The full compile process is similar to process 225 in
that the full compile process at 217 applies mapping and logic
optimizations to the entire design, not just the unmapped portions.
After the second compile process 217 of FIG. 1 completes, a scannable
netlist 219 is again generated that contains the testability cells but
that may or may not meet the original performance constraints 205.
Therefore, at block 221, the prior art then performs a test to determine
if the scannable netlist 219 meets the constraints 205. If the netlist 219
meets the constraints, then at block 235, other circuit synthesis
procedures continue until the integrated circuit design can be fabricated
onto a substrate and tested.
However, as is often the case, the addition of the testability cells by the
scan insertion process 213 does not allow the second compile process 217
to meet constraints 205 without a design modification to the original HDL
program 201. In such case, the overall process 200 flows from block 221
back to the HDL 201 where the architect modifies the HDL program 201 so
that the addition of the testability cells and other resources will
eventually satisfy, when possible, the given constraints 205 after the
incremental compile step 217 is again executed.
The prior art process 200 of FIG. 1 has several disadvantages. It is
disadvantageous to execute a second substantial compile process 217 in an
attempt to match the testability cells and linking resources to the given
set of constraints. Although this process can be an incremental compile
step in that much of the gate level connections are not removed, mapping
optimization portions of this compile process still operate in an
iterative fashion over the entire design. The addition of this second
compile process, using conventional technology, delays the overall
integrated circuit synthesis process by as much as one to two weeks. Even
after this long delay, there are no guarantees that the incremental
compile process 217 will generate a scannable netlist satisfying the
constraints 205. In this case, a time consuming task of returning to the
HDL for redesign is required. This process involves the chip architect
designers once more and, therefore, it is unclear under the prior art
system when a designer can sign off on his or her work in the design
process.
What is needed is a system that can reduce the time required to perform
circuit synthesis while providing effective DFT processes. The present
invention offers such advantageous functionality.
Accordingly, it is an object of the present invention to provide a time
efficient design synthesis system operable within a computer implemented
CAD system that includes effective DFT processes. It is further an object
of the present invention to provide the above with the elimination of the
second substantial compile process that is used in the prior art. It is
yet another object of the present invention to provide the compile process
with information relating to the impact of testability cells and resources
to the overall design so that this information can be accounted for during
the initial compilation phase. It is further an object of the present
invention to provide specific aspects of the initial compile process to a
modified scan insertion process so that the added testability cells and
resources can be processed to likely meet the constraints without
requiring a substantial second compilation process. To this end, it is an
object of the present invention to provide optimization procedures in a
modified scan insertion procedure that operate only on the test cells and
resources. These and other objects and advantages of the present invention
not specifically recited above will become clear within discussions of the
present invention herein.
SUMMARY OF THE INVENTION
A computer implemented process and system are described for providing an
test ready (TR) compiler with specific information regarding the impact of
added scannable test cells and resources on its mission mode design. In so
doing, the TR compiler optimizes with increased efficiency for the added
test resources so that predetermined performance and design related
constraints of the mission mode circuitry are maintained after addition of
the test resources. The TR compiler translates generic sequential cells
into technology dependent non-scan sequential cells. In the TR compiler,
during replacement, scannable memory cells are used in place of these
non-scan memory cells specified within the mission mode design and
therefore the TR compiler is informed of the characteristics of the
scannable memory cells and their links. For test, the scannable memory
celth are chained to each other to form scan chains. To account for this
chaining during compile, the TR compiler provides output driven loopback
connections to simulate the electrical characteristics of this chaining
during compile. In the above implementation, the TR compiler can
efficiently provide translation of an TR description having test
implementations into a gate level netlist. With the addition of certain
information regarding the test implementation (e.g., scan replacement is
done and loopback connections are added), the TR compiler of the present
invention better optimizes the overall design for the addition of the test
resources which are linked together for testability.
Specifically, embodiments of the present invention include, in a computer
implemented synthesis system, a method of generating a netlist having the
computer implemented steps of: receiving an HDL specification representing
a design to be realized in physical form and storing the HDL specification
in a computer memory unit; receiving constraints applicable to the design;
compiling the HDL specification with a compiler to produce a netlist
description of the design wherein the netlist comprises functional logic
blocks and connections there between including sequential cells and
combinational logic, the step of compiling further comprising the steps
of: translating generic non-scan cells to technology dependent non-scan
cells; replacing the non-scan sequential cells with scannable cells
specially adapted to apply test vectors to combinational logic of the
design; and installing a loopback connection between an output and an
input of each scannable sequential cell; and storing the nefiist
description into the computer memory unit, the netlist description
including the scannable sequential cells and the loopback connection
associated with each scannable sequential cell.
Embodiments of the present invention include the above and wherein the
non-scan sequential cells are D flip-flops and wherein the scannable
sequential cells are multiplexed input D flip-flops and wherein the step
of installing a loopback connection between an output and input of each
scannable sequential cell installs a loopback connection between the
output and a multiplexed scan-in input of each scannable sequential cell.
Embodiments of the present invention further include a system implemented
in accordance with the above.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow diagram illustrating a prior art process for logic
synthesis with design for test implementations.
FIG. 2 is an exemplary computer system used in accordance with the present
invention as a CAD system for design synthesis.
FIG. 3A is a diagram of a logic model including combinational logic and
memory cells used by the present invention to represent the design of a
synthesized integrated circuit.
FIG. 3B illustrates replacement performed by the present invention from
non-scan memory cells specified by or inferred from the original HDL
description into scannable memory cells used for DFT implementation.
FIG. 4 illustrates a procedure of the present invention (Design Rule
Checker) that determines valid scan chains and marks as violated any
scannable memory cell not pan of a valid scan chain.
FIG. 5A illustrates an exemplary edge triggered D flip-flop used in the HDL
description in an embodiment of the present invention.
FIG. 5B illustrates an exemplary scannable memory cell version of the
memory cell presented in FIG. 5A according to an embodiment of the present
invention.
FIG. 5C illustrates an exemplary edge triggered memory cell used in the HDL
description that also contains other combinational logic in addition to
the memory cell circuitry.
FIG. 5D illustrates an exemplary scannable memory cell version of the
memory cell presented in FIG. 5C according to an embodiment of the present
invention including other combinational logic present.
FIG. 6A illustrates an exemplary circuit implementation of a loopback line
added by the test ready (TR) compiler of the present invention to simulate
a linked scan chain where the loopback is taken from the output (Q).
FIG. 6B illustrates an exemplary circuit implementation of a loopback line
added by the TR compiler of the present invention to simulate a linked
scan chain where the loopback is taken from the inverted output (/Q).
FIG. 7 illustrates a task performed by the modified scan insertion process
of the present invention where the scan chain is buffered in links that
span more than one module allowing the loopback lines to accurately
simulate this condition.
FIG. 8 is an overall flow diagram of the embodiments of the present
invention starting from HDL description to the generation of test vectors
having a scannable gate level netlist.
FIG. 9 is a flow diagram illustrating processes of the test ready (TR)
compiler of the present invention.
FIG. 10 is an overall flow diagram illustrating processes of the modified
scan insertion process of the present invention including the constraint
driven compile process.
FIG. 11A and FIG. 11B represent a flow diagram illustrating processes of
the constraint driven compile process of the modified scan insertion
process of the present invention.
FIG. 12 is a flow diagram illustrating processes of the size design process
of the constraint driven compile process of the present invention.
FIG. 13A and FIG. 13B illustrate an exemplary circuit transition performed
by the phasing subprocess of the size design process shown in FIG. 12.
FIG. 14A and FIG. 14B illustrate an exemplary circuit transition performed
by the buffering subprocess of the size design process shown in FIG. 12.
FIG. 15A and FIG. 15B illustrate an exemplary circuit transition performed
by the downsizing subprocess of the size design process shown in FIG. 12.
FIG. 16A and FIG. 16B illustrate an exemplary circuit transition performed
by the isolation subprocess of the size design process shown in FIG. 12.
FIG. 17A and FIG. 17B illustrate an exemplary circuit transition performed
by the offloading subprocess of the size design process shown in FIG. 12.
FIG. 18A and FIG. 18B illustrate an exemplary circuit transition performed
by the balancing subprocess of the size design process shown in FIG. 12.
FIG. 19A and FIG. 19B illustrate an exemplary circuit transition performed
by the splitting subprocess of the size design process shown in FIG. 12.
FIG. 20 illustrates the present invention test ready (TR) compiler and
modified scan insertion process within a hierarchical design illustrating
the practical nature of the present invention on a chip level netlist.
DETAILED DESCRIPTION OF THE INVENTION
In the following detailed description of the present invention numerous
specific details are set forth in order to provide a thorough
understanding of the present invention. However, it will be obvious to one
skilled in the art that the present invention may be practiced without
these specific details. In other instances well known processes, methods,
procedures, components, and circuits have not been described in detail as
not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions which follow are presented in
terms of procedures, processes, and symbolic representations of operations
on data bits within a computer memory. These procedure descriptions and
representations are the means used by those skilled in the data processing
arts to most effectively convey the substance of their work to others
skilled in the art. A procedure, process, or logic block is here, and
generally, conceived to be a self-consistent sequence of steps leading to
a desired result. The steps are those requiting physical manipulations of
physical quantities. Usually, though not necessarily, these quantities
take the form of electrical or magnetic signals capable of being stored,
transferred, combined, compared, and otherwise manipulated. It has proven
convenient at times, principally for reasons of common usage, to refer to
these signals as bits, values, elements, symbols, characters, terms,
numbers, or the like.
It should be borne in mind, however, that all of these and similar terms
are to be associated with the appropriate physical quantities and are
merely convenient labels applied to these quantities. Unless specifically
stated otherwise as apparent from the following discussions, it is
appreciated that throughout the present invention, discussions utilizing
terms such as "processing" or "computing" or "calculating" or
"determining" or "displaying" or executing a procedure or the like, refer
to the action and processes of a computer system, or similar electronic
computing device, that manipulates and transforms data represented as
physical (electronic) quantities within the computer system's registers
and memories into other data similarly represented as physical quantities
within the computer system memories or registers or other such information
storage, transmission or display devices.
Specific aspects of the present invention are operable within a programmed
computer aided design (CAD) system. A CAD system operable to implement the
elements of the present invention is shown in FIG. 2. In general, the CAD
system of the present invention includes a computer system 112 which
includes a bus 100 for communicating information including address, data,
and control signals, a central processor 101 coupled with the bus 100 for
processing information and instructions, a random access memory 102
coupled with the bus 100 for storing information and instructions for the
central processor 101, a read only memory 103 coupled with the bus 100 for
storing static information and instructions for the processor 101, a data
storage device 104 such as a magnetic or optical disk and disk drive
coupled with the bus 100 for storing information and instructions, a
display device 105 coupled to the bus 100 for displaying information to
the computer user, an alphanumeric input device 106 including alphanumeric
and function keys coupled to the bus 100 for communicating information and
command selections to the central processor 101, a cursor control device
107 coupled to the bus for communicating user input information and
command selections to the central processor 101, and a signal generating
device 108 coupled to the bus 100 for communicating signals that are input
and output from the system 112.
Program instructions executed by the CAD system can be stored in RAM 102,
ROM 103, or in the storage device 104 and when executed in a group can be
referred to as logic blocks or procedures. It is appreciated that data
produced at the various logic synthesis stages of the present invention,
including representations of the different levels of abstraction of the
integrated circuit design, can also be stored in RAM 102, ROM 103 or the
storage device 104 as shown in FIG. 2.
The display device 105 of FIG. 2 utilized with the computer system 112 of
the present invention may be a liquid crystal device, cathode ray tube, or
other display device suitable for creating graphic images and alphanumeric
characters recognizable to the user. The cursor control device 107 allows
the computer user to dynamically signal the two dimensional movement of a
visible pointer on a display screen of the display device 105. Many
implementations of the cursor control device are known in the art
including a trackball, mouse, joystick or special keys on the alphanumeric
input device 105 capable of signaling movement of a given direction or
manner of displacement.
FIG. 3A illustrates a circuit model 300 utilized by the present invention
to represent a logic unit of an integrated circuit. The model 300 includes
a memory cell block 301 that outputs signals over line 311 to a
combinational logic block 305. Combinational logic 305 also outputs
signals over line 313 to drive inputs of the memory cells 301. Memory 301
receives a primary input signal 3 | | |
