An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a control signal in response to an output signal. The control signal may comprise a peak value of the output signal. The second circuit may be configured to generate a phase adjustment signal in response to the control signal. The third circuit may be configured to generate a second clock signal in response to the phase adjustment signal and a first clock signal. The second clock signal may clock the output signal.

A mixed signal integrated circuit is provided having analog and digital circuits coupled to receive respective analog and digital clocking signals. The analog circuit portion may involve switched capacitors which charge and discharge based on timing of the analog clocking signal. The critical sampling moments mandated by the analog clocking signal are purposefully delayed after a quiet time so that pre-existing, digitally induced noise does not impute error in the sampled or loaded voltages. A clocking generator is therefore presented which delays rising edges of the digital clocking signal from falling edges of the analog clocking signal. The amount of delay is chosen to ensure that asynchronously generated noise arising from the digital clocking signal does not substantially affect the critical sampled or loaded voltages. The digital circuit portion can therefore include a memory element having transitory bit lines and a sense amplifier coupled to receive voltages on those bit lines. The effect of noise introduced by the transitory bit lines and the operable sense amplifiers is minimized by designing the digital clocking signal leading edge to be delayed a fraction of 1/(2(N/M)) cycle of the digital clocking signal from a falling edge of the analog clocking signal. In this fashion, the settling time prior to sampling is a partial cycle of the digital clocking signal.

A system on chip with ADC having serial test mode. An integrated circuit having a processing system with a system clock and a data conversion circuit is provided that is operable to convert data between the analog and the digital domain, the data converter utilizing the system clock during normal operation. A clock isolation circuit is provided for isolating the operation of the data converter from the system clock during a test mode. A serial clock is provided for generating a serial clock during the test mode independent of a system clock. Control circuitry is then operable for controlling the data converter during the test mode to convert data utilizing the serial clock at times not coinciding with the rising and falling edges of the system clock, such control circuit operating in response to receiving a test control signal.

A mixed signal integrated circuit is provided having analog and digital circuits coupled to receive respective analog and digital clocking signals. The analog circuit portion may involve switched capacitors which charge and discharge based on timing of the analog clocking signal. The critical sampling moments mandated by the analog clocking signal are purposefully delayed after a quiet time so that pre-existing, digitally induced noise does not impute error in the sampled or loaded voltages. A clocking generator is therefore presented which delays rising edges of the digital clocking signal from falling edges of the analog clocking signal. The amount of delay is chosen to ensure that asynchronously generated noise arising from the digital clocking signal does not substantially affect the critical sampled or loaded voltages. The digital circuit portion can therefore include a memory element having transitory bit lines and a sense amplifier coupled to receive voltages on those bit lines. The effect of noise introduced by the transitory bit lines and the operable sense amplifiers is minimized by designing the digital clocking signal leading edge to be delayed a fraction of 1/(2(N/M)) cycle of the digital clocking signal from a falling edge of the analog clocking signal. In this fashion, the settling time prior to sampling is a partial cycle of the digital clocking signal.

A time domain data converter with output frequency domain conversion. A data conversion circuit is operable to receive a signal in the time domain and provide an output in the frequency domain. It includes a data converter for converting data from an analog format to a digital format in the time domain. It also includes a processor for processing the data in the digital format output from the data converter through a time domain/frequency domain transform to provide data in the digital format in the frequency domain. The output of the frequency domain operation or the time domain operation can be provided for output in response to the generation of a data ready signal.