 |
Claims  |
|
|
What is claimed is:
1. An electronic device having a first plurality of terminals for external
connection to a memory and a second plurality of terminals for external
connection to a system bus, comprising:
a memory controller circuit coupled to said first plurality of terminals;
configuration registers for storing configuration information for use by
said memory controller circuit in performing accesses to memory via said
first plurality of terminals;
a bus bridge circuit coupled to said second plurality of terminals for
transferring addresses and data, and comprising:
a request logic circuit for generating, responsive to at least one of the
addresses, a write request signal to said memory controller circuit
signaling an impending access to at least one of said configuration
registers; and
an enable circuit for enabling a write access to at least one of said
configuration registers responsive to receiving a reply signal;
wherein said memory controller circuit includes a reply logic circuit for
generating the reply signal responsive to the combination of the write
request signal from said request logic circuit and a signal in the memory
controller indicating the absence of a pending memory operation utilizing
current information in at least one of said configuration registers.
2. The device of claim 1, further comprising:
a microprocessor, coupled to the bus bridge circuit and to the memory
controller, having a processing unit operable to process digital data in
accordance with computer instructions, and implemented on a single
integrated circuit with the memory controller circuit, configuration
registers, and bus bridge circuit.
3. The device of claim 1, wherein the reply logic circuit comprises:
memory access logic circuitry, for generating a pending memory access
signal responsive to the memory controller circuit issuing a memory access
request signal or a memory refresh signal; and
reply signal generating logic, coupled to receive the pending memory access
signal and the request signal, for generating the reply signal.
4. The device of claim 1 wherein configuration registers comprise locations
for storing access controls for at least two addressable regions of an
address space.
5. The device of claim 4 wherein said memory controller circuit further
comprises a first selector logic circuit, responsive to at least some
addresses transferred by said bus bridge circuit and responsive to said
configuration register locations signifying access controls for the
addressable regions, for producing a control signal to said bus bridge
circuit.
6. The device of claim 5 further comprising:
a microprocessor, coupled to said memory controller circuit and to said bus
bridge circuit, and operable to process digital data in accordance with
computer instructions;
and wherein said memory controller circuit further comprises a second
selector logic circuit, responsive to addresses asserted by said
microprocessor and responsive to said configuration register locations
signifying access controls for the addressable regions, for enabling
memory access operations by said memory controller.
7. The device of claim 1 wherein said memory controller circuit further
comprises:
cache status logic for generating a pending writeback signal responsive to
receiving a signal indicating that at least one location of a cache memory
contains modified data;
and wherein the reply logic circuit comprises:
memory access logic circuitry, for generating a pending memory access
signal responsive to the memory controller circuit issuing a memory access
request signal or a memory refresh signal, or to the cache status logic
issuing the pending writeback signal; and
reply signal generating logic, coupled to receive the pending memory access
signal and the write request signal, for generating the reply signal.
8. The device of claim 7 wherein said cache status logic receives the state
of a plurality of dirty bits, each associated with a location of a cache
memory, and generates the pending writeback signal responsive to all or
one less than all of the plurality of dirty bits indicating that its
associated location of cache memory contains modified data.
9. The device of claim 1, wherein the information stored by the
configuration registers comprises memory access timing and memory address
information, for use by the memory controller circuit in performing
accesses to the memory.
10. The device of claim 9 wherein the configuration registers comprise a
plurality of memory array type registers, each for storing a code
indicating a column address width for a memory bank.
11. The device of claim 9, wherein the configuration registers comprise a
timing control register, for storing a code indicating an access time of
the memory.
12. The device of claim 9, wherein the configuration registers comprise a
plurality of top memory address registers, each for storing a top memory
address for an associated memory bank.
13. The device of claim 12, wherein the memory controller circuit
comprises:
comparison circuitry, coupled to receive a memory address and to receive
the contents of the top memory address registers, for selecting a memory
bank responsive to the relationship of the memory address to the top
memory addresses.
14. A method of operating an electronic device having a microprocessor, a
memory controller for controlling access to a memory, and having
configuration registers storing configuration information for use by the
memory controller in accessing memory, comprising the steps of:
requesting a write access to one of the configuration registers;
monitoring the operation of the memory controller to detect whether a
memory access is pending;
after the requesting step, and responsive to the monitoring step detecting
a pending memory access utilizing current information in at least one of
said configuration registers blocking write access to the configuration
registers; and
after the requesting step, and responsive to the monitoring step detecting
no pending memory access utilizing current information in at least one of
said configuration registers, enabling write access to said configuration
registers.
15. The method of claim 14, wherein the configuration registers comprise
memory access timing and memory address information, for use in accessing
memory.
16. The method of claim 15, wherein the configuration registers comprise a
plurality of top memory address registers, each for storing a top memory
address for an associated memory bank.
17. The method of claim 15, wherein the configuration registers comprise a
plurality of memory array type registers, each for storing a code
indicating a column address width for a memory bank.
18. The method of claim 15, wherein the configuration registers comprise a
timing control register, for storing a code indicating an access time of
the memory.
19. The method of claim 15, wherein the monitoring step comprises:
monitoring a first logic signal indicating whether a memory read/write
access is pending; and
receiving a second logic signal indicating whether a memory refresh
operation is pending.
20. The method of claim 19, wherein the monitoring step further comprises:
monitoring a third logic signal indicating whether a cache writeback
operation is pending. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
NOTICE
(C) Copyright, *M* Texas Instruments Incorporated 1995. A portion of the
disclosure of this patent document contains material which is subject to
copyright and mask work protection. The copyright and mask work owner has
no objection to the facsimile reproduction by anyone of the patent
document or the patent disclosure, as it appears in the Patent and
Trademark Office patent file or records, but otherwise reserves all
copyright and mask work rights whatsoever.
CROSS-REFERENCE TO RELATED APPLICATIONS
The following coassigned patent applications, all filed Dec. 22, 1994,
except as noted, are hereby incorporated herein by reference:
______________________________________
Serial No. Filing Date TI Case No.
______________________________________
08/363,198 December 22, 1994
TI-18329
08/363,109 December 22, 1994
TI-18533
08/363,673 December 22, 1994
TI-18536
08/363,098 December 22, 1994
TI-18538
08/362,669 December 22, 1994
TI-18540
08/362,325 December 22, 1994
TI-18541
08/363,543 December 22, 1994
TI-18902
08/363,450 December 22, 1994
TI-19880
08/363,459 December 22, 1994
TI-20173
08/363,449 December 22, 1994
TI-20175
08/362,302 December 22, 1994
TI-20177
08/362,351 December 22, 1994
TI-20178
08/362,288 December 22, 1994
TI-20180
08/362,367 December 22, 1994
TI-20181
08/362,033 December 22, 1994
TI-20182
08/362,701 December 22, 1994
TI-20183
08/363,661 December 22, 1994
TI-20185
08/362,702 December 22, 1994
TI-20186
08/401,105 March 8, 1995
TI-20202
______________________________________
Other patent applications and patents are incorporated herein by reference
by specific statements to that effect elsewhere in this application.
FIELD OF THE INVENTION
This invention generally relates to electronic circuits, computer systems
and methods of operating them.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in
connection with computer systems, as an example.
Early computers required large amounts of space, occupying whole rooms.
Since then minicomputers and desktop computers entered the marketplace.
Popular desktop computers have included the "Apple" (Motorola 680x0
microprocessor-based) and "IBM-compatible" (Intel or other x86
microprocessor-based) varieties, also known as personal computers (PCs)
which have become very popular for office and home use. Also, high-end
desk top computers called workstations based on a number of superscalar
and other very-high-performance microprocessors such as the SuperSPARC
microprocessor have been introduced.
In a further development, a notebook-size or palm-top computer is
optionally battery powered for portable user applications. Such notebook
and smaller computers challenge the art in demands for conflicting goals
of miniaturization, ever higher speed, performance and flexibility, and
long life between battery recharges. Also, a desktop enclosure called a
docking station has the portable computer fit into the docking station,
and improvements in such portable-computer/docking-station systems are
desirable. Improvements in circuits, integrated circuit devices, computer
systems of all types, and methods to address all the just-mentioned
challenges, among others, are desirable, as described herein.
SUMMARY OF THE INVENTION
Generally and in one form of the invention, an electronic device on a
single integrated circuit chip has a microprocessor with a processing unit
operable to process digital data in accordance with computer instructions,
and a first cache coupled to said processing unit. A second cache includes
a write-back cache which is at least ten times smaller than the first
cache, and coupled to the first cache.
Generally, another form of the invention has a memory controller circuit
for generating column addresses from addresses on an address bus. The
memory controller circuit includes a selector circuit having inputs for a
plurality of lines of the address bus, and an output for column addresses.
A control register has bits representing a particular memory array type
among a plurality of memory array types. A control circuit couples the
bits of the control register to the selector circuit thereby supplying the
column addresses from the plurality of lines in accordance with the
particular memory array type represented by the bits in the control
register.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 is a pictorial diagram of two notebook computer embodiments, one of
them being inserted into a docking station embodiment to provide a
combined system embodiment;
FIGS. 2A, 2B, and 2C are, respectively, a right-side profile view, plan
view, and rear elevation of the combined system of notebook and docking
station of FIG. 1;
FIG. 3 is an electrical block diagram of the FIG. 1 combined embodiment
system of improved notebook computer and docking station system to which
the notebook computer system connects;
FIG. 4 is an electrical block diagram of another embodiment of an improved
computer system for desktop, notebook computer and docking station
applications;
FIGS. 5, 6 and 7 are three parts of a more detailed electrical diagram
(partially schematic, partially block) of a preferred embodiment
electronic computer system for use in embodiments including those of FIGS.
3 and 4, wherein FIG. 5 shows microprocessor unit (MPU) and peripheral
control unit (PCU), FIG. 6 shows peripheral processor unit (PPU) and
peripherals, and FIG. 7 shows display and other elements;
FIG. 8 is a plan view of a preferred embodiment apparatus having a printed
wiring board and electronic components of the computer system of FIGS.
5-7;
FIG. 9 is a block diagram of a microprocessor unit (MPU) device embodiment
for the system of FIGS. 5-7;
FIG. 10 is a plan view of an integrated circuit with improved topography
for implementing the microprocessor unit of FIG. 9;
FIG. 11 is a block diagram of a peripheral processing unit (PPU) device
embodiment for implementing the PPU in the system of FIGS. 5-7;
FIG. 12 is a block diagram of a bus-quieting circuit embodiment;
FIG. 13 is a waveform diagram representing bus-quieting method steps;
FIG. 14 is a partially block, partially schematic diagram of a bus
interface embodiment of PPU 110 of FIG. 11 for bus types such as the X-bus
(XD) and intelligent drive electronics (IDE) types, improved with bus
quieting circuits and methods;
FIG. 15 is a state transition diagram representing an IDE bus control state
machine in the embodiment of FIG. 14;
FIG. 16 is a state transition diagram representing an XD bus control state
machine in the embodiment of FIG. 14;
FIG. 17 is a partially block, partially schematic diagram of the
microprocessor unit MPU 102 of FIGS. 5 and 9, emphasizing a device
embodiment with memory controller unit (MCU) and bus bridge for use in
system embodiments according to method embodiments as described;
FIG. 18 is a schematic diagram of part of the memory controller unit (MCU)
embodiment of FIG. 17;
FIG. 19 is a partially block, partially schematic diagram of a circuitry
embodiment part of the bus bridge of FIG. 17;
FIG. 20 is a schematic diagram of a circuitry embodiment part of the MCU of
FIG. 17, and FIG. 20 has connections which mate to lines in the bus bridge
schematic of FIG. 19;
FIG. 21 is a partially block, partially schematic diagram of address
comparison circuitry in the MCU of FIG. 17;
FIG. 22 is a partially block, partially schematic diagram of a DRAM control
block embodiment in the MCU of FIG. 17;
FIG. 23 is a partially block, partially schematic diagram of a column and
row address selector embodiment in the DRAM control block of FIG. 22 in
the MCU of FIG. 17;
FIG. 24 is a method embodiment flow diagram for BIOS software for loading a
Memory Array Type (MAT) register, and FIG. 24 mates with flow diagram FIG.
27;
FIG. 25 is a memory column address diagram for illustrating the operations
of the method of FIG. 24;
FIG. 26 is a block diagram of a system with the MCU of FIG. 17 connected to
a DRAM memory, for illustrating the operations of the method of FIG. 24;
FIG. 27 is a method embodiment flow diagram for BIOS software for loading a
Top Memory Address (TMA) register, and FIG. 27 mates with flow diagram
FIG. 24;
FIG. 28 is a diagram of memory address space in a particular bank for
illustrating an operation of determining a value MEMTOP in the operations
of the method of FIG. 27;
FIG. 29 is a diagram of a shifting process for generating a TMA value in
the operations of the method of FIG. 27;
FIG. 30 is a diagram of memory address space in a whole set of memory banks
for illustrating operations of determining value MEMTOP and TMA values in
the operations of the method of FIG. 27;
FIG. 31 is a diagram of an microprocessor device embodiment alternative to
that of FIG. 17; and
FIGS. 32-35 are schematic diagrams of a refresh control block in the MCU
embodiment of FIG. 17.
Corresponding numerals and symbols in the different figures refer to
corresponding parts unless otherwise indicated.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
In FIG. 1 a notebook-computer-and-docking-station system 5 has an
insertable or dockable notebook computer 6 shown being inserted along a
path of bold arrows into a docking station 7. A CRT (cathode ray tube)
display 8, a keyboard 9 and a mouse 10 are respectively connected to
mating connectors on a rear panel of docking station 7. Docking station 7
has illustratively four storage access drives, for example: 5.25 inch
floppy disk drive 11, 3.5 inch floppy disk drive 12, a CD (compact disc)
drive 13 and an additional floppy or CD drive 14.
Docking station 7 has a docking compartment 15 into which notebook computer
6 inserts securely against internal rear electrical connectors. Docking
compartment 15 in this embodiment accepts manual insertion of notebook
computer 6 along lateral guideways 16 and 17 using a minimum of mechanical
elements to achieve advantageous economy in cost of the physical docking.
A horizontal surface of guideway brackets or a horizontal panel as shown
provide physical support for notebook computer 6. In an alternative
embodiment, a motorized insertion mechanism associated with docking
compartment 15 holds, rearwardly moves and seats notebook computer 6
against either rear electrical connectors, lateral connectors or both.
Docking station 7 in this embodiment occupies a volume V=LWH equal to the
product of the length L, width W and height H of the form of a rectangular
solid. Notebook computer 6 also has a form of a rectangular solid with
volume v=l w h equal to the product of its own length l, width w, and
height h. The docking station 7 in this embodiment advantageously is
proportioned so that the width w of the notebook 6 exceeds at least 75%
and preferably 85% of the width W of the docking station. In this way, the
room left for keyboard 9 and user work space to the front of keyboard 9 is
advantageously sufficient to make docking station 7 as convenient to
locate as many conventional desktop computers. Drives are stacked in pairs
11, 12 and 13,14 providing extra ergonomically desirable height (user head
position level, low glare) for supporting display 8, reduced length L, and
efficient use of volume V. The weight distribution of the docking station
7 suits it for location on a desktop as shown, or for tower positioning
with docking station 7 resting on its right side-panel. In either
position, the drives 11,12 and 13,14 are suitable as shown, or
alternatively are mounted with the docking compartment 15 located
centrally between drives 11 and 13 on top, and drives 12 and 14 on the
bottom.
Notebook computer 6 has slits 18 for advantageous lateral ventilation both
in open air, and in a forced air ventilation environment of docking
station 7. Notebook computer 6 features front-facing slots of a 3.5 inch
floppy disk drive 19 and a card connector 20 (e.g. for flash memory, modem
or other insertable cards). These slots are accessible even when the
notebook computer 6 is docked.
A display panel 21 combined with a high-impact back panel is hingeably
mounted rearward on a high-impact mounting base 22. Looking to the left in
FIG. 1 is an identical but distinct notebook computer unit 6'. (For
economy of notation, additional numerals on notebook unit 6' are not
primed.)
Notebook unit 6' has display panel 21 raised to operating position relative
to base 22 in the portable environment. A 3.5 inch floppy diskette 23 and
a flash memory card 24 are shown near their respective insertion slits 19
and 20. A keyboard 25 mounts forwardly on base 22. To the rear of keyboard
25, and between keyboard 25 and display panel 21, lie (in order from right
to left) a recessed trackball 26 in a recess 27, an ON/OFF switch 28,
ventilation slits 29, a loudspeaker 30 beneath a protective grille,
further ventilation slits 31, and a SUSPEND/RESUME switch 32.
A physical protuberance or stud 33 is molded integrally with display panel
21 or affixed thereon, near a hinge so that when the display panel 21 is
closed against base 22, the stud 33 impinges against SUSPEND/RESUME switch
32 thereby putting the computer 6' in a Suspend mode whereby very little
power is consumed. Then when the panel 21 is reopened, the computer
resumes almost immediately with the current application program without
rebooting. ON/OFF switch 28 has no stud associated with it, so that the
user has the manual option to turn the notebook computer on or off and to
reboot when desired.
In still further features, notebook computers 6 and 6' have a display
brightness (e.g. backlighting) adjustment control 34 mounted low on the
right side of panel 21. An optional power supply 35 is powered from a
commercial power source to which an AC plug 36 connects. Power supply 35
in turn supplies battery recharge and supply voltages via a rear power
connector 37 to notebook computer 6'.
An infrared (IR) emitter/detector assembly 38 on notebook computer 6
provides two-way communication with a corresponding infrared
emitter/detector assembly on the back of notebook computer 6'. The two
computers 6 and 6' suitably communicate directly to one another when two
users are positioned opposite one another or otherwise such that the
computers 6 and 6' have the IR assemblies in line-of-sight. When the two
computers 6 and 6' are side-by-side, they still advantageously communicate
by reflection from an IR-reflective surface 39, such as the wall of a
conference room or side-panel of an overhead projector unit.
Docking station 7 has an AC power plug 40 connected to energize the docking
station circuitry as well as that of notebook computer 6 when the latter
is inserted into docking compartment 15. An AC Power On/Off switch 41 is
manually actuated by the user on the upper right front panel of docking
station 7 in FIG. 1.
Turning now to FIG. 2A, notebook computer 6 is shown inserted against a
power connector 45 of docking station 7 in a right profile view of the
assembly. A hard disk drive HDD and a power supply P.S. are visible in the
right profile view and in the plan view of FIG. 2. A ventilation fan 46
efficiently, quietly and with low electromagnetic interference, draws a
lateral air flow across a Docking PCB (Printed Circuit Board) of the
docking station, as well as through the notebook computer 6 having its own
printed circuit board. The ventilation flow continues through the
ventilation holes of power supply P.S. whereupon heated air is exhausted
by fan 46 broadside and outward from the rear panel of docking station 7,
as shown in the rear elevation detail of FIG. 2C.
The Docking PCB is supported low to the bottom panel 47 of an enclosure or
cabinet of the docking station 7.
As seen from the top in FIG. 2B, the enclosure has a left bay 48 for hard
disk drive HDD and power supply P.S., a wider middle bay 49 having mass
storage drives 11, 12, 13 and 14, and the docking PCB behind the docking
compartment 15, and then a right bay 50 into which a multimedia board 51,
a video teleconferencing board 52, and other boards of substantial size
readily fit from top to bottom of the enclosure.
For convenience and economy, several connectors 55 are physically mounted
and electrically connected to Docking PCB and are physically accessible
through a wide aperture in the rear of the enclosure. As shown in rear
elevation in FIG. 2C, connectors 55 include a keyboard connector KBD, a
mouse connector MS, a display connector VGA, a PRINTER port, a GAME port,
a local area network LAN connector, and an RJ-11 telephone jack or modem
port. A Multimedia connector and a teleconferencing Camera connector are
accessible at the rear of the right bay 50.
Emphasizing now the connector arrangement of the notebook computer 6 in
rear elevation, a series of these connectors are physically mounted and
electrically connected to an internal printed circuit board of notebook
computer 6. These connectors are utilized in two docking station and
system embodiments. In a first embodiment, shown in FIG. 2C, an
aperture-defining rectangular edge 58 provides physical access to several
of the connectors of notebook computer 6, thereby increasing the
connectivity of the combined system 6,7 to peripheral units as will be
discussed in connection with FIG. 3. In a second embodiment, the edge 58
is absent, and rear connectors of the docking station 7 mate to these
several connectors of notebook computer 6 as will be discussed in
connection with FIG. 4.
Looking from left to right in rear elevation of FIG. 2C, a power and
telephone connector 45 securely mounted to docking station 7 mates to
notebook computer 6. A telephone connector 59 of notebook 6 is suitably
obscured in the docking compartment 15, but available for use when the
notebook is used in the portable environment. A display connector 60, a
printer parallel port connector 61, and a disk drive connector 62 are
provided at the back of notebook 6. An optional mouse connector 63 and
keyboard connector 64 are provided next to IR emitter/detector 38.
At far right rear on notebook 6, a high-speed bus connector 65 mates
securely to a corresponding connector of docking station 7 so that
wide-bandwidth communication, such as by a PCI (Peripheral Component
Interconnect) type of bus is established between notebook 6 and docking
station 7. In this way, the notebook 6 contributes importantly to the
computing power of the combined system 5 comprised of notebook 6 and
docking station 7.
The physical presence of connector 45 on the left rear and connector 65 on
the right rear also contribute to the security of alignment and seating of
the notebook 6 in the docking compartment 15. Wide snap-springs of docking
compartment 15 click into shallow mating recesses of notebook 6,
completing the physical security of alignment and seating of notebook 6 in
docking compartment 15.
In FIG. 3, the docking station PCB has a docking station power supply 69
supplying supply voltage VCC to the components of the docking station.
Power supply 69 has Power On/Off switch 41, power plug 40, and supplies
operating and battery recharging power along power lines 70 through
connector 45 to notebook computer 6 which has a printed circuit board and
system 100 of interconnected integrated circuits therein as described more
fully in connection with FIGS. 5-7 and the later Figures of drawing.
In the docking station PCB, a main bus 71, such as a high bandwidth PCI
bus, interconnects via buffers 72, connector 65 and buffers 73 with a high
bandwidth bus 104 in system 100 of notebook 6. A docking station
microprocessor unit MPU and memory circuitry 74 preferably provides
advanced superscalar computing power that is connected to bus 71. A
display interface 76 receives display data and commands from bus 71 and
supplies video data out to CRT display monitor 8. A SCSI interface 77
communicates with bus 71 and can receive and send data for any suitable
SCSI peripheral. Video input circuit 52 receives video data from a video
camera, video recorder, or camera-recorder (CAMERA) and supplies this data
to bus 71 for processing. A LAN (Local Area Network) circuit 79 provides
two-way communication between the docking station 7 and to n other
computers having LAN circuits 79.1, . . . 79.n. Token ring, Ethernet, and
other advanced LANs are accommodated. An adapter 80 having an interface
chip therein provides communication with any LAN system and plugs into a
single same socket regardless of the LAN protocol. Such LAN circuitry is
described in coassigned U.S. Pat. No. 5,299,193 "Signal Interface for
Coupling a Network Front End Circuit to a Network Adapter Circuit" issued
Mar. 29, 1994 (TI-15009), which is hereby incorporated herein by
reference.
A digital signal processor circuit 81 is connected to bus 71, and is
adapted for voice recognition, voice synthesis, image processing, image
recognition, and telephone communications for teleconferencing and
videoteleconferencing. This circuit 81 suitably uses the Texas Instruments
TMS320C25, TMS320C5x, TMS320C3x and TMS320C4x, and/or TMS320C80 (MVP), DSP
chips, as described in coassigned U.S. Pat. Nos. 5,072,418, and 5,099,417,
and as to the MVP: coassigned U.S. Pat. No. 5,212,777 "SIMD/MIMD
Reconfigurable Multi-Processor and Method of Operation" and coassigned
U.S. Pat. No. 5,420,809, issued May 30, 1995, and entitled "Method of
Operating a Data Processing Apparatus to Compute Correlation", all of
which patents and application are hereby incorporated herein by reference.
An interface chip 82, such as a PCI to ISA or EISA interface, connects bus
71 with a different bus 83 to which a multimedia (MIDI) card 51 is
connected. Card 51 has an input for at least one microphone, musical
instrument or other sound source 84. Card 51 has an output accommodating
monaural, stereo, or other sound transducers 85. A SCSI card 86 interfaces
a document scanner to bus 83.
Still further peripherals compatible with the speed selected for bus 83 are
connected thereto via an I/O interface 87 which communicates with
connectors for the hard disk drive HDD, the floppy disk drive FDD 11,
mouse MS 10, keyboard KBD 9, the CD-ROM drive 13 and a printer such as a
laser printer.
A cursory view of the notebook 6 in FIG. 3 shows that various rear
connectors 60-64 are physically accessible through aperture 58 of FIG. 2C
allowing still additional peripherals to be optionally connected. For
example, the display connector 60 is connected to a second monitor 194 so
that multiple screen viewing is available to the docking station user.
Connector 59 of notebook 6 is connected through connector 45 to the RJ-11
telephone connector on the back of docking station 7 so that the user does
not need to do any more than insert notebook 6 into docking station 7
(without connecting to the rear of notebook 6) to immediately obtain
functionality from the circuits of notebook 6.
In FIG. 4, an alternative embodiment of docking station PCB has a
comprehensive connector 89 to which the connectors 60-64 of notebook 6
connect. The connectors 60-64 are not independently accessible physically
through any aperture 58 of FIG. 2C, in contrast with the system of FIG. 3.
In this way, when notebook 6 is inserted into docking compartment 15,
straight-through lines from connectors 60-64 through connector 89 pass
respectively to display 8, to a PRINTER peripheral, to floppy disk drive
FDD, to mouse MS, and to keyboard KBD. Comprehensive connector 89 not only
accommodates lines from a bus to bus interface 90 to bus buffers 72,
cascaded between buses 104 and 71, but also has an HDD path from notebook
6 to the internal hard disk drive HDD of docking station 7.
< | | |
