A maximum/minimum value determination apparatus for determining a maximum/minimum value between two digital signals includes two conversion modules each of which receives a first digital signal and a second digital signal and outputs a first analog signal and a second analog signal respectively, where the first analog signal and the second analog signal are respectively linearly related to the first digital signal and the second digital signal. A difference amplifier is connected to the two conversion modules for receiving the first analog signal and the second analog signal and outputting a selecting signal which is either a logical high signal or a logical low signal according to a difference between the first analog signal and the second analog signal. A first multiplexer is adapted to receive the first digital signal, the second digital signal, and the selecting signal and output a maximum of the first digital signal and the second digital signal according to the selecting signal. A second multiplexer adapted to receive the first digital signal, the second digital signal, and the selecting signal and output a minimum of the first digital signal and the second digital signal according to the selecting signal.

An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.

A saturation-capable arithmetic logic unit (ALU) includes a general-purpose comparator coupled to receive a data value and a saturation threshold value during a saturation operation. Using the general-purpose comparator of the ALU for saturation minimizes circuit area without adversely affecting microprocessor performance. In an unsigned saturation operation, the data value is replaced with the threshold value when the data value is greater than the threshold value. In a signed saturation operation, positive data values are compared with an upper threshold value and negative data values are compared with a lower threshold value. In this manner, the data value need only be compared to either the upper or lower threshold value, rather than both. If the data value falls outside the bounds set by the upper and lower threshold values, the data value is replaced with the nearest threshold value.

An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.

In digital processing, a method and circuit for implementing at least one of a maximum and a minimum instruction between a source operand and a destination operand in which an arithmetic operation is performed using the source and destination operands to generate a result and the storage of data in a destination storage is controlled in accordance with the sign of the source operand, the sign of the destination operand and the sign of the said result.