Process for manufacturing an interconnect for testing a semiconductor die

What is claimed is:

1. A method for forming an interconnect for making an electrical connection with a semiconductor die, said method comprising:

providing a substrate;

forming a raised contact on the substrate corresponding to a contact location on the die;

etching a portion of the substrate subjacent to the raised contact to form a tip portion of the raised contact as a flexible membrane; and

forming a conductive layer on the raised contact insulated from the substrate by an insulating layer.

2. The method as claimed in claim 1 and further comprising forming a projection on the raised contact for penetrating the contact location on the die to a limited penetration depth.

3. The method as claimed in claim 1 and further comprising testing a semiconductor die using the interconnect.

4. The method as claimed in claim 1 and further comprising forming an etch stop to control an end point during etching of the interior portion of the raised contact.

5. The method as claimed in claim 1 and wherein the raised contact is formed as a raised pillar by anisotropically etching the substrate.

6. The method as claimed in claim 1 and wherein a penetrating projection is formed on the raised contact for penetrating the contact location on the die to a limited penetration depth and the raised contact is formed with a height to provide a separation distance between the die and interconnect.

7. A method for forming an interconnect for making an electrical connection with a semiconductor die, said method comprising:

providing a substrate with a first and second side;

forming a first mask on the substrate and etching the first side of the substrate to form a raised projection for penetrating a contact location on the die;

forming a second mask on the raised projection and etching the first side of the substrate to form a raised contact with the projection thereon;

forming a third mask on the substrate and etching the second side of the substrate to form a tip portion of the raised contact as a flexible membrane with a desired thickness; and

forming a conductive layer on the raised contact insulated from the substrate by an insulating layer.

8. The method as claimed in claim 7 and further comprising forming a conductive trace on the substrate in electrical communication with the conductive layer.

9. The method as claimed in claim 7 and further comprising forming an elastomeric member on the interconnect for contacting the die.

10. The method as claimed in claim 7 and wherein the second side of the substrate is etched with a hollow pocket subjacent to the raised contact.

11. The method as claimed in claim 7 and wherein the second side of the substrate is etched with an elongated groove subjacent to the raised contact.

12. The method as claimed in claim 7 and further comprising implanting a dopant in the substrate to a desired depth to control an endpoint during etching of the second side of the substrate.

13. The method as claimed in claim 7 and further comprising placing the interconnect and die in a carrier adapted to bias the die and interconnect together with a force.

14. The method as claimed in claim 7 and wherein the raised contacts are formed with a height to permit a desired separation of the die and interconnect.

15. The method as claimed in claim 7 and further comprising forming a fourth mask on the substrate and etching the first side of the substrate with a recess such that the contact member is formed in the recess.

16. A method for forming an interconnect for making an electrical connection with a semiconductor die, said method comprising:

providing a substrate having a first side and a second side;

forming a first mask on the first side of the substrate and etching the substrate to form a raised projection adapted to penetrate the die to a limited penetration depth;

forming a second mask having a masking block covering the raised projection and etching the substrate to form a raised contact adapted to contact a contact location on the die, said raised contact having a tip portion with the projection thereon, said raised contact having a height for separating the substrate and interconnect by a desired amount;

forming a third mask on the second side of the substrate and etching the substrate such that the tip portion of the raised contact is formed with a desired thickness;

forming an insulating layer on the substrate; and

forming a conductive layer on the raised contact insulated from the substrate by the insulating layer.

17. The method as claimed in claim 16 and further comprising biasing the interconnect against the die with a force for establishing a temporary electrical connection for testing the die.

18. The method as claimed in claim 16 and wherein a plurality of raised contacts having a hollow etched pocket are formed corresponding to a plurality of contact locations on the die.

19. The method as claimed in claim 16 and wherein the raised contact is a continuous structure having a plurality of projections thereon corresponding to a plurality of contact locations on the die.

20. The method as claimed in claim 16 and further comprising forming a fourth mask on the first side of the substrate and etching the substrate to form a recess wherein the raised projection is formed.

21. The method as claimed in claim 20 and further comprising forming a groove in the recess and placing an elastomeric member in the groove for contacting the die.

22. The method as claimed in claim 16 and wherein the raised contact is formed by an anisotropic etch process as a pillar having sloped sidewalls.

23. The method as claimed in claim 16 and wherein the projection is formed by an anisotropic etch process as a blade having sloped sidewalls.

24. The method as claimed in claim 16 and wherein the substrate is formed of a material selected from the group consisting of monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, and ceramic.

25. The method as claimed in claim 16 and further comprising forming the raised contact with the height between about 50-100 .mu.m.

26. The method as claimed in claim 16 and further comprising controlling the thickness and dimensions of the tip portion to provide a desired amount of flexibility for the tip portion.

27. The method as claimed in claim 16 and further comprising controlling the thickness of the tip portion by forming an etch stop in the substrate for end pointing etching with the third etch mask.

28. The method as claimed in claim 26 and wherein the etch stop is formed by implanting a dopant into the substrate to a desired depth.

29. A method for forming an interconnect for making an electrical connection with a semiconductor die, said method comprising:

providing a substrate;

forming a raised contact on the substrate adapted to contact a contact location on the die;

implanting a dopant into the substrate to define a base for the raised contact;

etching an undoped portion of the substrate surrounding the raised contact to form said base with a flexible membrane portion and connecting portions attached to the substrate formed, said membrane portion and connecting portions formed of doped substrate; and

forming a conductive layer on the raised contact insulated from the substrate by an insulating layer.

30. The method as claimed in claim 29 and wherein a thickness of the membrane portion is determined by implanting the dopant to a first depth and a height of the connecting portions is determined by implanting the dopant to a second depth.

31. The method as claimed in claim 29 and wherein the base portion is generally rectangular shaped.

32. The method as claimed in claim 29 and further comprising forming a penetrating projection on the raised contact adapted to penetrate the contact location on the die to a limited penetration depth.

33. A method for forming an interconnect for making an electrical connection with a semiconductor die, said method comprising:

providing a flexible substrate;

forming a raised contact on the substrate adapted to contact a contact location on the die;

forming a support substrate having a pocket filled with an elastomeric material;

placing the flexible substrate on the support substrate with the raised contact atop the elastomeric material; and

forming a conductive layer on the raised contact insulated from the substrate by an insulating layer.

34. The method as claimed in claim 33 and further comprising forming a penetrating projection on the raised contact adapted to penetrate the contact location on the die to a limited penetration depth.

35. The method as claimed in claim 33 and wherein the elastomeric material is a silicone adhesive.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates to semiconductor manufacture and more particularly to a compliant interconnect suitable for making a temporary or permanent electrical connection to an unpackaged semiconductor die.

BACKGROUND OF THE INVENTION

Microelectronic packages, called "multi chip modules" or "hybrids", are assembled using unpackaged semiconductor dice. Prior to the assembly procedure, each unpackaged die must be tested to measure its quality and reliability. This has led to the development of test procedures suitable for testing unpackaged semiconductor dice. Known-good-die (KGD) refers to an unpackaged die having the same quality and reliability as the equivalent packaged die.

Testing includes burn-in testing wherein the dice are heated while the integrated circuits are electrically biased. In addition, the dice are subject to speed and functionality tests to check the performance of the integrated circuits and devices formed on the dice. Among the parameters tested are input and output voltages, capacitance and current specifications. Memory chips are also put through logic tests wherein data storage, retrieval capabilities and response times are measured.

For testing and burning-in unpackaged dice, temporary carriers have been used in the manufacturing process in place of conventional single chip packages. This type of carrier typically includes a base for retaining and housing a single die. The carrier also includes an interconnect that allows a temporary electrical connection to be made between an individual die and external test circuitry. Carriers for testing unpackaged dice are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al., U.S. Pat. No. 5,302,891 to Wood et al. and U.S. Pat. No. 5,408,190 to Wood et al., which are commonly assigned with the present application.

One of the key design considerations for a carrier is the method for establishing a temporary electrical connection with the bond pads on the die. With some carriers, the die is placed circuitry side down in the carrier and biased into contact with the interconnect. The interconnect contains the contact structure that physically aligns with and contacts the bond pads of the die. Exemplary contact structures include wires, needles, and bumps. The mechanisms for making electrical contact include piercing the native oxide of the bond pad with a sharp point, breaking or burnishing the native oxide with a bump, or moving across the bond pad with a contact adapted to scrub away the oxide. In general, each of these contact structures is adapted to form a low-resistance contact with the bondpad.

With this method for testing unpackaged semiconductor dice, it is preferable to perform the test procedure without damaging the die. The bond pads of a die are particularly susceptible to damage by the contact structure of the carrier during formation of the temporary electrical connection. It is also advantageous for the contact structure on the carrier to compensate for differences in the vertical location of the bond pads.

Besides testing of unpackaged dice to form known good die, it is sometimes necessary to establish a temporary electrical connection with semiconductor dice contained on a semiconductor wafer. As an example this can occur in the testing of the dice before singulation from the wafer. It is also sometimes necessary to establish a permanent electrical connection between unpackaged dice such as in the formation of multi chip modules.

The present invention is directed to an improved compliant interconnect suitable for establishing a temporary or permanent electrical connection with bond pads or other contact locations on a semiconductor die. The interconnect is adapted to make a low resistance electrical connection with a die without damaging the bond pads of the die. In addition the interconnect can be formed of a material such as silicon having a thermal coefficient of expansion matching that of a semiconductor die or wafer.

In view of the foregoing it is an object of the present invention to provide an improved compliant interconnect for semiconductor dice and a method for forming the interconnect.

It is yet another object of the present invention to provide an improved method for making a temporary or permanent electrical connection to semiconductor dice.

Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved compliant interconnect for semiconductor dice and a method for making the interconnect are provided. The interconnect is adapted to make an electrical connection to contact locations, typically bond pads, on unpackaged dice. The interconnect can be used for making a temporary electrical connection to a singulated die, or dice contained on a wafer, in order to test the integrated circuitry contained on the dice. The interconnect can also be used to establish a permanent electrical connection to one or more dice or for interconnecting multiple semiconductor dice.

In an illustrative embodiment the interconnect includes a silicon substrate and raised contact structures formed with an etched, hollow interior portion. The raised contact structures are formed with penetrating projections for penetrating the contact locations on the die to a limited penetration depth. The penetrating projections are formed on a flexible membrane portion of the contact Structures. The dimensions of the flexible membrane portion are controlled to provide a desired compliancy or spring constant for the contact structures. In addition, the contact structures are overlaid with a conductive material in electrical communication with conductive traces for conducting signals to and from the contact structures.

For testing an unpackaged semiconductor die the interconnect is used with a carrier adapted to hold the die and to bias the die and interconnect together.

In an alternate embodiment of the invention the interconnect includes contact structures formed on a compliant hollowed out base portion. The base portion is formed by implanting dopants into the substrate and then etching away the area of the substrate that has not been implanted.

In another alternate embodiment of the invention the interconnect includes raised contact members mounted on an etched pocket formed in a baseplate. The etched pocket can be filled with a compliant material such as a silicone adhesive. The etched pocket and compliant material can be sized for mounting one contact structure or several contact structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A-1F are schematic cross sectional views illustrating steps involved in a process for forming an interconnect in accordance with the invention;

FIG. 1CC is an enlarged schematic cross sectional view of a portion of the structure shown in FIG. 1C;

FIG. 2 is an enlarged perspective view partially cut away of a contact structure formed in accordance with the process illustrated in FIGS. 1A-1F;

FIG. 2A is an enlarged perspective view of an alternate embodiment contact structure;

FIG. 2B is an enlarged perspective view of an alternate embodiment contact structure;

FIG. 3 is a plan view of the interconnect and a semiconductor die superimposed on the interconnect;

FIG. 4 is a schematic cross sectional view of an interconnect constructed in accordance with the invention in use establishing an electrical connection with a semiconductor die;

FIG. 5 is a schematic cross sectional view illustrating an interconnect constructed in accordance with an alternate embodiment of the invention in use for testing a lead-on-chip semiconductor die;

FIG. 6 is an enlarged cross sectional view taken along section line 6--6 of FIG. 4;

FIGS. 7A-7F are schematic cross sectional views illustrating steps involved in a process for forming a compliant interconnect in accordance with an alternate embodiment of the invention;

FIG. 7FF is a plan view of FIG. 7F; and

FIGS. 8A and 8B are schematic cross sectional views of an alternate embodiment interconnect.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIGS. 1A-1F, a process for forming an interconnect adapted to establish an electrical connection with contact locations on a semiconductor die is shown. This electrical connection can be a temporary electrical connection for testing an unpackaged die or a permanent electrical connection such as for forming a multi chip module.

Initially, as shown in FIG. 1A, a substrate 10 is formed of a material having a coefficient of thermal expansion (CTE) that closely matches the CTE of a silicon die. Suitable materials for the substrate 10 include monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, and ceramic.

Next, as shown in FIG. 1B, an etch stop 12 is formed in the substrate 10 by implanting a portion 14 of the substrate 10 with a dopant such as boron. The dopant can be ion implanted and then driven into the substrate 10 to a desired depth by annealing using techniques that are known in the art. As will be further explained, the etch stop 12 is used to end point a subsequent etch process of a backside of the substrate 10.

As also shown in FIG. 1B, a first etch mask 16 is formed on a first surface 18 (i.e., backside) of the substrate 10. The etch mask 16 can be formed of a material such as silicon nitride (Si.sub.3 N.sub.4), by blanket depositing a layer of the material (e.g., CVD) followed by photopatterning and then etching (e.g., wet or dry etching). A typical thickness for the etch mask 16 is about 500 .ANG. to 3000 .ANG.. The etch mask 16 includes masking blocks 20 and openings 22 therebetween. An etch mask 16 formed of silicon nitride can be etched with a pattern of openings 22 using hot (e.g., 180.degree. C.) phosphoric acid. A dry etch process with a suitable etchant species can also be used for this etch. Viewed from above, the masking blocks 20 can be rectangular blocks formed in a parallel spaced pattern. This parallel spaced pattern corresponds to the spacing of contact locations on a semiconductor die.

Next, as shown in FIG. 1C, etched pockets 26 are formed in the substrate 10 using the first etch mask 16 (FIG. 1B). The pockets 26 can be etched in the substrate 10 using a wet or dry isotropic, or anisotropic, etch process. The etch stop 12 formed in the substrate 10 can be used to control the depth of the pockets 26. For a substrate 10 formed of silicon, a wet etchant such as a solution of KOH and H.sub.2 O can be utilized to anisotroprically etch the grooves 26. This type of etching is also known in the art as bulk micro-machining. The etched pocket 26 include sloped sidewalls 28. The slope of the sidewalls 28 is a function of the different etch rates of monocrystalline silicon along the different crystalline orientations. This etch angle is approximately 54.degree..

Following formation of the etched pockets 26, the first etch mask 16 (FIG. 1B) is stripped. With the first etch mask 16 formed of silicon nitride, the mask can be stripped using a wet etchant such as H.sub.3 P0.sub.4 that is selective to the substrate 10. As is apparent, the etch step for forming the etched pockets 26 can be performed after formation of the contact structure 24 (FIG. 1F). As will become apparent, the etch step for forming the etched pockets 26 controls a thickness of a membrane portion 42 (FIG. 1F) of the contact structure 24. In addition, as shown in FIG. 1CC, the etch process is controlled such that a width of the opening "y" on the surface 18 of the substrate 10 is selected to achieve a depth "z" and a width "x" at the bottom of the pocket 26.

As also shown in FIG. 1C, a second etch mask 29 having masking blocks 32, is formed on a second surface 34 (i.e., front side) of the substrate 10. The second etch mask 29 and masking blocks 32 can be formed as previously described out of a material such as silicon nitride (Si.sub.3 N.sub.4) by blanket depositing the material (e.g., CVD) followed by photopatterning and then etching (e.g., wet or dry etch).

Next, as shown in FIG. 1D, the exposed substrate 10 between the masking blocks 32 is etched to form penetrating projections 30. In this step a wet or dry isotropic, or anisotropic, etch process is used to form the projections 30 as the material under the masking blocks 32 is undercut by the etchant reacting with the substrate 10. In other words, the exposed substrate 10 between the masking blocks 32 etches faster than the covered substrate 10 under the masking blocks 32.

For an anisotropic etch, in which the etch rate is different in different directions, an etchant solution containing a mixture of KOH and H.sub.2 O can be utilized. This results in the penetrating projections 30 formed as blades having sidewalls that are sloped at an angle of approximately 54.degree. with the horizontal. As with the etched pockets 26, the slope of the sidewalls 28 of the penetrating projections 30 is a function of the different etch rates of monocrystalline silicon along the different crystalline orientations. The surface of the substrate 10 represents the (100) planes of the silicon which etches faster than the sloped sidewalls that represent the (111) plane. In addition to sloped sidewalls, the penetrating projections 30 include a tip portion. The width of the tip portion is determined by the width of the masking blocks 32 and by the parameters of the etch process. FIG. 6 clearly shows the shape of the penetrating projections 30.

In place of an anisotropic etch, an isotropic etch can be used to form the penetrating projections 30 with radiused sidewalls (not shown). For an isotropic etch in which the etch rate is the same in all directions, an etchant solution containing a mixture of HF, HNO.sub.3 and H.sub.2 O can be utilized. This will result in the projections 30 having a pointed tip and a radiused sidewall contour (not shown). The sidewall contour is controlled by the etch parameters (i.e., time, temperature, concentration of etchant) and by the width of the masking blocks 32.

The placement and peripheral dimensions of the penetrating projections 30 correspond to the placement and peripheral dimensions of contact locations, typically bond pads 48 (FIG. 6), on a semiconductor die 50. For example, bond pads on a die are typically polygonal shaped metal pads that are about 50-100 .mu.m on a side and spaced apart by about 50-100 .mu.m. The etched grooves 26 can also be located to correspond to the placement of the bond pads on the die. Furthermore, a greater or lesser number of penetrating projections 30 can be used and other patterns than the parallel space pattern of penetrating projections 30 can be used (e.g., square pattern, cross pattern, telescoping pattern).

The height of each projection 30 is preferably about 1/10 to 3/4 the thickness of a bond pad 48 (FIG. 6) on a semiconductor die 50. The projections 30 will therefore not completely penetrate the full thickness of the bond pad 48 and the surface 35 provides a stop plane for limiting further penetration of the projections 30 into the bond pad 48. In addition, the height of the projections 30 is selected to allow good electrical contact but at the same time to minimally damage the bond pad 48 (FIG. 6). As an example, the height of each penetrating projection 30 measured from a surface 35 of the substrate 10 to the tip of the projection 30 will be on the order of 2000-5000 .ANG.. This compares to the thickness of a bond pad that is typically on the order of 6000 to 10,000 .ANG.. Example spacing between the projections 30 would be about 5 .mu.m, while an example length of the projections 30 (i.e., dimension perpendicular to the cross section shown) would be from 3 to 10 .mu.m.

Next, as shown in FIG. 1E, the second etch mask 29 is stripped and a third etch mask 37 having masking blocks 36 is formed over the penetrating projections 30. The etch mask 37 and masking blocks 36 can be formed of a material such as silicon nitride as previously explained. The etch mask 37 is used to etch the substrate 10 along a profile 38 represented by the dotted lines to form raised contact structures 24 (FIG. 1F). As before, either a wet or dry isotropic or anisotropic etch process can be used to etch the substrate 10. Typical etching techniques comprise wet anisotropic etching with a mixture of H.sub.2 O. With an anisotropic etch the sidewalls 40 of the contact structures 24 will be sloped at an angle of about 54.degree. with the horizontal. As shown in FIG. 1F, this forms the contact structures 24 with sloped sidewalls and a generally pyramidally shaped cross section.

FIG. 2 shows a perspective view of the contact structure 24 with one side cut away to show the hollow nature of the contact structure 24. Alternately, depending on the size and shape of the masking blocks 36 (FIG. 1E) and 20 (FIG. 1B), a contact structure 24A can be formed as a continuous elongated structure. In this case an elongated groove 26A rather than an enclosed pocket 26 would be formed. The spaced contact structures 24A and penetrating projections 30A can be formed to correspond to the location of the bond pads 48 (FIG. 6) on a semiconductor die 50 (FIG. 6).

As another alternative and as shown in FIG. 2B, a contact structure 24BB can be formed with additional etched faces 49 by appropriately controlling the etch parameters.

The height of the contact structures 24 (or 24A) is selected to provide a separation distance of "A" (FIG. 6) between the die 50 and substrate 10. This helps to prevent particulate contaminants from preventing an electrical connection between the contact structure 24 (or 24A) and die 50. The height of each contact structure 24 (or 24A) measured from a surface of the substrate 10 will be on the order of 50-100 .mu.m and the width about 40-80 .mu.m. The length of each contact structure 24 will be approximately the same as the length of the substrate 10. The length of each contact structure 24A will be approximately the same as the width. Following formation of the contact structures 24 (or 24A), the third etch mask 37 is stripped using a suitable etchant as previously described.

The contact structures 24 (or 24A) include a flexible membrane portion 42 (or 42A) which functions as a compliant member. As clearly shown in FIG. 6, the membrane portion 42 can be formed with a thickness of (t) to achieve a desired amount of deflection and spring force (C) as the penetrating projections 30 are pressed into the bond pads 48 of the die 50 with a certain force. The spring constant (C) produced by the membrane portion 42 is dependent on its dimensions and material. These parameters can be related by the formula:

where C is the spring constant

w is the width of the membrane portion 42

t is the thickness of the membrane portion 42

l is the length of the membrane portion 42

E is the modulus of elasticity of the substrate 10

The dimensions for the membrane portion 42 can be controlled by placement of the etch stop 12 and by controlling the etch processes for forming the grooves 26 and penetrating projections 30. In general, higher values for the spring constant (C) can achieved with long, thin and narrow membrane portions 42. By way of example, grooves or asperities (not shown) on the bond pad 48 that can result from probe testing at the wafer level can be compensated for by deflection of the membrane portion 42 (or 42A).

Next, as shown in FIG. 1F, following the formation of the contact structures 24 (or 24A), an insulating layer 44 is formed over the contact structures 24 (or 24A) and substrate 10. The insulating layer 44 can be formed by oxidation of the substrate 10 such as by exposing the substrate 10 to an oxidizing atmosphere in a reaction chamber. Silicon dioxide can be deposited using plasma CVD techniques. Here TEOS (tetraethylorthosilane) can be injected into the reaction chamber to grow silicon dioxide (SiO.sub.2) at a temperature of about 400.degree. C. Another commonly used insulator suitable for this purpose is Si.sub.3 N.sub.4. A representative thic