Enhanced DRAM with single row SRAM cache for all device read operations

Claims

What is claimed as the invention is:

1. An integrated circuit memory device, comprising:

a random access memory array;

a single row decoder;

a single column decoder responsive to an externally supplied address signal on an address bus for accessing a specified subset of memory cells within said memory array;

said memory device further including a data bus for providing a signal indicative of data associated with said specified subset of memory cells;

a memory cache corresponding to a single row of said memory array and interposed between said single column decoder an said memory array, wherein corresponding locations in rows of both said memory cache and memory array may be addressed by said single column decoder, said memory cache for storing a row of said data associated with said specified subset of memory cells last accessed from said memory device;

a last row read register coupled to said address bus for indicating an address of said data stored in said memory cache; and

a comparator associated with said address bus and said last row read register far causing said data stored in said memory cache to be placed on said data bus if said address indicated in said last row read register corresponds to said address signal;

said memory cache and said memory array being configured so that all reads from said memory device are only from said memory cache.

2. The integrated circuit of claim 1 wherein said integrated circuit further comprises:

a coupling circuit interposed between said memory cache and said random access memory array for transferring data from another specified subset of memory cells within said random access memory array to said memory cache if said address indicated in said last row read register does not correspond to said address signal.

3. The integrated circuit of claim 2 further comprising an input/output control and data latch interposed between said memory cache and said data bus, said input/output control and data latch responsive to write, output and chip enable signals for coupling said data bus through said coupling circuit to said memory cache and said random access memory array.

4. The integrated circuit of claim 3 wherein said input/output control and data latch is responsive to a predetermined transition of said write enable signal to latch said signals on said data bus.

5. The integrated circuit of claim 3 wherein data applied to said data bus may be concurrently written to said memory cache and said memory array through said coupling circuit when said row address portion of said address signal corresponds to said address indicated in said last row read register.

6. The integrated circuit of claim 3 wherein data applied to said data bus may be written to said random access memory array through said coupling circuit when said row address portion of said address signal does not correspond to said address indicated in said last row read register.

7. The integrated circuit of claim 1 further comprising:

a column address latch interposed between said address bus and said single column decoder and responsive to a column address latch signal for selectively retaining a column address signal portion of said address signal on said address bus.

8. The integrated circuit of claim 7 wherein said column address latch signal is externally supplied to said memory device.

9. The integrated circuit of claim 7 further comprising:

a row address latch interposed between said address bus and said single row decoder and responsive to a row address latch signal for selectively retaining a row address signal portion of said address signal on said address bus.

10. The integrated circuit of claim 9 further comprising a row address and refresh control circuit responsive to a plurality of externally supplied signals for operatively controlling said row address latch, said last row read register and said memory cache.

11. The integrated circuit of claim 10 wherein said plurality of externally supplied signals comprises a row enable signal.

12. The integrated circuit of claim 11 wherein said data stored in said memory cache is placed on said data bus if said address indicated in said last row read register corresponds to said row address signal portion of said address signal when said row enable signal is asserted.

13. The integrated circuit of claim 11 wherein said data stored in said memory cache is updated from said random access memory array prior to being placed on said data bus if said address indicated in said last row read register does not correspond to said row address signal portion of said address signal when said row enable signal is asserted.

14. The integrated circuit of claim 13 wherein said updated data stored in said memory cache is placed on said data bus in response to said column address portion of said address signal when said row enable signal is de-asserted.

15. The integrated circuit of claim 14 further comprising a refresh counter responsive to said row address and refresh control circuit, said row address and refresh control circuit being responsive to a refresh signal and coupled to said random access memory array for refreshing said random access memory array while said updated data stored in said memory cache is placed on said data bus.

16. An integrated circuit memory device, comprising:

a dynamic random access memory array;

a single row decoder;

a single column decoder responsive to an externally supplied address signal on an address bus for accessing a specified subset of memory cells within said memory array,

said address signal including row and column address portions and said memory device further including a data bus for providing a signal indicative of data associated with said specified subset of memory cells;

a static random access memory cache associated with said memory array and interposed between said single column decoder and said memory array, wherein corresponding locations in rows of both said memory cache and memory array may be addressed by said single column decoder, said memory cache for storing a row of said data associated with said specified subset of memory cells last accessed from said memory device;

a row address circuit for operatively controlling said memory cache and a row address latch circuit coupled between said address bus and said single row decoder, said row address circuit responsive to an externally applied row enable signal; and

a column address latch circuit coupled between said address bus and said single column decoder, said column address latch circuit responsive to an externally applied column address latch signal;

whereby said row address portion of said address signal may be entered into said row address latch circuit in response to a single transition of said row enable signal and the data stored in said memory cache may be placed on said data bus by supplying said column address portion of said address signal on said address bus without transitioning said column address latch signal;

said memory cache and said memory array being configured so that all reads from said memory device are only from said memory cache.

17. The memory device of claim 16 further comprising:

a refresh control circuit responsive to an externally applied refresh signal for refreshing said memory array.

18. The memory device of claim 17 wherein said refresh control circuit is further responsive to said externally supplied row enable signal.

19. The memory device of claim 17 wherein said data stored in said memory cache may be placed on said data bus while said refresh control circuit refreshes said memory array.

20. The memory device of claim 16 further comprising:

a write/read control circuit associated with said row address circuit and responsive to an externally applied write/read signal for determining whether data on said data bus will be written to said memory array to said specified subset of memory cells or data in said specified subset of memory cells will be placed on said data bus.

21. The memory device of claim 20 further comprising:

an input/output control circuit responsive to an externally applied write enable signal and having an internal input and output bus coupled thereto, said input bus being coupled to an output of said memory cache; and

a column write select circuit coupled between said memory cache and said memory array and coupled to said output bus of said input/output control circuit, said input/output control circuit being operative in conjunction with said write/read control circuit to write data applied on said data bus to said specified subset of memory cells of said memory array.

22. The memory device of claim 21 wherein said data applied on said data bus may also be concurrently written to said memory cache.

23. The memory device of claim 22 wherein said data is written to said memory cache if said row address portion of said address signal is indicative of a row of data currently stored in said memory cache.

24. The memory device of claim 21 further comprising:

a data latch associated with said input/output control circuit for latching said write data applied on said data bus in response to said write enable signal and wherein said column address portion of said address signal may be asynchronously latched in said column address latch circuit in response to said column address latch signal.

25. The memory device of claim 16 further comprising:

a last row read register coupled to said address bus for indicating said row address portion of said address signal corresponding to said data currently stored in said memory cache; and

a comparator associated with said address bus and said last row read register for causing said contents of said memory cache to be directed to said data bus if said row address portion of said address signal corresponds to said row address of said data currently stored in said last row read register.

26. An integrated circuit memory device, comprising:

a dynamic random access memory array having a single row decoder;

a single column decoder responsive to an externally supplied address signal on an address bus for accessing a specified subset of memory cells within said memory array;

said memory device further including a bidirectional data bus for providing a signal indicative of data associated with said specified subset of memory cells;

an input/output control and data latch circuit responsive to an externally applied write enable signal, said input/output control and data latch circuit being coupled to said data bus and having input and output busses thereof; and

a memory cache coupled to said input bus and an associated column write select circuit, said memory cache being coupled to said output bus and interposed between said single column decoder and said memory array, wherein corresponding locations in rows of both said memory cache and memory array may be addressed by said single column decoder, said memory cache for storing a row of said data associated with said specified subset of memory cells last accessed from said memory device;

wherein data read from said memory device is read out of said memory cache only and data written to said memory device is written to said memory array.

27. The integrated circuit of claim 26 whereby said data read out of said memory cache is loaded thereto from said memory array.

28. The integrated circuit of claim 26 wherein said memory device allows data latched in said input/output control and data latch circuit to be written to said memory array substantially concurrently with a read out of said data stored in said memory cache to said data bus.

29. The integrated circuit of claim 26 wherein said data written to said memory array and said data read out of said memory cache are multiplexed on said data bus.

30. The integrated circuit of claim 26 wherein said column write select circuit further allows data latched in said input/output control and data latch circuit to be also written to said memory cache substantially concurrently with writing to said memory array.

31. The integrated circuit of claim 30 whereby said data is also written to said memory cache when said portion of data associated with said specified subset of memory cells stored in said cache memory corresponds to a row of said memory array to be written.

32. The integrated circuit of claim 26 further comprising:

a row address circuit for operatively controlling said memory cache and a row address latch circuit coupled between said address bus and said single row decoder, said row address circuit responsive to an externally applied row enable signal; and

a column address latch circuit coupled between said address bus and said single column decoder, said column address latch circuit responsive to an externally applied column address latch signal;

whereby a row address portion of said address signal may be entered into said row address latch circuit in response to a single transition of said row enable signal and said data stored in said memory cache may be placed on said data bus by supplying a column address portion of said address signal on said address bus without transitioning said column address latch signal.

33. The memory device of claim 32 further comprising:

a last row read register coupled to said address bus for indicating said row address portion of said address signal corresponding to said data currently stored in said memory cache; and

a comparator associated with said address bus and said last row read register for causing said contents of said memory cache to be directed to said data bus if said row address portion of said address signal corresponds to said row address of said data currently stored in said last row read register.

34. The memory device of claim 32 further comprising:

a refresh control circuit responsive to an externally applied refresh signal for refreshing said memory array.

35. The memory device of claim 33 wherein said refresh control circuit is further responsive to said externally supplied row enable signal.

36. The memory device of claim 34 wherein said data stored in said memory cache may be placed on said data bus while said refresh control circuit refreshes said memory array.