Method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping barrier/eureka synchronization partitions are available simultaneously through the use of a plurality of parallel barrier/eureka synchronization domains. The present barrier/eureka mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes.
A debugging method and apparatus for multitask programs, and a recording medium storing a program used for realization of the debugging method and apparatus enable each of arbitrarily-selected tasks to be stopped at an arbitrary target program position. A plurality of barrier synchronization points are set. Each of the barrier synchronization points groups a break point set for each of a plurality of tasks. A barrier synchronization point which includes a break point that has first stopped a corresponding task is specified. Tasks having breakpoints belonging to the specified barrier synchronization point are sequentially stopped at the respective breakpoints. When all the tasks have stopped, the suspended tasks are brought back to an executable state.
A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.
A parallel computer system capable of arbitrarily selecting nodes participating in barrier synchronization while enabling an arbitrary number of node groups to independently execute a process requiring the barrier synchronization. A communication network for the parallel computer system includes a plurality of routing controllers. Each routing controller has a register for setting a predetermined number of receipts of barrier synchronization request messages from other routing controllers, a destination to which the barrier synchronization request message is transmitted, and a destination to which a barrier synchronization establishment message is transmitted. If a destination of transmission of the barrier synchronization request message is set when completing a predetermined number of receipts of the barrier synchronization request messages and receipts of a barrier synchronization request message from a self-node, the barrier synchronization request message is transmitted to that destination of transmission. If the transmission destination is not set, the barrier synchronization establishment message is transmitted to the set transmission destination of the barrier synchronization establishment message. When receiving the barrier synchronization establishment message, the barrier synchronization establishment message is also transmitted to the set transmission destination of the barrier synchronization establishment message.
A data processing arrangement comprises various data processors (P) and a memory arrangement (MA) for supplying input data (Di) to the data processors (P) and for storing output data (Do) from the data processors (P). The following steps are alternately carried out: a configuring step (CS) and a processing step (PS). In a configuration step (CS), the data processing arrangement is configured such that each data processor (P) will process a block (B) of data contained in the memory arrangement (MA) and then stop processing data. In a processing step (PS), the blocks (B) of data are processed in the respective data processors (P). A subsequent configuring step (CS) is carried out only when each data processor (P) has processed its block (B) of data (.A-inverted.P: B=PROC>CS). Such a data processing arrangement allows great versatility because different data processing chains can be realized without this requiring relatively complicated software.
A data structure supporting a data-parallel reduction operation performed by a group of threads, a rope, participating in a multi-level two-phase tree structure: a fan-in computation phase followed by a fan-out broadcast phase. Local reductions are performed at each subtree during the fan-in phase, and the final reduced value is broadcast to all the threads during the fan-out phase. As the reduction operation is a data-parallel operation, the reduction operation is rope specific and is provided by the use of a parallel computation skeleton defined by the data structure which is a fan-in followed by the fan-out, a data-type specific binary operation, and a final broadcast that takes place in the reduction operation. When the rope object is constructed, the parallel computation skeleton is automatically constructed from information contained in the data structure. When a reduction operation is invoked, this parallel computation skeleton is used to build a data-type specific reduction object which is used by all the threads in the rope. The threads in a rope may perform type-specific reduction operations by cloning this parallel computation skeleton to a data-type specific reduction object for that type. This data-type specific reduction object is an instance of a template instance which is parametrized on two data-types: a data-type of the values used in the reduction operation and a type of a binary operation function object.
